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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2s.h @ 746:7e84ae1513b6

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Code cleanup sensors under development: Deactivated compile option for Sentinel and CO2 sensor. Added missing compile switches.
author Ideenmodellierer
date Tue, 21 Feb 2023 21:19:31 +0100
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_i2s.h
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4 * @author MCD Application Team
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5 * @brief Header file of I2S HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_I2S_H
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38 #define __STM32F4xx_HAL_I2S_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup I2S I2S
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56 /** @defgroup I2S_Exported_Types I2S Exported Types
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57 * @{
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58 */
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59
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60 /**
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61 * @brief I2S Init structure definition
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62 */
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63 typedef struct
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64 {
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65 uint32_t Mode; /*!< Specifies the I2S operating mode.
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66 This parameter can be a value of @ref I2S_Mode */
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67
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68 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
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69 This parameter can be a value of @ref I2S_Standard */
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70
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71 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
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72 This parameter can be a value of @ref I2S_Data_Format */
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73
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74 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
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75 This parameter can be a value of @ref I2S_MCLK_Output */
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76
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77 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
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78 This parameter can be a value of @ref I2S_Audio_Frequency */
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79
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80 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
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81 This parameter can be a value of @ref I2S_Clock_Polarity */
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82
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83 uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
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84 This parameter can be a value of @ref I2S_Clock_Source */
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85
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86 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
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87 This parameter can be a value of @ref I2S_FullDuplex_Mode */
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88
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89 }I2S_InitTypeDef;
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90
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91 /**
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92 * @brief HAL State structures definition
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93 */
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94 typedef enum
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95 {
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96 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
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97 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
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98 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
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99 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
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100 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
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101 HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
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102 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
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103 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
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104
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105 }HAL_I2S_StateTypeDef;
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106
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107 /**
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108 * @brief I2S handle Structure definition
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109 */
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110 typedef struct __I2S_HandleTypeDef
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111 {
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112 SPI_TypeDef *Instance; /*!< I2S registers base address */
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113
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114 I2S_InitTypeDef Init; /*!< I2S communication parameters */
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115
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116 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
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117
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118 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
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119
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120 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
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121
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122 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
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123
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124 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
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125
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126 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
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127 (This field is initialized at the
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128 same value as transfer size at the
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129 beginning of the transfer and
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130 decremented when a sample is received
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131 NbSamplesReceived = RxBufferSize-RxBufferCount) */
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132
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133 void (*IrqHandlerISR) (struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
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134
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135 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
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136
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137 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
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138
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139 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
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140
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141 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
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142
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143 __IO uint32_t ErrorCode; /*!< I2S Error code
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144 This parameter can be a value of @ref I2S_ErrorCode */
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145
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146 }I2S_HandleTypeDef;
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147 /**
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148 * @}
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149 */
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150
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151 /* Exported constants --------------------------------------------------------*/
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152 /** @defgroup I2S_Exported_Constants I2S Exported Constants
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153 * @{
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154 */
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155 /**
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156 * @defgroup I2S_ErrorCode I2S Error Code
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157 * @{
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158 */
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159 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
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160 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
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161 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
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162 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
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163 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
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164 #define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
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165 /**
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166 * @}
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167 */
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168
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169 /** @defgroup I2S_Mode I2S Mode
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170 * @{
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171 */
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172 #define I2S_MODE_SLAVE_TX (0x00000000U)
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173 #define I2S_MODE_SLAVE_RX (0x00000100U)
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174 #define I2S_MODE_MASTER_TX (0x00000200U)
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175 #define I2S_MODE_MASTER_RX (0x00000300U)
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176 /**
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177 * @}
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178 */
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179
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180 /** @defgroup I2S_Standard I2S Standard
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181 * @{
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182 */
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183 #define I2S_STANDARD_PHILIPS (0x00000000U)
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184 #define I2S_STANDARD_MSB (0x00000010U)
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185 #define I2S_STANDARD_LSB (0x00000020U)
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186 #define I2S_STANDARD_PCM_SHORT (0x00000030U)
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187 #define I2S_STANDARD_PCM_LONG (0x000000B0U)
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188 /**
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189 * @}
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190 */
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191
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192 /** @defgroup I2S_Data_Format I2S Data Format
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193 * @{
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194 */
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195 #define I2S_DATAFORMAT_16B (0x00000000U)
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196 #define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
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197 #define I2S_DATAFORMAT_24B (0x00000003U)
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198 #define I2S_DATAFORMAT_32B (0x00000005U)
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199 /**
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200 * @}
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201 */
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202
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203 /** @defgroup I2S_MCLK_Output I2S Mclk Output
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204 * @{
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205 */
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206 #define I2S_MCLKOUTPUT_ENABLE SPI_I2SPR_MCKOE
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207 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
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208 /**
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209 * @}
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210 */
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211
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212 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
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213 * @{
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214 */
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215 #define I2S_AUDIOFREQ_192K (192000U)
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216 #define I2S_AUDIOFREQ_96K (96000U)
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217 #define I2S_AUDIOFREQ_48K (48000U)
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218 #define I2S_AUDIOFREQ_44K (44100U)
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219 #define I2S_AUDIOFREQ_32K (32000U)
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220 #define I2S_AUDIOFREQ_22K (22050U)
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221 #define I2S_AUDIOFREQ_16K (16000U)
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222 #define I2S_AUDIOFREQ_11K (11025U)
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223 #define I2S_AUDIOFREQ_8K (8000U)
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224 #define I2S_AUDIOFREQ_DEFAULT (2U)
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225 /**
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226 * @}
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227 */
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228
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229 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
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230 * @{
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231 */
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232 #define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
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233 #define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
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234 /**
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235 * @}
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236 */
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237
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238 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
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239 * @{
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240 */
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241 #define I2S_CPOL_LOW (0x00000000U)
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242 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
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243 /**
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244 * @}
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245 */
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246
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247 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
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248 * @{
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249 */
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250 #define I2S_IT_TXE SPI_CR2_TXEIE
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251 #define I2S_IT_RXNE SPI_CR2_RXNEIE
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252 #define I2S_IT_ERR SPI_CR2_ERRIE
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253 /**
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254 * @}
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255 */
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256
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257 /** @defgroup I2S_Flags_Definition I2S Flags Definition
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258 * @{
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259 */
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260 #define I2S_FLAG_TXE SPI_SR_TXE
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261 #define I2S_FLAG_RXNE SPI_SR_RXNE
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262
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263 #define I2S_FLAG_UDR SPI_SR_UDR
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264 #define I2S_FLAG_OVR SPI_SR_OVR
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265 #define I2S_FLAG_FRE SPI_SR_FRE
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266
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267 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
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268 #define I2S_FLAG_BSY SPI_SR_BSY
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269 /**
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270 * @}
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271 */
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272 /** @defgroup I2S_Clock_Source I2S Clock Source Definition
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273 * @{
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274 */
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275 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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276 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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277 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
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278 defined(STM32F479xx)
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279 #define I2S_CLOCK_PLL (0x00000000U)
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280 #define I2S_CLOCK_EXTERNAL (0x00000001U)
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281 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
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282 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
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283
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284 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
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285 defined(STM32F413xx) || defined(STM32F423xx)
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286 #define I2S_CLOCK_PLL (0x00000000U)
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287 #define I2S_CLOCK_EXTERNAL (0x00000001U)
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288 #define I2S_CLOCK_PLLR (0x00000002U)
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289 #define I2S_CLOCK_PLLSRC (0x00000003U)
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290 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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291
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292 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
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293 #define I2S_CLOCK_PLLSRC (0x00000000U)
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294 #define I2S_CLOCK_EXTERNAL (0x00000001U)
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295 #define I2S_CLOCK_PLLR (0x00000002U)
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296 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
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297 /**
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298 * @}
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299 */
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300
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301 /**
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302 * @}
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303 */
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304
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305 /* Exported macro ------------------------------------------------------------*/
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306 /** @defgroup I2S_Exported_Macros I2S Exported Macros
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307 * @{
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308 */
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309
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310 /** @brief Reset I2S handle state
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311 * @param __HANDLE__ specifies the I2S Handle.
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312 * @retval None
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313 */
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314 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
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315
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316 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
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317 * @param __HANDLE__ specifies the I2S Handle.
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318 * @retval None
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319 */
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320 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
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321 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &=(uint16_t)(~SPI_I2SCFGR_I2SE))
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322
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323 /** @brief Enable or disable the specified I2S interrupts.
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324 * @param __HANDLE__ specifies the I2S Handle.
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325 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
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326 * This parameter can be one of the following values:
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327 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
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328 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
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329 * @arg I2S_IT_ERR: Error interrupt enable
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330 * @retval None
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331 */
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332 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
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333 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &=(uint16_t)(~(__INTERRUPT__)))
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334
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335 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
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336 * @param __HANDLE__ specifies the I2S Handle.
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337 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
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338 * @param __INTERRUPT__ specifies the I2S interrupt source to check.
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339 * This parameter can be one of the following values:
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340 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
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341 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
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342 * @arg I2S_IT_ERR: Error interrupt enable
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343 * @retval The new state of __IT__ (TRUE or FALSE).
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344 */
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345 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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346
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347 /** @brief Checks whether the specified I2S flag is set or not.
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348 * @param __HANDLE__ specifies the I2S Handle.
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349 * @param __FLAG__ specifies the flag to check.
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350 * This parameter can be one of the following values:
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351 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
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352 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
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353 * @arg I2S_FLAG_UDR: Underrun flag
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354 * @arg I2S_FLAG_OVR: Overrun flag
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355 * @arg I2S_FLAG_FRE: Frame error flag
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356 * @arg I2S_FLAG_CHSIDE: Channel Side flag
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357 * @arg I2S_FLAG_BSY: Busy flag
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358 * @retval The new state of __FLAG__ (TRUE or FALSE).
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359 */
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360 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
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361
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362 /** @brief Clears the I2S OVR pending flag.
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363 * @param __HANDLE__ specifies the I2S Handle.
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364 * @retval None
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365 */
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366 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
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367 do{ \
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368 __IO uint32_t tmpreg = 0x00U; \
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369 tmpreg = (__HANDLE__)->Instance->DR; \
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370 tmpreg = (__HANDLE__)->Instance->SR; \
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371 UNUSED(tmpreg); \
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372 } while(0)
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373
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374 /** @brief Clears the I2S UDR pending flag.
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375 * @param __HANDLE__ specifies the I2S Handle.
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376 * @retval None
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377 */
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378 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
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379 do{ \
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380 __IO uint32_t tmpreg = 0x00U; \
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381 tmpreg = (__HANDLE__)->Instance->SR; \
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382 UNUSED(tmpreg); \
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383 } while(0)
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384 /**
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385 * @}
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386 */
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387
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388 /* Include I2S Extension module */
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389 #include "stm32f4xx_hal_i2s_ex.h"
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390
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391 /* Exported functions --------------------------------------------------------*/
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392 /** @defgroup I2S_Exported_Functions I2S Exported Functions
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393 * @{
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394 */
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395
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396 /** @defgroup I2S_Exported_Functions_Group1 I2S Initialization and de-initialization functions
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397 * @{
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398 */
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399 /* Initialization/de-initialization functions **********************************/
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400 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
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401 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
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402 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
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403 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
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404 /**
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405 * @}
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406 */
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407
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408 /** @defgroup I2S_Exported_Functions_Group2 I2S IO operation functions
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409 * @{
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410 */
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411 /* I/O operation functions *****************************************************/
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412 /* Blocking mode: Polling */
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413 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
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414 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
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415
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416 /* Non-Blocking mode: Interrupt */
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417 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
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418 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
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419 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
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420
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421 /* Non-Blocking mode: DMA */
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422 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
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423 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
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424
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425 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
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426 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
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427 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
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428
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429 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
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430 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
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431 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
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432 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
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433 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
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434 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
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435 /**
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436 * @}
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437 */
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438
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439 /** @defgroup I2S_Exported_Functions_Group3 I2S Peripheral Control and State functions
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440 * @{
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441 */
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442 /* Peripheral Control and State functions ************************************/
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443 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
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444 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
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445 /**
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446 * @}
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447 */
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448
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449 /**
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450 * @}
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451 */
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452
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453 /* Private types -------------------------------------------------------------*/
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454 /* Private variables ---------------------------------------------------------*/
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455 /* Private constants ---------------------------------------------------------*/
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456 /** @defgroup I2S_Private_Constants I2S Private Constants
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457 * @{
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458 */
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459
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460 /**
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461 * @}
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462 */
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463
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464 /* Private macros ------------------------------------------------------------*/
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465 /** @defgroup I2S_Private_Macros I2S Private Macros
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466 * @{
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467 */
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468 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
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469 ((MODE) == I2S_MODE_SLAVE_RX) || \
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470 ((MODE) == I2S_MODE_MASTER_TX) || \
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471 ((MODE) == I2S_MODE_MASTER_RX))
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472
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473 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
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474 ((STANDARD) == I2S_STANDARD_MSB) || \
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475 ((STANDARD) == I2S_STANDARD_LSB) || \
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476 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
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477 ((STANDARD) == I2S_STANDARD_PCM_LONG))
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478
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479 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
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480 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
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481 ((FORMAT) == I2S_DATAFORMAT_24B) || \
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482 ((FORMAT) == I2S_DATAFORMAT_32B))
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483
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484 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
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485 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
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486
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487 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
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488 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
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489 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
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490
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491 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
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492 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
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493
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494 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
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495 ((CPOL) == I2S_CPOL_HIGH))
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496
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497 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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498 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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499 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
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500 defined(STM32F479xx)
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501 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
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502 ((CLOCK) == I2S_CLOCK_PLL))
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503 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
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504 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
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505
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506 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
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507 defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) ||\
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508 defined(STM32F423xx)
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509 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
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510 ((CLOCK) == I2S_CLOCK_PLL) ||\
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511 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
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512 ((CLOCK) == I2S_CLOCK_PLLR))
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513 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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514
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515 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
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516 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\
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517 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\
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518 ((CLOCK) == I2S_CLOCK_PLLR))
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519 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
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520
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521 /**
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522 * @}
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523 */
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524
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525 /* Private functions ---------------------------------------------------------*/
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526 /**
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527 * @}
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528 */
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529
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530 /**
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531 * @}
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532 */
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533
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534 #ifdef __cplusplus
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535 }
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536 #endif
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537
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538
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539 #endif /* __STM32F4xx_HAL_I2S_H */
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540
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541 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/