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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f411xe.h
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief CMSIS STM32F411xExx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral’s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32f401xe
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49 * @{
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50 */
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51
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52 #ifndef __STM32F401xE_H
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53 #define __STM32F401xE_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59
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60 /** @addtogroup Configuration_section_for_CMSIS
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61 * @{
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62 */
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63
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64 /**
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65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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66 */
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67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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71 #define __FPU_PRESENT 1 /*!< FPU present */
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72
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73 /**
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74 * @}
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75 */
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76
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77 /** @addtogroup Peripheral_interrupt_number_definition
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78 * @{
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79 */
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80
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81 /**
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82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
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83 * in @ref Library_configuration_section
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84 */
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85 typedef enum
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86 {
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87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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96 /****** STM32 specific Interrupt Numbers **********************************************************************/
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97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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102 RCC_IRQn = 5, /*!< RCC global Interrupt */
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103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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148 USART6_IRQn = 71, /*!< USART6 global interrupt */
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149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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151 FPU_IRQn = 81, /*!< FPU global interrupt */
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152 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
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153 SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
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154 } IRQn_Type;
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155
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156 /**
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157 * @}
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158 */
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159
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160 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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161 #include "system_stm32f4xx.h"
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162 #include <stdint.h>
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163
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164 /** @addtogroup Peripheral_registers_structures
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165 * @{
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166 */
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167
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168 /**
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169 * @brief Analog to Digital Converter
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170 */
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171
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172 typedef struct
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173 {
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174 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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175 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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176 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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177 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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178 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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179 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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180 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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181 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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182 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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183 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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184 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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185 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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186 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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187 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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188 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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189 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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190 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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191 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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192 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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193 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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194 } ADC_TypeDef;
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195
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196 typedef struct
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197 {
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198 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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199 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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200 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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201 AND triple modes, Address offset: ADC1 base address + 0x308 */
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202 } ADC_Common_TypeDef;
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203
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204 /**
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205 * @brief CRC calculation unit
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206 */
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207
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208 typedef struct
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209 {
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210 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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211 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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212 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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213 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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214 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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215 } CRC_TypeDef;
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216
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217 /**
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218 * @brief Debug MCU
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219 */
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220
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221 typedef struct
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222 {
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223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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227 }DBGMCU_TypeDef;
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228
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229
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230 /**
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231 * @brief DMA Controller
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232 */
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233
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234 typedef struct
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235 {
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236 __IO uint32_t CR; /*!< DMA stream x configuration register */
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237 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
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238 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
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239 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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240 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
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241 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
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242 } DMA_Stream_TypeDef;
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243
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244 typedef struct
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245 {
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246 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
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247 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
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248 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
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249 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
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250 } DMA_TypeDef;
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251
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252
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253 /**
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254 * @brief External Interrupt/Event Controller
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255 */
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256
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257 typedef struct
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258 {
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259 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
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260 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
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261 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
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262 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
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263 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
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264 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
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265 } EXTI_TypeDef;
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266
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267 /**
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268 * @brief FLASH Registers
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269 */
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270
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271 typedef struct
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272 {
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273 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
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274 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
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275 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
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276 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
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277 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
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278 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
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279 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
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280 } FLASH_TypeDef;
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281
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282 /**
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283 * @brief General Purpose I/O
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284 */
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285
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286 typedef struct
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287 {
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288 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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289 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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290 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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291 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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292 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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293 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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294 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
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295 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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296 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
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297 } GPIO_TypeDef;
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298
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299 /**
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300 * @brief System configuration controller
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301 */
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302
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303 typedef struct
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304 {
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305 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
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306 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
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307 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
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308 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
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309 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
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310 } SYSCFG_TypeDef;
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311
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312 /**
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313 * @brief Inter-integrated Circuit Interface
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314 */
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315
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316 typedef struct
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317 {
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318 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
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319 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
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320 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
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321 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
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322 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
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323 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
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324 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
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325 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
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326 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
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327 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
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328 } I2C_TypeDef;
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329
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330 /**
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331 * @brief Independent WATCHDOG
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332 */
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333
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334 typedef struct
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335 {
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336 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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337 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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338 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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339 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
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340 } IWDG_TypeDef;
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341
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342 /**
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343 * @brief Power Control
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344 */
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345
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346 typedef struct
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347 {
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348 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
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349 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
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350 } PWR_TypeDef;
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351
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352 /**
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353 * @brief Reset and Clock Control
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354 */
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355
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356 typedef struct
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357 {
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358 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
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359 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
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360 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
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361 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
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362 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
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363 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
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364 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
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365 uint32_t RESERVED0; /*!< Reserved, 0x1C */
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366 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
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367 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
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368 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
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369 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
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370 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
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371 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
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372 uint32_t RESERVED2; /*!< Reserved, 0x3C */
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373 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
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374 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
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375 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
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376 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
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377 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
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378 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
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379 uint32_t RESERVED4; /*!< Reserved, 0x5C */
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380 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
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381 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
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382 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
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383 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
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384 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
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385 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
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386 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
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387 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
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388
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389 } RCC_TypeDef;
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390
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391 /**
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392 * @brief Real-Time Clock
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393 */
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394
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395 typedef struct
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396 {
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397 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
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398 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
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399 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
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400 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
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401 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
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402 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
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403 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
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404 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
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405 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
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406 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
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407 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
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408 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
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409 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
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410 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
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411 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
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412 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
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413 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
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414 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
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415 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
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416 uint32_t RESERVED7; /*!< Reserved, 0x4C */
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417 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
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418 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
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419 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
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420 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
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421 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
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422 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
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423 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
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424 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
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425 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
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426 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
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427 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
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428 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
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429 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
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430 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
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431 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
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432 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
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433 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
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434 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
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435 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
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|
436 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
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|
|
437 } RTC_TypeDef;
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|
|
438
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|
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439
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|
|
440 /**
|
|
|
441 * @brief SD host Interface
|
|
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442 */
|
|
|
443
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|
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444 typedef struct
|
|
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445 {
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446 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
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447 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
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448 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
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449 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
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450 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
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451 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
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|
|
452 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
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|
453 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
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454 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
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455 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
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456 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
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457 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
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458 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
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459 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
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460 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
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461 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
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462 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
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463 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
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464 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
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465 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
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466 } SDIO_TypeDef;
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467
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468 /**
|
|
|
469 * @brief Serial Peripheral Interface
|
|
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470 */
|
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471
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|
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472 typedef struct
|
|
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473 {
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474 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
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475 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
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476 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
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|
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477 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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478 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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479 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
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|
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480 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
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|
481 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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|
482 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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|
|
483 } SPI_TypeDef;
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|
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484
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|
|
485 /**
|
|
|
486 * @brief TIM
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|
|
487 */
|
|
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488
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|
|
489 typedef struct
|
|
|
490 {
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491 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
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492 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
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|
|
493 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
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|
494 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
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495 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
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|
496 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
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|
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497 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
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498 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
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|
|
499 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
500 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
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|
|
501 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
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|
|
502 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
503 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
504 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
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|
|
505 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
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|
|
506 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
507 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
508 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
509 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
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|
|
510 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
511 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
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|
|
512 } TIM_TypeDef;
|
|
|
513
|
|
|
514 /**
|
|
|
515 * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
516 */
|
|
|
517
|
|
|
518 typedef struct
|
|
|
519 {
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|
|
520 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
|
|
|
521 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
|
|
|
522 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
|
|
|
523 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
|
|
|
524 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
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|
|
525 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
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|
|
526 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
|
|
|
527 } USART_TypeDef;
|
|
|
528
|
|
|
529 /**
|
|
|
530 * @brief Window WATCHDOG
|
|
|
531 */
|
|
|
532
|
|
|
533 typedef struct
|
|
|
534 {
|
|
|
535 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
536 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
537 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
538 } WWDG_TypeDef;
|
|
|
539
|
|
|
540
|
|
|
541 /**
|
|
|
542 * @brief __USB_OTG_Core_register
|
|
|
543 */
|
|
|
544 typedef struct
|
|
|
545 {
|
|
|
546 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
|
|
|
547 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
|
|
|
548 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
|
|
|
549 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
|
|
|
550 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
|
|
|
551 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
|
|
|
552 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
|
|
|
553 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
|
|
|
554 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
|
|
|
555 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
|
|
|
556 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
|
|
|
557 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
|
|
|
558 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
|
|
|
559 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
|
|
|
560 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
|
|
|
561 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
|
|
|
562 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
|
|
|
563 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
|
|
|
564 }
|
|
|
565 USB_OTG_GlobalTypeDef;
|
|
|
566
|
|
|
567
|
|
|
568
|
|
|
569 /**
|
|
|
570 * @brief __device_Registers
|
|
|
571 */
|
|
|
572 typedef struct
|
|
|
573 {
|
|
|
574 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
|
|
|
575 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
|
|
|
576 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
|
|
|
577 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
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|
|
578 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
|
|
|
579 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
|
|
|
580 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
|
|
|
581 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
|
|
|
582 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
|
|
|
583 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
|
|
|
584 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
|
|
|
585 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
|
|
|
586 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
|
|
|
587 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
|
|
|
588 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
|
|
|
589 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
|
|
|
590 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
|
|
|
591 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
|
|
|
592 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
|
|
|
593 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
|
|
|
594 }
|
|
|
595 USB_OTG_DeviceTypeDef;
|
|
|
596
|
|
|
597
|
|
|
598 /**
|
|
|
599 * @brief __IN_Endpoint-Specific_Register
|
|
|
600 */
|
|
|
601 typedef struct
|
|
|
602 {
|
|
|
603 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
|
|
|
604 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
|
|
|
605 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
|
|
|
606 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
|
|
|
607 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
|
|
|
608 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
|
|
|
609 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
|
|
|
610 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
|
|
|
611 }
|
|
|
612 USB_OTG_INEndpointTypeDef;
|
|
|
613
|
|
|
614
|
|
|
615 /**
|
|
|
616 * @brief __OUT_Endpoint-Specific_Registers
|
|
|
617 */
|
|
|
618 typedef struct
|
|
|
619 {
|
|
|
620 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
|
|
|
621 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
|
|
|
622 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
|
|
|
623 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
|
|
|
624 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
|
|
|
625 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
|
|
|
626 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
|
|
|
627 }
|
|
|
628 USB_OTG_OUTEndpointTypeDef;
|
|
|
629
|
|
|
630
|
|
|
631 /**
|
|
|
632 * @brief __Host_Mode_Register_Structures
|
|
|
633 */
|
|
|
634 typedef struct
|
|
|
635 {
|
|
|
636 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
|
|
|
637 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
|
|
|
638 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
|
|
|
639 uint32_t Reserved40C; /* Reserved 40Ch*/
|
|
|
640 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
|
|
|
641 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
|
|
|
642 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
|
|
|
643 }
|
|
|
644 USB_OTG_HostTypeDef;
|
|
|
645
|
|
|
646
|
|
|
647 /**
|
|
|
648 * @brief __Host_Channel_Specific_Registers
|
|
|
649 */
|
|
|
650 typedef struct
|
|
|
651 {
|
|
|
652 __IO uint32_t HCCHAR;
|
|
|
653 __IO uint32_t HCSPLT;
|
|
|
654 __IO uint32_t HCINT;
|
|
|
655 __IO uint32_t HCINTMSK;
|
|
|
656 __IO uint32_t HCTSIZ;
|
|
|
657 __IO uint32_t HCDMA;
|
|
|
658 uint32_t Reserved[2];
|
|
|
659 }
|
|
|
660 USB_OTG_HostChannelTypeDef;
|
|
|
661
|
|
|
662
|
|
|
663 /**
|
|
|
664 * @brief Peripheral_memory_map
|
|
|
665 */
|
|
|
666 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
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|
|
667 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
|
|
668 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
|
|
669 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
|
|
670 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
|
|
671 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
|
|
672 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
|
|
673 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
|
|
674 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
|
|
675 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
|
|
676 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
|
|
677 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
|
|
678 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
|
|
|
679 #define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
|
|
|
680
|
|
|
681 /* Legacy defines */
|
|
|
682 #define SRAM_BASE SRAM1_BASE
|
|
|
683 #define SRAM_BB_BASE SRAM1_BB_BASE
|
|
|
684
|
|
|
685
|
|
|
686 /*!< Peripheral memory map */
|
|
|
687 #define APB1PERIPH_BASE PERIPH_BASE
|
|
|
688 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
|
|
|
689 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
|
|
|
690 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
|
|
|
691
|
|
|
692 /*!< APB1 peripherals */
|
|
|
693 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
|
|
|
694 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
|
|
|
695 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
|
|
|
696 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
|
|
697 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
|
|
698 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
|
|
699 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
|
|
700 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
|
|
|
701 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
|
|
702 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
|
|
703 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
|
|
|
704 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
|
|
705 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
|
|
706 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
|
|
707 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
|
|
|
708 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
|
|
709
|
|
|
710 /*!< APB2 peripherals */
|
|
|
711 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
|
|
|
712 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
|
|
|
713 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
|
|
|
714 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
|
|
|
715 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
|
|
|
716 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
|
|
|
717 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
|
|
718 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
|
|
|
719 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
|
|
|
720 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
|
|
|
721 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
|
|
|
722 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
|
|
|
723 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
|
|
|
724 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
|
|
|
725
|
|
|
726 /*!< AHB1 peripherals */
|
|
|
727 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
|
|
|
728 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
|
|
|
729 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
|
|
|
730 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
|
|
|
731 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
|
|
|
732 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
|
|
|
733 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
|
|
|
734 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
|
|
|
735 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
|
|
|
736 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
|
|
|
737 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
|
|
|
738 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
|
|
|
739 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
|
|
|
740 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
|
|
|
741 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
|
|
|
742 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
|
|
|
743 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
|
|
|
744 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
|
|
|
745 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
|
|
|
746 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
|
|
|
747 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
|
|
|
748 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
|
|
|
749 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
|
|
|
750 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
|
|
|
751 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
|
|
|
752 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
|
|
|
753 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
|
|
|
754
|
|
|
755 /* Debug MCU registers base address */
|
|
|
756 #define DBGMCU_BASE ((uint32_t )0xE0042000)
|
|
|
757
|
|
|
758 /*!< USB registers base address */
|
|
|
759 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
|
|
|
760
|
|
|
761 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
|
|
|
762 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
|
|
|
763 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
|
|
|
764 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
|
|
|
765 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
|
|
|
766 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
|
|
|
767 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
|
|
|
768 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
|
|
|
769 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
|
|
|
770 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
|
|
|
771 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
|
|
|
772 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
|
|
|
773
|
|
|
774 /**
|
|
|
775 * @}
|
|
|
776 */
|
|
|
777
|
|
|
778 /** @addtogroup Peripheral_declaration
|
|
|
779 * @{
|
|
|
780 */
|
|
|
781 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
|
|
|
782 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
|
|
|
783 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
|
|
|
784 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
|
|
785 #define RTC ((RTC_TypeDef *) RTC_BASE)
|
|
|
786 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
|
|
787 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
|
|
788 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
|
|
|
789 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
|
|
|
790 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
|
|
|
791 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
|
|
|
792 #define USART2 ((USART_TypeDef *) USART2_BASE)
|
|
|
793 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
|
|
|
794 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
|
|
|
795 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
|
|
|
796 #define PWR ((PWR_TypeDef *) PWR_BASE)
|
|
|
797 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
|
|
|
798 #define USART1 ((USART_TypeDef *) USART1_BASE)
|
|
|
799 #define USART6 ((USART_TypeDef *) USART6_BASE)
|
|
|
800 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
|
|
|
801 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
|
|
802 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
|
|
803 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
|
|
|
804 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
|
|
|
805 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
|
|
|
806 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
|
|
807 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
|
|
808 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
|
|
809 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
|
|
810 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
|
|
|
811 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
|
|
812 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
|
|
813 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
|
|
814 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
|
|
|
815 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
|
|
|
816 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
|
|
817 #define CRC ((CRC_TypeDef *) CRC_BASE)
|
|
|
818 #define RCC ((RCC_TypeDef *) RCC_BASE)
|
|
|
819 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
|
|
|
820 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
|
|
821 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
|
|
|
822 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
|
|
|
823 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
|
|
|
824 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
|
|
|
825 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
|
|
|
826 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
|
|
|
827 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
|
|
|
828 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
|
|
|
829 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
|
|
830 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
|
|
|
831 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
|
|
|
832 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
|
|
|
833 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
|
|
|
834 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
|
|
|
835 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
|
|
|
836 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
|
|
|
837 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
|
|
|
838
|
|
|
839 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
|
|
|
840
|
|
|
841 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
|
|
|
842
|
|
|
843 /**
|
|
|
844 * @}
|
|
|
845 */
|
|
|
846
|
|
|
847 /** @addtogroup Exported_constants
|
|
|
848 * @{
|
|
|
849 */
|
|
|
850
|
|
|
851 /** @addtogroup Peripheral_Registers_Bits_Definition
|
|
|
852 * @{
|
|
|
853 */
|
|
|
854
|
|
|
855 /******************************************************************************/
|
|
|
856 /* Peripheral Registers_Bits_Definition */
|
|
|
857 /******************************************************************************/
|
|
|
858
|
|
|
859 /******************************************************************************/
|
|
|
860 /* */
|
|
|
861 /* Analog to Digital Converter */
|
|
|
862 /* */
|
|
|
863 /******************************************************************************/
|
|
|
864 /******************** Bit definition for ADC_SR register ********************/
|
|
|
865 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
|
|
|
866 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
|
|
|
867 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
|
|
|
868 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
|
|
|
869 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
|
|
|
870 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
|
|
|
871
|
|
|
872 /******************* Bit definition for ADC_CR1 register ********************/
|
|
|
873 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
|
|
|
874 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
875 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
876 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
877 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
878 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
879 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
|
|
|
880 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
|
|
|
881 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
|
|
|
882 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
|
|
|
883 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
|
|
|
884 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
|
|
|
885 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
|
|
|
886 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
|
|
|
887 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
|
|
|
888 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
889 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
890 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
891 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
|
|
|
892 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
|
|
|
893 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
|
|
|
894 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
895 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
896 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
|
|
|
897
|
|
|
898 /******************* Bit definition for ADC_CR2 register ********************/
|
|
|
899 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
|
|
|
900 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
|
|
|
901 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
|
|
|
902 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
|
|
|
903 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
|
|
|
904 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
|
|
|
905 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
|
|
|
906 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
907 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
908 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
909 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
910 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
|
|
|
911 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
912 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
913 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
|
|
|
914 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
|
|
|
915 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
916 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
917 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
918 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
919 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
|
|
|
920 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
921 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
922 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
|
|
|
923
|
|
|
924 /****************** Bit definition for ADC_SMPR1 register *******************/
|
|
|
925 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
|
|
|
926 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
927 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
928 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
929 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
|
|
|
930 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
931 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
932 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
933 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
|
|
|
934 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
935 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
936 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
937 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
|
|
|
938 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
939 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
940 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
941 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
|
|
|
942 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
943 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
944 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
945 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
|
|
|
946 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
947 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
948 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
949 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
|
|
|
950 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
951 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
952 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
|
|
|
953 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
|
|
|
954 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
955 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
956 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
957 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
|
|
|
958 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
959 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
960 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
961
|
|
|
962 /****************** Bit definition for ADC_SMPR2 register *******************/
|
|
|
963 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
|
|
|
964 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
965 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
966 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
967 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
|
|
|
968 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
969 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
970 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
971 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
|
|
|
972 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
973 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
974 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
975 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
|
|
|
976 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
977 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
978 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
979 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
|
|
|
980 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
981 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
982 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
983 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
|
|
|
984 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
985 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
986 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
987 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
|
|
|
988 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
989 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
990 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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|
|
991 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
|
|
|
992 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
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|
|
993 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
994 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
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|
|
995 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
|
|
|
996 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
997 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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|
|
998 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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|
|
999 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
|
|
|
1000 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
|
|
|
1001 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
|
|
|
1002 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
|
|
|
1003
|
|
|
1004 /****************** Bit definition for ADC_JOFR1 register *******************/
|
|
|
1005 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
|
|
|
1006
|
|
|
1007 /****************** Bit definition for ADC_JOFR2 register *******************/
|
|
|
1008 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
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|
|
1009
|
|
|
1010 /****************** Bit definition for ADC_JOFR3 register *******************/
|
|
|
1011 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
|
|
|
1012
|
|
|
1013 /****************** Bit definition for ADC_JOFR4 register *******************/
|
|
|
1014 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
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|
|
1015
|
|
|
1016 /******************* Bit definition for ADC_HTR register ********************/
|
|
|
1017 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
|
|
|
1018
|
|
|
1019 /******************* Bit definition for ADC_LTR register ********************/
|
|
|
1020 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
|
|
|
1021
|
|
|
1022 /******************* Bit definition for ADC_SQR1 register *******************/
|
|
|
1023 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
|
|
|
1024 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1025 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1026 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1027 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1028 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1029 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
|
|
|
1030 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1031 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1032 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1033 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1034 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1035 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
|
|
|
1036 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1037 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1038 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1039 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1040 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1041 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
|
|
|
1042 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1043 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1044 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1045 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1046 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1047 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
|
|
|
1048 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1049 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1050 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1051 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1052
|
|
|
1053 /******************* Bit definition for ADC_SQR2 register *******************/
|
|
|
1054 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
|
|
|
1055 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1056 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1057 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1058 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1059 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1060 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
|
|
|
1061 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1062 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1063 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1064 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1065 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1066 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
|
|
|
1067 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1068 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1069 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1070 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1071 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1072 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
|
|
|
1073 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1074 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1075 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1076 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1077 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1078 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
|
|
|
1079 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1080 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1081 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1082 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1083 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
|
|
1084 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
|
|
|
1085 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1086 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1087 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1088 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1089 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
|
1090
|
|
|
1091 /******************* Bit definition for ADC_SQR3 register *******************/
|
|
|
1092 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
|
|
|
1093 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1094 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1095 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1096 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1097 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1098 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
|
|
|
1099 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1100 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1101 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1102 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1103 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1104 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
|
|
|
1105 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1106 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1107 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1108 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1109 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1110 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
|
|
|
1111 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1112 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1113 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1114 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1115 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1116 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
|
|
|
1117 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1118 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1119 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1120 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1121 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
|
|
1122 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
|
|
|
1123 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1124 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1125 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1126 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1127 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
|
1128
|
|
|
1129 /******************* Bit definition for ADC_JSQR register *******************/
|
|
|
1130 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
|
|
|
1131 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1132 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1133 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1134 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1135 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1136 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
|
|
|
1137 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1138 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1139 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1140 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1141 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1142 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
|
|
|
1143 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1144 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1145 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1146 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1147 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1148 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
|
|
|
1149 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1150 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1151 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1152 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1153 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1154 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
|
|
|
1155 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1156 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1157
|
|
|
1158 /******************* Bit definition for ADC_JDR1 register *******************/
|
|
|
1159 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1160
|
|
|
1161 /******************* Bit definition for ADC_JDR2 register *******************/
|
|
|
1162 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1163
|
|
|
1164 /******************* Bit definition for ADC_JDR3 register *******************/
|
|
|
1165 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1166
|
|
|
1167 /******************* Bit definition for ADC_JDR4 register *******************/
|
|
|
1168 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1169
|
|
|
1170 /******************** Bit definition for ADC_DR register ********************/
|
|
|
1171 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
|
|
|
1172 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
|
|
|
1173
|
|
|
1174 /******************* Bit definition for ADC_CSR register ********************/
|
|
|
1175 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
|
|
|
1176 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
|
|
|
1177 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
|
|
|
1178 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
|
|
|
1179 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
|
|
|
1180 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
|
|
|
1181 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
|
|
|
1182 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
|
|
|
1183 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
|
|
|
1184 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
|
|
|
1185 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
|
|
|
1186 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
|
|
|
1187 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
|
|
|
1188 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
|
|
|
1189 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
|
|
|
1190 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
|
|
|
1191 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
|
|
|
1192 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
|
|
|
1193
|
|
|
1194 /******************* Bit definition for ADC_CCR register ********************/
|
|
|
1195 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
|
|
|
1196 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1197 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1198 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1199 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1200 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1201 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
|
|
|
1202 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
1203 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
1204 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
1205 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
1206 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
|
|
|
1207 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
|
|
|
1208 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
1209 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
1210 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
|
|
|
1211 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1212 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1213 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
|
|
|
1214 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
|
|
|
1215
|
|
|
1216 /******************* Bit definition for ADC_CDR register ********************/
|
|
|
1217 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
|
|
|
1218 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
|
|
|
1219
|
|
|
1220 /******************************************************************************/
|
|
|
1221 /* */
|
|
|
1222 /* CRC calculation unit */
|
|
|
1223 /* */
|
|
|
1224 /******************************************************************************/
|
|
|
1225 /******************* Bit definition for CRC_DR register *********************/
|
|
|
1226 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
|
|
1227
|
|
|
1228
|
|
|
1229 /******************* Bit definition for CRC_IDR register ********************/
|
|
|
1230 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
|
|
1231
|
|
|
1232
|
|
|
1233 /******************** Bit definition for CRC_CR register ********************/
|
|
|
1234 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
|
|
|
1235
|
|
|
1236 /******************************************************************************/
|
|
|
1237 /* */
|
|
|
1238 /* Debug MCU */
|
|
|
1239 /* */
|
|
|
1240 /******************************************************************************/
|
|
|
1241
|
|
|
1242 /******************************************************************************/
|
|
|
1243 /* */
|
|
|
1244 /* DMA Controller */
|
|
|
1245 /* */
|
|
|
1246 /******************************************************************************/
|
|
|
1247 /******************** Bits definition for DMA_SxCR register *****************/
|
|
|
1248 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
|
|
|
1249 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
|
|
|
1250 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
|
|
|
1251 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
|
|
|
1252 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
|
|
|
1253 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
|
|
|
1254 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
|
|
|
1255 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
|
|
|
1256 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
|
|
|
1257 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
|
|
|
1258 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
|
|
|
1259 #define DMA_SxCR_CT ((uint32_t)0x00080000)
|
|
|
1260 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
|
|
|
1261 #define DMA_SxCR_PL ((uint32_t)0x00030000)
|
|
|
1262 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
|
|
|
1263 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
|
|
|
1264 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
|
|
|
1265 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
|
|
|
1266 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
|
|
|
1267 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
|
|
|
1268 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
|
|
|
1269 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
|
|
|
1270 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
|
|
|
1271 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
|
|
|
1272 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
|
|
|
1273 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
|
|
|
1274 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
|
|
|
1275 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
|
|
|
1276 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
|
|
|
1277 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
|
|
|
1278 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
|
|
|
1279 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
|
|
|
1280 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
|
|
|
1281 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
|
|
|
1282 #define DMA_SxCR_EN ((uint32_t)0x00000001)
|
|
|
1283
|
|
|
1284 /******************** Bits definition for DMA_SxCNDTR register **************/
|
|
|
1285 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
|
|
|
1286 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
|
|
|
1287 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
|
|
|
1288 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
|
|
|
1289 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
|
|
|
1290 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
|
|
|
1291 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
|
|
|
1292 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
|
|
|
1293 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
|
|
|
1294 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
|
|
|
1295 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
|
|
|
1296 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
|
|
|
1297 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
|
|
|
1298 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
|
|
|
1299 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
|
|
|
1300 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
|
|
|
1301 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
|
|
|
1302
|
|
|
1303 /******************** Bits definition for DMA_SxFCR register ****************/
|
|
|
1304 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
|
|
|
1305 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
|
|
|
1306 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
|
|
|
1307 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
|
|
|
1308 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
|
|
|
1309 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
|
|
|
1310 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
|
|
|
1311 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
|
|
|
1312 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
|
|
|
1313
|
|
|
1314 /******************** Bits definition for DMA_LISR register *****************/
|
|
|
1315 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
|
|
|
1316 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
|
|
|
1317 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
|
|
|
1318 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
|
|
|
1319 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
|
|
|
1320 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
|
|
|
1321 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
|
|
|
1322 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
|
|
|
1323 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
|
|
|
1324 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
|
|
|
1325 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
|
|
|
1326 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
|
|
|
1327 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
|
|
|
1328 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
|
|
|
1329 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
|
|
|
1330 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
|
|
|
1331 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
|
|
|
1332 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
|
|
|
1333 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
|
|
|
1334 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
|
|
|
1335
|
|
|
1336 /******************** Bits definition for DMA_HISR register *****************/
|
|
|
1337 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
|
|
|
1338 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
|
|
|
1339 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
|
|
|
1340 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
|
|
|
1341 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
|
|
|
1342 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
|
|
|
1343 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
|
|
|
1344 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
|
|
|
1345 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
|
|
|
1346 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
|
|
|
1347 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
|
|
|
1348 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
|
|
|
1349 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
|
|
|
1350 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
|
|
|
1351 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
|
|
|
1352 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
|
|
|
1353 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
|
|
|
1354 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
|
|
|
1355 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
|
|
|
1356 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
|
|
|
1357
|
|
|
1358 /******************** Bits definition for DMA_LIFCR register ****************/
|
|
|
1359 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
|
|
|
1360 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
|
|
|
1361 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
|
|
|
1362 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
|
|
|
1363 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
|
|
|
1364 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
|
|
|
1365 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
|
|
|
1366 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
|
|
|
1367 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
|
|
|
1368 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
|
|
|
1369 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
|
|
|
1370 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
|
|
|
1371 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
|
|
|
1372 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
|
|
|
1373 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
|
|
|
1374 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
|
|
|
1375 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
|
|
|
1376 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
|
|
|
1377 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
|
|
|
1378 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
|
|
|
1379
|
|
|
1380 /******************** Bits definition for DMA_HIFCR register ****************/
|
|
|
1381 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
|
|
|
1382 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
|
|
|
1383 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
|
|
|
1384 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
|
|
|
1385 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
|
|
|
1386 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
|
|
|
1387 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
|
|
|
1388 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
|
|
|
1389 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
|
|
|
1390 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
|
|
|
1391 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
|
|
|
1392 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
|
|
|
1393 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
|
|
|
1394 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
|
|
|
1395 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
|
|
|
1396 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
|
|
|
1397 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
|
|
|
1398 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
|
|
|
1399 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
|
|
|
1400 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
|
|
|
1401
|
|
|
1402
|
|
|
1403 /******************************************************************************/
|
|
|
1404 /* */
|
|
|
1405 /* External Interrupt/Event Controller */
|
|
|
1406 /* */
|
|
|
1407 /******************************************************************************/
|
|
|
1408 /******************* Bit definition for EXTI_IMR register *******************/
|
|
|
1409 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
|
|
1410 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
|
|
1411 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
|
|
1412 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
|
|
1413 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
|
|
1414 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
|
|
1415 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
|
|
1416 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
|
|
1417 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
|
|
1418 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
|
|
1419 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
|
|
1420 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
|
|
1421 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
|
|
1422 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
|
|
1423 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
|
|
1424 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
|
|
1425 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
|
|
1426 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
|
|
1427 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
|
|
|
1428 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
|
|
1429
|
|
|
1430 /******************* Bit definition for EXTI_EMR register *******************/
|
|
|
1431 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
|
|
1432 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
|
|
1433 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
|
|
1434 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
|
|
1435 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
|
|
1436 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
|
|
1437 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
|
|
1438 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
|
|
1439 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
|
|
1440 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
|
|
1441 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
|
|
1442 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
|
|
1443 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
|
|
1444 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
|
|
1445 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
|
|
1446 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
|
|
1447 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
|
|
1448 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
|
|
1449 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
|
|
|
1450 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
|
|
1451
|
|
|
1452 /****************** Bit definition for EXTI_RTSR register *******************/
|
|
|
1453 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
|
|
1454 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
|
|
1455 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
|
|
1456 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
|
|
1457 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
|
|
1458 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
|
|
1459 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
|
|
1460 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
|
|
1461 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
|
|
1462 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
|
|
1463 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
|
|
1464 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
|
|
1465 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
|
|
1466 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
|
|
1467 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
|
|
1468 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
|
|
1469 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
|
|
1470 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
|
|
1471 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
|
|
1472 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
|
|
1473
|
|
|
1474 /****************** Bit definition for EXTI_FTSR register *******************/
|
|
|
1475 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
|
|
1476 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
|
|
1477 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
|
|
1478 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
|
|
1479 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
|
|
1480 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
|
|
1481 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
|
|
1482 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
|
|
1483 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
|
|
1484 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
|
|
1485 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
|
|
1486 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
|
|
1487 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
|
|
1488 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
|
|
1489 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
|
|
1490 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
|
|
1491 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
|
|
1492 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
|
|
1493 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
|
|
1494 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
|
|
1495
|
|
|
1496 /****************** Bit definition for EXTI_SWIER register ******************/
|
|
|
1497 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
|
|
1498 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
|
|
1499 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
|
|
1500 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
|
|
1501 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
|
|
1502 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
|
|
1503 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
|
|
1504 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
|
|
1505 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
|
|
1506 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
|
|
1507 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
|
|
1508 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
|
|
1509 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
|
|
1510 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
|
|
1511 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
|
|
1512 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
|
|
1513 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
|
|
1514 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
|
|
1515 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
|
|
1516 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
|
|
1517
|
|
|
1518 /******************* Bit definition for EXTI_PR register ********************/
|
|
|
1519 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
|
|
1520 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
|
|
1521 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
|
|
1522 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
|
|
|
1523 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
|
|
|
1524 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
|
|
|
1525 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
|
|
|
1526 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
|
|
|
1527 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
|
|
|
1528 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
|
|
|
1529 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
|
|
|
1530 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
|
|
|
1531 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
|
|
|
1532 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
|
|
|
1533 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
|
|
|
1534 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
|
|
|
1535 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
|
|
|
1536 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
|
|
|
1537 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
|
|
|
1538 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
|
|
|
1539
|
|
|
1540 /******************************************************************************/
|
|
|
1541 /* */
|
|
|
1542 /* FLASH */
|
|
|
1543 /* */
|
|
|
1544 /******************************************************************************/
|
|
|
1545 /******************* Bits definition for FLASH_ACR register *****************/
|
|
|
1546 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
|
|
|
1547 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
|
|
|
1548 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
|
|
|
1549 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
|
|
|
1550 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
|
|
|
1551 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
|
|
|
1552 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
|
|
|
1553 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
|
|
|
1554 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
|
|
|
1555
|
|
|
1556 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
|
|
|
1557 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
|
|
|
1558 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
|
|
|
1559 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
|
|
|
1560 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
|
|
|
1561 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
|
|
|
1562 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
|
|
|
1563
|
|
|
1564 /******************* Bits definition for FLASH_SR register ******************/
|
|
|
1565 #define FLASH_SR_EOP ((uint32_t)0x00000001)
|
|
|
1566 #define FLASH_SR_SOP ((uint32_t)0x00000002)
|
|
|
1567 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
|
|
|
1568 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
|
|
|
1569 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
|
|
|
1570 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
|
|
|
1571 #define FLASH_SR_BSY ((uint32_t)0x00010000)
|
|
|
1572
|
|
|
1573 /******************* Bits definition for FLASH_CR register ******************/
|
|
|
1574 #define FLASH_CR_PG ((uint32_t)0x00000001)
|
|
|
1575 #define FLASH_CR_SER ((uint32_t)0x00000002)
|
|
|
1576 #define FLASH_CR_MER ((uint32_t)0x00000004)
|
|
|
1577 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
|
|
|
1578 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
|
|
|
1579 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
|
|
|
1580 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
|
|
|
1581 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
|
|
|
1582 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
|
|
|
1583 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
|
|
|
1584 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
|
|
|
1585 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
|
|
|
1586 #define FLASH_CR_STRT ((uint32_t)0x00010000)
|
|
|
1587 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
|
|
|
1588 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
|
|
|
1589
|
|
|
1590 /******************* Bits definition for FLASH_OPTCR register ***************/
|
|
|
1591 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
|
|
|
1592 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
|
|
|
1593 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
|
|
|
1594 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
|
|
|
1595 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
|
|
|
1596
|
|
|
1597 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
|
|
|
1598 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
|
|
|
1599 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
|
|
|
1600 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
|
|
|
1601 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
|
|
|
1602 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
|
|
|
1603 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
|
|
|
1604 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
|
|
|
1605 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
|
|
|
1606 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
|
|
|
1607 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
|
|
|
1608 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
|
|
|
1609 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
|
|
|
1610 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
|
|
|
1611 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
|
|
|
1612 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
|
|
|
1613 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
|
|
|
1614 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
|
|
|
1615 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
|
|
|
1616 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
|
|
|
1617 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
|
|
|
1618 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
|
|
|
1619 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
|
|
|
1620 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
|
|
|
1621 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
|
|
|
1622
|
|
|
1623 /****************** Bits definition for FLASH_OPTCR1 register ***************/
|
|
|
1624 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
|
|
|
1625 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
|
|
|
1626 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
|
|
|
1627 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
|
|
|
1628 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
|
|
|
1629 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
|
|
|
1630 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
|
|
|
1631 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
|
|
|
1632 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
|
|
|
1633 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
|
|
|
1634 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
|
|
|
1635 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
|
|
|
1636 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
|
|
|
1637
|
|
|
1638 /******************************************************************************/
|
|
|
1639 /* */
|
|
|
1640 /* General Purpose I/O */
|
|
|
1641 /* */
|
|
|
1642 /******************************************************************************/
|
|
|
1643 /****************** Bits definition for GPIO_MODER register *****************/
|
|
|
1644 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
|
|
1645 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
|
|
1646 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
|
|
1647
|
|
|
1648 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
|
|
|
1649 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
|
|
|
1650 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
|
|
|
1651
|
|
|
1652 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
|
|
|
1653 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
|
|
|
1654 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
|
|
|
1655
|
|
|
1656 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
|
|
|
1657 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
|
|
|
1658 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
|
|
|
1659
|
|
|
1660 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
|
|
|
1661 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
|
|
|
1662 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
|
|
|
1663
|
|
|
1664 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
|
|
|
1665 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
|
|
|
1666 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
|
|
|
1667
|
|
|
1668 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
|
|
|
1669 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
|
|
|
1670 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
|
|
|
1671
|
|
|
1672 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
|
|
|
1673 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
|
|
|
1674 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
|
|
|
1675
|
|
|
1676 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
|
|
|
1677 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
|
|
|
1678 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
|
|
|
1679
|
|
|
1680 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
|
|
|
1681 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
|
|
|
1682 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
|
|
|
1683
|
|
|
1684 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
|
|
|
1685 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
|
|
|
1686 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
|
|
|
1687
|
|
|
1688 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
|
|
|
1689 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
|
|
|
1690 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
|
|
|
1691
|
|
|
1692 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
|
|
|
1693 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
|
|
|
1694 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
|
|
|
1695
|
|
|
1696 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
|
|
|
1697 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
|
|
|
1698 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
|
|
|
1699
|
|
|
1700 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
|
|
|
1701 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
|
|
|
1702 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
|
|
|
1703
|
|
|
1704 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
|
|
|
1705 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
|
|
1706 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
|
|
1707
|
|
|
1708 /****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
1709 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
|
|
1710 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
|
|
1711 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
|
|
1712 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
|
|
|
1713 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
|
|
|
1714 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
|
|
|
1715 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
|
|
|
1716 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
|
|
|
1717 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
|
|
|
1718 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
|
|
|
1719 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
|
|
|
1720 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
|
|
|
1721 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
|
|
|
1722 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
|
|
|
1723 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
|
|
1724 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
|
|
1725
|
|
|
1726 /****************** Bits definition for GPIO_OSPEEDR register ***************/
|
|
|
1727 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
|
|
|
1728 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
|
|
|
1729 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
|
|
|
1730
|
|
|
1731 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
|
|
|
1732 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
|
|
|
1733 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
|
|
|
1734
|
|
|
1735 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
|
|
|
1736 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
|
|
|
1737 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
|
|
|
1738
|
|
|
1739 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
|
|
|
1740 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
|
|
|
1741 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
|
|
|
1742
|
|
|
1743 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
|
|
|
1744 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
|
|
|
1745 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
|
|
|
1746
|
|
|
1747 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
|
|
|
1748 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
|
|
|
1749 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
|
|
|
1750
|
|
|
1751 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
|
|
|
1752 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
|
|
|
1753 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
|
|
|
1754
|
|
|
1755 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
|
|
|
1756 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
|
|
|
1757 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
|
|
|
1758
|
|
|
1759 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
|
|
|
1760 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
|
|
|
1761 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
|
|
|
1762
|
|
|
1763 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
|
|
|
1764 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
|
|
|
1765 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
|
|
|
1766
|
|
|
1767 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
|
|
|
1768 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
|
|
|
1769 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
|
|
|
1770
|
|
|
1771 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
|
|
|
1772 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
|
|
|
1773 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
|
|
|
1774
|
|
|
1775 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
|
|
|
1776 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
|
|
|
1777 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
|
|
|
1778
|
|
|
1779 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
|
|
|
1780 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
|
|
|
1781 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
|
|
|
1782
|
|
|
1783 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
|
|
|
1784 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
|
|
|
1785 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
|
|
|
1786
|
|
|
1787 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
|
|
|
1788 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
|
|
|
1789 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
|
|
|
1790
|
|
|
1791 /****************** Bits definition for GPIO_PUPDR register *****************/
|
|
|
1792 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
|
|
1793 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
|
|
1794 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
|
|
1795
|
|
|
1796 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
|
|
|
1797 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
|
|
|
1798 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
|
|
|
1799
|
|
|
1800 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
|
|
|
1801 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
|
|
|
1802 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
|
|
|
1803
|
|
|
1804 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
|
|
|
1805 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
|
|
|
1806 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
|
|
|
1807
|
|
|
1808 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
|
|
|
1809 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
|
|
|
1810 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
|
|
|
1811
|
|
|
1812 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
|
|
|
1813 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
|
|
|
1814 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
|
|
|
1815
|
|
|
1816 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
|
|
|
1817 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
|
|
|
1818 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
|
|
|
1819
|
|
|
1820 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
|
|
|
1821 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
|
|
|
1822 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
|
|
|
1823
|
|
|
1824 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
|
|
|
1825 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
|
|
|
1826 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
|
|
|
1827
|
|
|
1828 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
|
|
|
1829 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
|
|
|
1830 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
|
|
|
1831
|
|
|
1832 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
|
|
|
1833 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
|
|
|
1834 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
|
|
|
1835
|
|
|
1836 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
|
|
|
1837 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
|
|
|
1838 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
|
|
|
1839
|
|
|
1840 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
|
|
|
1841 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
|
|
|
1842 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
|
|
|
1843
|
|
|
1844 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
|
|
|
1845 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
|
|
|
1846 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
|
|
|
1847
|
|
|
1848 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
|
|
|
1849 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
|
|
|
1850 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
|
|
|
1851
|
|
|
1852 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
|
|
|
1853 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
|
|
1854 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
|
|
1855
|
|
|
1856 /****************** Bits definition for GPIO_IDR register *******************/
|
|
|
1857 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
|
|
|
1858 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
|
|
|
1859 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
|
|
|
1860 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
|
|
|
1861 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
|
|
|
1862 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
|
|
|
1863 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
|
|
|
1864 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
|
|
|
1865 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
|
|
|
1866 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
|
|
|
1867 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
|
|
|
1868 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
|
|
|
1869 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
|
|
|
1870 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
|
|
|
1871 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
|
|
|
1872 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
|
|
|
1873 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
|
|
|
1874 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
|
|
|
1875 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
|
|
|
1876 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
|
|
|
1877 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
|
|
|
1878 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
|
|
|
1879 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
|
|
|
1880 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
|
|
|
1881 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
|
|
|
1882 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
|
|
|
1883 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
|
|
|
1884 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
|
|
|
1885 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
|
|
|
1886 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
|
|
|
1887 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
|
|
|
1888 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
|
|
|
1889 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
|
|
|
1890
|
|
|
1891 /****************** Bits definition for GPIO_ODR register *******************/
|
|
|
1892 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
|
|
|
1893 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
|
|
|
1894 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
|
|
|
1895 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
|
|
|
1896 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
|
|
|
1897 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
|
|
|
1898 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
|
|
|
1899 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
|
|
|
1900 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
|
|
|
1901 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
|
|
|
1902 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
|
|
|
1903 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
|
|
|
1904 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
|
|
|
1905 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
|
|
|
1906 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
|
|
|
1907 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
|
|
|
1908 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
|
|
|
1909 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
|
|
|
1910 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
|
|
|
1911 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
|
|
|
1912 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
|
|
|
1913 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
|
|
|
1914 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
|
|
|
1915 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
|
|
|
1916 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
|
|
|
1917 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
|
|
|
1918 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
|
|
|
1919 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
|
|
|
1920 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
|
|
|
1921 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
|
|
|
1922 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
|
|
|
1923 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
|
|
|
1924 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
|
|
|
1925
|
|
|
1926 /****************** Bits definition for GPIO_BSRR register ******************/
|
|
|
1927 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
|
|
|
1928 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
|
|
|
1929 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
|
|
|
1930 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
|
|
|
1931 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
|
|
|
1932 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
|
|
|
1933 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
|
|
|
1934 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
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|
|
1935 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
|
|
|
1936 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
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|
|
1937 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
|
|
|
1938 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
|
|
|
1939 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
|
|
|
1940 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
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|
|
1941 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
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|
|
1942 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
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|
|
1943 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
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|
|
1944 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
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|
|
1945 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
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|
|
1946 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
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|
|
1947 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
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|
|
1948 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
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|
|
1949 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
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|
|
1950 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
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|
|
1951 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
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|
|
1952 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
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|
|
1953 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
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|
|
1954 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
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|
|
1955 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
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|
|
1956 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
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|
|
1957 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
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|
|
1958 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
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|
|
1959
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|
|
1960 /****************** Bit definition for GPIO_LCKR register *********************/
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|
1961 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
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|
1962 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
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|
|
1963 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
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|
1964 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
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|
|
1965 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
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|
1966 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
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|
|
1967 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
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|
|
1968 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
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|
|
1969 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
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|
|
1970 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
|
|
|
1971 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
|
|
|
1972 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
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|
|
1973 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
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|
|
1974 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
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|
|
1975 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
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|
|
1976 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
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|
|
1977 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
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|
|
1978
|
|
|
1979 /******************************************************************************/
|
|
|
1980 /* */
|
|
|
1981 /* Inter-integrated Circuit Interface */
|
|
|
1982 /* */
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|
|
1983 /******************************************************************************/
|
|
|
1984 /******************* Bit definition for I2C_CR1 register ********************/
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|
|
1985 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
|
|
|
1986 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
|
|
|
1987 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
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|
|
1988 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
|
|
|
1989 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
|
|
|
1990 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
|
|
|
1991 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
|
|
|
1992 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
|
|
|
1993 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
|
|
|
1994 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
|
|
|
1995 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
|
|
|
1996 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
|
|
|
1997 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
|
|
|
1998 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
|
|
|
1999
|
|
|
2000 /******************* Bit definition for I2C_CR2 register ********************/
|
|
|
2001 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
|
|
|
2002 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
2003 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
2004 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
2005 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
2006 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
2007 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
2008
|
|
|
2009 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
|
|
|
2010 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
|
|
|
2011 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
|
|
|
2012 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
|
|
|
2013 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
|
|
|
2014
|
|
|
2015 /******************* Bit definition for I2C_OAR1 register *******************/
|
|
|
2016 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
|
|
|
2017 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
|
|
|
2018
|
|
|
2019 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
2020 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
2021 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
2022 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
2023 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
2024 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
2025 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
2026 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
2027 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
|
|
|
2028 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
|
|
|
2029
|
|
|
2030 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
|
|
|
2031
|
|
|
2032 /******************* Bit definition for I2C_OAR2 register *******************/
|
|
|
2033 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
|
|
|
2034 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
|
|
|
2035
|
|
|
2036 /******************** Bit definition for I2C_DR register ********************/
|
|
|
2037 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
|
|
|
2038
|
|
|
2039 /******************* Bit definition for I2C_SR1 register ********************/
|
|
|
2040 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
|
|
|
2041 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
|
|
|
2042 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
|
|
|
2043 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
|
|
|
2044 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
|
|
|
2045 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
|
|
|
2046 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
|
|
|
2047 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
|
|
|
2048 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
|
|
|
2049 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
|
|
|
2050 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
|
|
|
2051 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
|
|
|
2052 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
|
|
|
2053 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
|
|
|
2054
|
|
|
2055 /******************* Bit definition for I2C_SR2 register ********************/
|
|
|
2056 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
|
|
|
2057 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
|
|
|
2058 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
|
|
|
2059 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
|
|
|
2060 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
|
|
|
2061 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
|
|
|
2062 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
|
|
|
2063 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
|
|
|
2064
|
|
|
2065 /******************* Bit definition for I2C_CCR register ********************/
|
|
|
2066 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
|
|
|
2067 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
|
|
|
2068 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
|
|
|
2069
|
|
|
2070 /****************** Bit definition for I2C_TRISE register *******************/
|
|
|
2071 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
|
|
|
2072
|
|
|
2073 /****************** Bit definition for I2C_FLTR register *******************/
|
|
|
2074 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
|
|
|
2075 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
|
|
|
2076
|
|
|
2077 /******************************************************************************/
|
|
|
2078 /* */
|
|
|
2079 /* Independent WATCHDOG */
|
|
|
2080 /* */
|
|
|
2081 /******************************************************************************/
|
|
|
2082 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
2083 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
|
|
|
2084
|
|
|
2085 /******************* Bit definition for IWDG_PR register ********************/
|
|
|
2086 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
|
|
|
2087 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
2088 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
2089 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
2090
|
|
|
2091 /******************* Bit definition for IWDG_RLR register *******************/
|
|
|
2092 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
|
|
|
2093
|
|
|
2094 /******************* Bit definition for IWDG_SR register ********************/
|
|
|
2095 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
|
|
|
2096 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
|
|
|
2097
|
|
|
2098
|
|
|
2099 /******************************************************************************/
|
|
|
2100 /* */
|
|
|
2101 /* Power Control */
|
|
|
2102 /* */
|
|
|
2103 /******************************************************************************/
|
|
|
2104 /******************** Bit definition for PWR_CR register ********************/
|
|
|
2105 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
|
|
|
2106 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
|
|
|
2107 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
|
|
|
2108 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
|
|
|
2109 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
|
|
|
2110
|
|
|
2111 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
|
|
|
2112 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
|
|
2113 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
|
|
2114 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
|
|
2115
|
|
|
2116 /*!< PVD level configuration */
|
|
|
2117 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
|
|
|
2118 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
|
|
|
2119 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
|
|
|
2120 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
|
|
|
2121 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
|
|
|
2122 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
|
|
|
2123 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
|
|
|
2124 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
|
|
|
2125
|
|
|
2126 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
|
|
|
2127 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
|
|
|
2128 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
|
|
|
2129 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
|
|
|
2130 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
2131
|
|
|
2132 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
|
|
|
2133 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
|
|
|
2134 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
|
|
|
2135
|
|
|
2136 #define PWR_CR_FMSSR ((uint32_t)0x00100000) /*!< Flash Memory Sleep System Run */
|
|
|
2137 #define PWR_CR_FISSR ((uint32_t)0x00200000) /*!< Flash Interface Stop while System Run */
|
|
|
2138 /* Legacy define */
|
|
|
2139 #define PWR_CR_PMODE PWR_CR_VOS
|
|
|
2140
|
|
|
2141 /******************* Bit definition for PWR_CSR register ********************/
|
|
|
2142 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
|
|
|
2143 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
|
|
|
2144 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
|
|
|
2145 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
|
|
|
2146 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
|
|
|
2147 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
|
|
|
2148 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
|
|
|
2149
|
|
|
2150 /* Legacy define */
|
|
|
2151 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
|
|
|
2152
|
|
|
2153 /******************************************************************************/
|
|
|
2154 /* */
|
|
|
2155 /* Reset and Clock Control */
|
|
|
2156 /* */
|
|
|
2157 /******************************************************************************/
|
|
|
2158 /******************** Bit definition for RCC_CR register ********************/
|
|
|
2159 #define RCC_CR_HSION ((uint32_t)0x00000001)
|
|
|
2160 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
|
|
|
2161
|
|
|
2162 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
|
|
|
2163 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
|
|
|
2164 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
|
|
|
2165 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
|
|
|
2166 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
|
|
|
2167 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
|
|
|
2168
|
|
|
2169 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
|
|
|
2170 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
|
|
|
2171 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
|
|
|
2172 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
|
|
|
2173 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
|
|
|
2174 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
|
|
|
2175 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
|
|
|
2176 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
|
|
|
2177 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
|
|
|
2178
|
|
|
2179 #define RCC_CR_HSEON ((uint32_t)0x00010000)
|
|
|
2180 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
|
|
|
2181 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
|
|
|
2182 #define RCC_CR_CSSON ((uint32_t)0x00080000)
|
|
|
2183 #define RCC_CR_PLLON ((uint32_t)0x01000000)
|
|
|
2184 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
|
|
|
2185 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
|
|
|
2186 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
|
|
|
2187
|
|
|
2188 /******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
2189 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
|
|
|
2190 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
|
|
|
2191 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
|
|
|
2192 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
|
|
|
2193 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
|
|
|
2194 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
|
|
|
2195 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
|
|
|
2196
|
|
|
2197 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
|
|
|
2198 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
|
|
|
2199 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
|
|
|
2200 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
|
|
|
2201 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
|
|
|
2202 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
|
|
|
2203 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
|
|
|
2204 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
|
|
|
2205 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
|
|
|
2206 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
|
|
|
2207
|
|
|
2208 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
|
|
|
2209 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
|
|
|
2210 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
|
|
|
2211
|
|
|
2212 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
|
|
|
2213 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
|
|
|
2214 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
|
|
|
2215
|
|
|
2216 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
|
|
|
2217 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
|
|
|
2218 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
|
|
|
2219 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
|
|
|
2220 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
|
|
|
2221
|
|
|
2222 /******************** Bit definition for RCC_CFGR register ******************/
|
|
|
2223 /*!< SW configuration */
|
|
|
2224 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
|
|
2225 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
|
|
2226 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
|
|
2227
|
|
|
2228 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
|
|
|
2229 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
|
|
|
2230 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
|
|
|
2231
|
|
|
2232 /*!< SWS configuration */
|
|
|
2233 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
|
|
2234 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
|
|
2235 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
|
|
2236
|
|
|
2237 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
|
|
|
2238 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
|
|
|
2239 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
|
|
|
2240
|
|
|
2241 /*!< HPRE configuration */
|
|
|
2242 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
2243 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
|
|
2244 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
|
|
2245 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
|
|
2246 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
|
|
2247
|
|
|
2248 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
|
|
2249 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
|
|
2250 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
|
|
2251 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
|
|
2252 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
|
|
2253 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
|
|
2254 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
|
|
2255 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
|
|
2256 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
|
|
2257
|
|
|
2258 /*!< PPRE1 configuration */
|
|
|
2259 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
|
|
|
2260 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
|
|
2261 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
|
|
2262 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
|
|
2263
|
|
|
2264 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
2265 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
|
|
|
2266 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
|
|
|
2267 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
|
|
|
2268 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
|
|
|
2269
|
|
|
2270 /*!< PPRE2 configuration */
|
|
|
2271 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
|
|
2272 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
|
|
2273 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
|
|
2274 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
|
|
2275
|
|
|
2276 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
2277 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
|
|
|
2278 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
|
|
|
2279 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
|
|
|
2280 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
|
|
|
2281
|
|
|
2282 /*!< RTCPRE configuration */
|
|
|
2283 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
|
|
|
2284 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
|
|
|
2285 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
|
|
|
2286 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
|
|
|
2287 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
|
|
|
2288 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
|
|
|
2289
|
|
|
2290 /*!< MCO1 configuration */
|
|
|
2291 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
|
|
|
2292 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
|
|
|
2293 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
|
|
|
2294
|
|
|
2295 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
|
|
|
2296
|
|
|
2297 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
|
|
|
2298 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
|
|
|
2299 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
|
|
|
2300 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
|
|
|
2301
|
|
|
2302 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
|
|
|
2303 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
|
|
|
2304 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
|
|
|
2305 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
|
|
|
2306
|
|
|
2307 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
|
|
|
2308 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
|
|
|
2309 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
|
|
|
2310
|
|
|
2311 /******************** Bit definition for RCC_CIR register *******************/
|
|
|
2312 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
|
|
|
2313 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
|
|
|
2314 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
|
|
|
2315 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
|
|
|
2316 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
|
|
|
2317 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
|
|
|
2318
|
|
|
2319 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
|
|
|
2320 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
|
|
|
2321 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
|
|
|
2322 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
|
|
|
2323 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
|
|
|
2324 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
|
|
|
2325 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
|
|
|
2326
|
|
|
2327 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
|
|
|
2328 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
|
|
|
2329 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
|
|
|
2330 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
|
|
|
2331 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
|
|
|
2332 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
|
|
|
2333
|
|
|
2334 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
|
|
|
2335
|
|
|
2336 /******************** Bit definition for RCC_AHB1RSTR register **************/
|
|
|
2337 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
|
|
|
2338 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
|
|
|
2339 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
|
|
|
2340 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
|
|
|
2341 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
|
|
|
2342 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
|
|
|
2343 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
|
|
|
2344 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
|
|
|
2345 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
|
|
|
2346
|
|
|
2347 /******************** Bit definition for RCC_AHB2RSTR register **************/
|
|
|
2348 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
|
|
|
2349
|
|
|
2350 /******************** Bit definition for RCC_AHB3RSTR register **************/
|
|
|
2351
|
|
|
2352 /******************** Bit definition for RCC_APB1RSTR register **************/
|
|
|
2353 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
|
|
|
2354 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
|
|
|
2355 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
|
|
|
2356 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
|
|
|
2357 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
|
|
|
2358 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
|
|
|
2359 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
|
|
|
2360 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
|
|
|
2361 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
|
|
|
2362 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
|
|
|
2363 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
|
|
|
2364 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
|
|
|
2365
|
|
|
2366 /******************** Bit definition for RCC_APB2RSTR register **************/
|
|
|
2367 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
|
|
|
2368 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
|
|
|
2369 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
|
|
|
2370 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
|
|
|
2371 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
|
|
|
2372 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
|
|
|
2373 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
|
|
|
2374 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
|
|
|
2375 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
|
|
|
2376 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
|
|
|
2377 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
|
|
|
2378 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
|
|
|
2379
|
|
|
2380 /* Old SPI1RST bit definition, maintained for legacy purpose */
|
|
|
2381 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
|
|
|
2382
|
|
|
2383 /******************** Bit definition for RCC_AHB1ENR register ***************/
|
|
|
2384 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
|
|
|
2385 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
|
|
|
2386 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
|
|
|
2387 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
|
|
|
2388 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
|
|
|
2389 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
|
|
|
2390 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
|
|
|
2391 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
|
|
|
2392 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
|
|
|
2393 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
|
|
|
2394 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
|
|
|
2395
|
|
|
2396 /******************** Bit definition for RCC_AHB2ENR register ***************/
|
|
|
2397 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
|
|
|
2398
|
|
|
2399 /******************** Bit definition for RCC_AHB3ENR register ***************/
|
|
|
2400
|
|
|
2401 /******************** Bit definition for RCC_APB1ENR register ***************/
|
|
|
2402 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
|
|
|
2403 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
|
|
|
2404 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
|
|
|
2405 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
|
|
|
2406 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
|
|
|
2407 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
|
|
|
2408 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
|
|
|
2409 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
|
|
|
2410 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
|
|
|
2411 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
|
|
|
2412 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
|
|
|
2413 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
|
|
|
2414
|
|
|
2415 /******************** Bit definition for RCC_APB2ENR register ***************/
|
|
|
2416 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
|
|
|
2417 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
|
|
|
2418 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
|
|
|
2419 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
|
|
|
2420 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
|
|
|
2421 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
|
|
|
2422 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
|
|
|
2423 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
|
|
|
2424 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
|
|
|
2425 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
|
|
|
2426 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
|
|
|
2427 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
|
|
|
2428
|
|
|
2429 /******************** Bit definition for RCC_AHB1LPENR register *************/
|
|
|
2430 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
|
|
|
2431 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
|
|
|
2432 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
|
|
|
2433 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
|
|
|
2434 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
|
|
|
2435 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
|
|
|
2436 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
|
|
|
2437 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
|
|
|
2438 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
|
|
2439 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
|
|
2440 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
|
|
2441 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
|
|
2442 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
|
|
2443 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
|
|
2444
|
|
|
2445 /******************** Bit definition for RCC_AHB2LPENR register *************/
|
|
|
2446 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
|
|
|
2447
|
|
|
2448 /******************** Bit definition for RCC_AHB3LPENR register *************/
|
|
|
2449
|
|
|
2450 /******************** Bit definition for RCC_APB1LPENR register *************/
|
|
|
2451 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
|
|
|
2452 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
|
|
|
2453 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
|
|
|
2454 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
|
|
|
2455 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
|
|
|
2456 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
|
|
|
2457 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
|
|
|
2458 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
|
|
|
2459 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
|
|
|
2460 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
|
|
|
2461 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
|
|
|
2462 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
|
|
|
2463 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
|
|
|
2464
|
|
|
2465 /******************** Bit definition for RCC_APB2LPENR register *************/
|
|
|
2466 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
|
|
|
2467 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
|
|
|
2468 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
|
|
|
2469 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
|
|
|
2470 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
|
|
|
2471 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
|
|
|
2472 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
|
|
|
2473 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
|
|
|
2474 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
|
|
|
2475 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
|
|
|
2476 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
|
|
|
2477 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
|
|
|
2478
|
|
|
2479 /******************** Bit definition for RCC_BDCR register ******************/
|
|
|
2480 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
|
|
|
2481 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
|
|
|
2482 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
|
|
|
2483 #define RCC_BDCR_LSEMOD ((uint32_t)0x00000008)
|
|
|
2484
|
|
|
2485 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
|
|
|
2486 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
|
|
|
2487 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
|
|
|
2488
|
|
|
2489 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
|
|
|
2490 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
|
|
|
2491
|
|
|
2492 /******************** Bit definition for RCC_CSR register *******************/
|
|
|
2493 #define RCC_CSR_LSION ((uint32_t)0x00000001)
|
|
|
2494 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
|
|
|
2495 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
|
|
|
2496 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
|
|
|
2497 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
|
|
|
2498 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
|
|
|
2499 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
|
|
|
2500 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
|
|
|
2501 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
|
|
|
2502 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
|
|
|
2503
|
|
|
2504 /******************** Bit definition for RCC_SSCGR register *****************/
|
|
|
2505 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
|
|
|
2506 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
|
|
|
2507 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
|
|
|
2508 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
|
|
|
2509
|
|
|
2510 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
|
|
|
2511 #define RCC_PLLI2SCFGR_PLLI2SM ((uint32_t)0x0000003F)
|
|
|
2512 #define RCC_PLLI2SCFGR_PLLI2SM_0 ((uint32_t)0x00000001)
|
|
|
2513 #define RCC_PLLI2SCFGR_PLLI2SM_1 ((uint32_t)0x00000002)
|
|
|
2514 #define RCC_PLLI2SCFGR_PLLI2SM_2 ((uint32_t)0x00000004)
|
|
|
2515 #define RCC_PLLI2SCFGR_PLLI2SM_3 ((uint32_t)0x00000008)
|
|
|
2516 #define RCC_PLLI2SCFGR_PLLI2SM_4 ((uint32_t)0x00000010)
|
|
|
2517 #define RCC_PLLI2SCFGR_PLLI2SM_5 ((uint32_t)0x00000020)
|
|
|
2518
|
|
|
2519 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
|
|
|
2520 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
|
|
|
2521 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
|
|
|
2522 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
|
|
|
2523 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
|
|
|
2524 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
|
|
|
2525 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
|
|
|
2526 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
|
|
|
2527 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
|
|
|
2528 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
|
|
|
2529
|
|
|
2530 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
|
|
|
2531 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
|
|
|
2532 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
|
|
|
2533 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
|
|
|
2534
|
|
|
2535
|
|
|
2536 /******************************************************************************/
|
|
|
2537 /* */
|
|
|
2538 /* Real-Time Clock (RTC) */
|
|
|
2539 /* */
|
|
|
2540 /******************************************************************************/
|
|
|
2541 /******************** Bits definition for RTC_TR register *******************/
|
|
|
2542 #define RTC_TR_PM ((uint32_t)0x00400000)
|
|
|
2543 #define RTC_TR_HT ((uint32_t)0x00300000)
|
|
|
2544 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
|
|
|
2545 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
|
|
|
2546 #define RTC_TR_HU ((uint32_t)0x000F0000)
|
|
|
2547 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
|
|
|
2548 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
|
|
|
2549 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
|
|
|
2550 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
|
|
|
2551 #define RTC_TR_MNT ((uint32_t)0x00007000)
|
|
|
2552 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
|
|
|
2553 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
|
|
|
2554 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
|
|
|
2555 #define RTC_TR_MNU ((uint32_t)0x00000F00)
|
|
|
2556 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
|
|
|
2557 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
|
|
|
2558 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
|
|
|
2559 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
|
|
|
2560 #define RTC_TR_ST ((uint32_t)0x00000070)
|
|
|
2561 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
|
|
|
2562 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
|
|
|
2563 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
|
|
|
2564 #define RTC_TR_SU ((uint32_t)0x0000000F)
|
|
|
2565 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
|
|
|
2566 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
|
|
|
2567 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
|
|
|
2568 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
|
|
|
2569
|
|
|
2570 /******************** Bits definition for RTC_DR register *******************/
|
|
|
2571 #define RTC_DR_YT ((uint32_t)0x00F00000)
|
|
|
2572 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
|
|
|
2573 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
|
|
|
2574 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
|
|
|
2575 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
|
|
|
2576 #define RTC_DR_YU ((uint32_t)0x000F0000)
|
|
|
2577 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
|
|
|
2578 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
|
|
|
2579 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
|
|
|
2580 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
|
|
|
2581 #define RTC_DR_WDU ((uint32_t)0x0000E000)
|
|
|
2582 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
|
|
|
2583 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
|
|
|
2584 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
|
|
|
2585 #define RTC_DR_MT ((uint32_t)0x00001000)
|
|
|
2586 #define RTC_DR_MU ((uint32_t)0x00000F00)
|
|
|
2587 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
|
|
|
2588 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
|
|
|
2589 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
|
|
|
2590 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
|
|
|
2591 #define RTC_DR_DT ((uint32_t)0x00000030)
|
|
|
2592 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
|
|
|
2593 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
|
|
|
2594 #define RTC_DR_DU ((uint32_t)0x0000000F)
|
|
|
2595 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
|
|
|
2596 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
|
|
|
2597 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
|
|
|
2598 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
|
|
|
2599
|
|
|
2600 /******************** Bits definition for RTC_CR register *******************/
|
|
|
2601 #define RTC_CR_COE ((uint32_t)0x00800000)
|
|
|
2602 #define RTC_CR_OSEL ((uint32_t)0x00600000)
|
|
|
2603 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
|
|
|
2604 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
|
|
|
2605 #define RTC_CR_POL ((uint32_t)0x00100000)
|
|
|
2606 #define RTC_CR_COSEL ((uint32_t)0x00080000)
|
|
|
2607 #define RTC_CR_BCK ((uint32_t)0x00040000)
|
|
|
2608 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
|
|
|
2609 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
|
|
|
2610 #define RTC_CR_TSIE ((uint32_t)0x00008000)
|
|
|
2611 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
|
|
|
2612 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
|
|
|
2613 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
|
|
|
2614 #define RTC_CR_TSE ((uint32_t)0x00000800)
|
|
|
2615 #define RTC_CR_WUTE ((uint32_t)0x00000400)
|
|
|
2616 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
|
|
|
2617 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
|
|
|
2618 #define RTC_CR_DCE ((uint32_t)0x00000080)
|
|
|
2619 #define RTC_CR_FMT ((uint32_t)0x00000040)
|
|
|
2620 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
|
|
|
2621 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
|
|
|
2622 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
|
|
|
2623 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
|
|
|
2624 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
|
|
|
2625 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
|
|
|
2626 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
|
|
|
2627
|
|
|
2628 /******************** Bits definition for RTC_ISR register ******************/
|
|
|
2629 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
|
|
|
2630 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
|
|
|
2631 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
|
|
|
2632 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
|
|
|
2633 #define RTC_ISR_TSF ((uint32_t)0x00000800)
|
|
|
2634 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
|
|
|
2635 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
|
|
|
2636 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
|
|
|
2637 #define RTC_ISR_INIT ((uint32_t)0x00000080)
|
|
|
2638 #define RTC_ISR_INITF ((uint32_t)0x00000040)
|
|
|
2639 #define RTC_ISR_RSF ((uint32_t)0x00000020)
|
|
|
2640 #define RTC_ISR_INITS ((uint32_t)0x00000010)
|
|
|
2641 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
|
|
|
2642 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
|
|
|
2643 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
|
|
|
2644 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
|
|
|
2645
|
|
|
2646 /******************** Bits definition for RTC_PRER register *****************/
|
|
|
2647 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
|
|
2648 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
|
|
2649
|
|
|
2650 /******************** Bits definition for RTC_WUTR register *****************/
|
|
|
2651 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
|
|
2652
|
|
|
2653 /******************** Bits definition for RTC_CALIBR register ***************/
|
|
|
2654 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
|
|
|
2655 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
|
|
|
2656
|
|
|
2657 /******************** Bits definition for RTC_ALRMAR register ***************/
|
|
|
2658 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
|
|
|
2659 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
|
|
|
2660 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
|
|
|
2661 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
|
|
|
2662 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
|
|
|
2663 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
|
|
|
2664 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
|
|
|
2665 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
|
|
|
2666 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
|
|
|
2667 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
|
|
|
2668 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
|
|
|
2669 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
|
|
|
2670 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
|
|
|
2671 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
|
|
|
2672 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
|
|
|
2673 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
|
|
|
2674 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
|
|
|
2675 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
|
|
|
2676 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
|
|
|
2677 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
|
|
|
2678 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
|
|
|
2679 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
|
|
|
2680 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
|
|
|
2681 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
|
|
|
2682 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
|
|
|
2683 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
|
|
|
2684 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
|
|
|
2685 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
|
|
|
2686 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
|
|
|
2687 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
|
|
|
2688 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
|
|
|
2689 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
|
|
|
2690 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
|
|
|
2691 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
|
|
|
2692 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
|
|
|
2693 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
|
|
|
2694 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
|
|
|
2695 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
|
|
|
2696 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
|
|
|
2697 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
|
|
|
2698
|
|
|
2699 /******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
2700 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
|
|
|
2701 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
|
|
|
2702 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
|
|
|
2703 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
|
|
|
2704 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
|
|
|
2705 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
|
|
|
2706 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
|
|
|
2707 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
|
|
|
2708 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
|
|
|
2709 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
|
|
|
2710 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
|
|
|
2711 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
|
|
|
2712 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
|
|
|
2713 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
|
|
|
2714 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
|
|
|
2715 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
|
|
|
2716 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
|
|
|
2717 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
|
|
|
2718 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
|
|
|
2719 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
|
|
|
2720 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
|
|
|
2721 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
|
|
|
2722 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
|
|
|
2723 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
|
|
|
2724 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
|
|
|
2725 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
|
|
|
2726 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
|
|
|
2727 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
|
|
|
2728 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
|
|
|
2729 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
|
|
|
2730 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
|
|
|
2731 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
|
|
|
2732 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
|
|
|
2733 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
|
|
|
2734 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
|
|
|
2735 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
|
|
|
2736 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
|
|
|
2737 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
|
|
|
2738 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
|
|
|
2739 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
|
|
|
2740
|
|
|
2741 /******************** Bits definition for RTC_WPR register ******************/
|
|
|
2742 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
|
|
|
2743
|
|
|
2744 /******************** Bits definition for RTC_SSR register ******************/
|
|
|
2745 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
|
|
|
2746
|
|
|
2747 /******************** Bits definition for RTC_SHIFTR register ***************/
|
|
|
2748 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
|
|
|
2749 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
|
|
|
2750
|
|
|
2751 /******************** Bits definition for RTC_TSTR register *****************/
|
|
|
2752 #define RTC_TSTR_PM ((uint32_t)0x00400000)
|
|
|
2753 #define RTC_TSTR_HT ((uint32_t)0x00300000)
|
|
|
2754 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
|
|
|
2755 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
|
|
|
2756 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
|
|
|
2757 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
|
|
|
2758 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
|
|
|
2759 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
|
|
|
2760 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
|
|
|
2761 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
|
|
|
2762 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
|
|
|
2763 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
|
|
|
2764 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
|
|
|
2765 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
|
|
|
2766 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
|
|
|
2767 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
|
|
|
2768 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
|
|
|
2769 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
|
|
|
2770 #define RTC_TSTR_ST ((uint32_t)0x00000070)
|
|
|
2771 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
|
|
|
2772 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
|
|
|
2773 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
|
|
|
2774 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
|
|
|
2775 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
|
|
|
2776 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
|
|
|
2777 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
|
|
|
2778 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
|
|
|
2779
|
|
|
2780 /******************** Bits definition for RTC_TSDR register *****************/
|
|
|
2781 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
|
|
|
2782 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
|
|
|
2783 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
|
|
|
2784 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
|
|
|
2785 #define RTC_TSDR_MT ((uint32_t)0x00001000)
|
|
|
2786 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
|
|
|
2787 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
|
|
|
2788 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
|
|
|
2789 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
|
|
|
2790 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
|
|
|
2791 #define RTC_TSDR_DT ((uint32_t)0x00000030)
|
|
|
2792 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
|
|
|
2793 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
|
|
|
2794 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
|
|
|
2795 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
|
|
|
2796 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
|
|
|
2797 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
|
|
|
2798 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
|
|
|
2799
|
|
|
2800 /******************** Bits definition for RTC_TSSSR register ****************/
|
|
|
2801 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
|
|
|
2802
|
|
|
2803 /******************** Bits definition for RTC_CAL register *****************/
|
|
|
2804 #define RTC_CALR_CALP ((uint32_t)0x00008000)
|
|
|
2805 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
|
|
|
2806 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
|
|
|
2807 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
|
|
|
2808 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
|
|
|
2809 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
|
|
|
2810 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
|
|
|
2811 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
|
|
|
2812 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
|
|
|
2813 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
|
|
|
2814 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
|
|
|
2815 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
|
|
|
2816 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
|
|
|
2817
|
|
|
2818 /******************** Bits definition for RTC_TAFCR register ****************/
|
|
|
2819 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
|
|
|
2820 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
|
|
|
2821 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
|
|
|
2822 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
|
|
|
2823 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
|
|
|
2824 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
|
|
|
2825 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
|
|
|
2826 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
|
|
|
2827 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
|
|
|
2828 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
|
|
|
2829 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
|
|
|
2830 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
|
|
|
2831 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
|
|
|
2832 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
|
|
|
2833 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
|
|
|
2834 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
|
|
|
2835 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
|
|
|
2836 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
|
|
|
2837 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
|
|
|
2838 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
|
|
|
2839
|
|
|
2840 /******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
2841 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
2842 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
2843 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
2844 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
2845 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
2846 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
|
|
|
2847
|
|
|
2848 /******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
2849 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
2850 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
2851 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
2852 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
2853 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
2854 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
|
|
|
2855
|
|
|
2856 /******************** Bits definition for RTC_BKP0R register ****************/
|
|
|
2857 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
|
|
|
2858
|
|
|
2859 /******************** Bits definition for RTC_BKP1R register ****************/
|
|
|
2860 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
|
|
|
2861
|
|
|
2862 /******************** Bits definition for RTC_BKP2R register ****************/
|
|
|
2863 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
|
|
|
2864
|
|
|
2865 /******************** Bits definition for RTC_BKP3R register ****************/
|
|
|
2866 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
|
|
|
2867
|
|
|
2868 /******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
2869 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
|
|
2870
|
|
|
2871 /******************** Bits definition for RTC_BKP5R register ****************/
|
|
|
2872 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
|
|
2873
|
|
|
2874 /******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
2875 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
|
|
2876
|
|
|
2877 /******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
2878 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
|
|
2879
|
|
|
2880 /******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
2881 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
|
|
2882
|
|
|
2883 /******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
2884 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
|
|
2885
|
|
|
2886 /******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
2887 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
|
|
2888
|
|
|
2889 /******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
2890 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
|
|
2891
|
|
|
2892 /******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
2893 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
|
|
2894
|
|
|
2895 /******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
2896 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
|
|
2897
|
|
|
2898 /******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
2899 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
|
|
2900
|
|
|
2901 /******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
2902 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
|
|
2903
|
|
|
2904 /******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
2905 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
|
|
2906
|
|
|
2907 /******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
2908 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
|
|
2909
|
|
|
2910 /******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
2911 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
|
|
2912
|
|
|
2913 /******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
2914 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
|
|
2915
|
|
|
2916
|
|
|
2917
|
|
|
2918 /******************************************************************************/
|
|
|
2919 /* */
|
|
|
2920 /* SD host Interface */
|
|
|
2921 /* */
|
|
|
2922 /******************************************************************************/
|
|
|
2923 /****************** Bit definition for SDIO_POWER register ******************/
|
|
|
2924 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
|
|
2925 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
2926 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
2927
|
|
|
2928 /****************** Bit definition for SDIO_CLKCR register ******************/
|
|
|
2929 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
|
|
|
2930 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
|
|
|
2931 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
|
|
|
2932 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
|
|
|
2933
|
|
|
2934 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
2935 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
|
|
|
2936 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
|
|
|
2937
|
|
|
2938 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
|
|
|
2939 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
|
|
|
2940
|
|
|
2941 /******************* Bit definition for SDIO_ARG register *******************/
|
|
|
2942 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
|
|
|
2943
|
|
|
2944 /******************* Bit definition for SDIO_CMD register *******************/
|
|
|
2945 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
|
|
|
2946
|
|
|
2947 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
2948 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
|
|
|
2949 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
|
|
|
2950
|
|
|
2951 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
|
|
|
2952 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
|
|
2953 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
|
|
|
2954 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
|
|
|
2955 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
|
|
|
2956 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
|
|
|
2957 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
|
|
|
2958
|
|
|
2959 /***************** Bit definition for SDIO_RESPCMD register *****************/
|
|
|
2960 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
|
|
|
2961
|
|
|
2962 /****************** Bit definition for SDIO_RESP0 register ******************/
|
|
|
2963 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
2964
|
|
|
2965 /****************** Bit definition for SDIO_RESP1 register ******************/
|
|
|
2966 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
2967
|
|
|
2968 /****************** Bit definition for SDIO_RESP2 register ******************/
|
|
|
2969 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
2970
|
|
|
2971 /****************** Bit definition for SDIO_RESP3 register ******************/
|
|
|
2972 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
2973
|
|
|
2974 /****************** Bit definition for SDIO_RESP4 register ******************/
|
|
|
2975 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
2976
|
|
|
2977 /****************** Bit definition for SDIO_DTIMER register *****************/
|
|
|
2978 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
|
|
|
2979
|
|
|
2980 /****************** Bit definition for SDIO_DLEN register *******************/
|
|
|
2981 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
|
|
|
2982
|
|
|
2983 /****************** Bit definition for SDIO_DCTRL register ******************/
|
|
|
2984 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
|
|
|
2985 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
|
|
|
2986 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
|
|
|
2987 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
|
|
|
2988
|
|
|
2989 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
|
|
2990 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
2991 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
2992 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
2993 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
2994
|
|
|
2995 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
|
|
|
2996 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
|
|
|
2997 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
|
|
|
2998 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
|
|
|
2999
|
|
|
3000 /****************** Bit definition for SDIO_DCOUNT register *****************/
|
|
|
3001 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
|
|
|
3002
|
|
|
3003 /****************** Bit definition for SDIO_STA register ********************/
|
|
|
3004 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
|
|
|
3005 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
|
|
|
3006 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
|
|
|
3007 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
|
|
|
3008 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
|
|
|
3009 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
|
|
|
3010 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
|
|
|
3011 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
|
|
|
3012 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
|
|
3013 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
|
|
|
3014 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
|
|
|
3015 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
|
|
|
3016 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
|
|
|
3017 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
|
|
|
3018 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
|
|
3019 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
|
|
3020 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
|
|
|
3021 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
|
|
|
3022 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
|
|
|
3023 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
|
|
|
3024 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
|
|
|
3025 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
|
|
|
3026 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
|
|
|
3027 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
|
|
|
3028
|
|
|
3029 /******************* Bit definition for SDIO_ICR register *******************/
|
|
|
3030 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
|
|
|
3031 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
|
|
|
3032 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
|
|
|
3033 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
|
|
|
3034 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
|
|
|
3035 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
|
|
|
3036 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
|
|
|
3037 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
|
|
|
3038 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
|
|
|
3039 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
|
|
|
3040 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
|
|
|
3041 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
|
|
|
3042 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
|
|
|
3043
|
|
|
3044 /****************** Bit definition for SDIO_MASK register *******************/
|
|
|
3045 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
|
|
|
3046 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
|
|
|
3047 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
|
|
|
3048 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
|
|
|
3049 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
|
|
3050 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
|
|
3051 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
|
|
|
3052 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
|
|
|
3053 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
|
|
|
3054 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
|
|
|
3055 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
|
|
|
3056 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
|
|
|
3057 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
|
|
|
3058 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
|
|
|
3059 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
|
|
|
3060 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
|
|
|
3061 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
|
|
|
3062 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
|
|
|
3063 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
|
|
|
3064 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
|
|
|
3065 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
|
|
|
3066 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
|
|
|
3067 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
|
|
3068 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
|
|
|
3069
|
|
|
3070 /***************** Bit definition for SDIO_FIFOCNT register *****************/
|
|
|
3071 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
|
|
|
3072
|
|
|
3073 /****************** Bit definition for SDIO_FIFO register *******************/
|
|
|
3074 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
|
|
|
3075
|
|
|
3076 /******************************************************************************/
|
|
|
3077 /* */
|
|
|
3078 /* Serial Peripheral Interface */
|
|
|
3079 /* */
|
|
|
3080 /******************************************************************************/
|
|
|
3081 /******************* Bit definition for SPI_CR1 register ********************/
|
|
|
3082 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
|
|
|
3083 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
|
|
|
3084 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
|
|
|
3085
|
|
|
3086 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
3087 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
3088 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
3089 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
3090
|
|
|
3091 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
|
|
|
3092 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
|
|
|
3093 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
|
|
|
3094 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
|
|
|
3095 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
|
|
|
3096 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
|
|
|
3097 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
|
|
|
3098 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
|
|
|
3099 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
|
|
|
3100 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
|
|
|
3101
|
|
|
3102 /******************* Bit definition for SPI_CR2 register ********************/
|
|
|
3103 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
|
|
|
3104 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
|
|
|
3105 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
|
|
|
3106 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
|
|
|
3107 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
|
|
|
3108 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
|
|
|
3109 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
|
|
|
3110
|
|
|
3111 /******************** Bit definition for SPI_SR register ********************/
|
|
|
3112 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
|
|
|
3113 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
|
|
|
3114 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
|
|
|
3115 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
|
|
|
3116 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
|
|
|
3117 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
|
|
|
3118 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
|
|
|
3119 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
|
|
|
3120 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
|
|
|
3121
|
|
|
3122 /******************** Bit definition for SPI_DR register ********************/
|
|
|
3123 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
|
|
|
3124
|
|
|
3125 /******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
3126 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
|
|
|
3127
|
|
|
3128 /****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
3129 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
|
|
|
3130
|
|
|
3131 /****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
3132 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
|
|
|
3133
|
|
|
3134 /****************** Bit definition for SPI_I2SCFGR register *****************/
|
|
|
3135 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
|
|
|
3136
|
|
|
3137 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
|
|
3138 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
3139 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
3140
|
|
|
3141 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
|
|
|
3142
|
|
|
3143 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
|
|
3144 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3145 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3146
|
|
|
3147 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
|
|
|
3148
|
|
|
3149 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
|
|
|
3150 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3151 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3152
|
|
|
3153 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
|
|
|
3154 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
|
|
|
3155
|
|
|
3156 /****************** Bit definition for SPI_I2SPR register *******************/
|
|
|
3157 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
|
|
|
3158 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
|
|
|
3159 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
|
|
|
3160
|
|
|
3161 /******************************************************************************/
|
|
|
3162 /* */
|
|
|
3163 /* SYSCFG */
|
|
|
3164 /* */
|
|
|
3165 /******************************************************************************/
|
|
|
3166 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
|
|
|
3167 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
|
|
|
3168 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
|
|
|
3169 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
|
|
|
3170 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
|
|
|
3171
|
|
|
3172 /****************** Bit definition for SYSCFG_PMC register ******************/
|
|
|
3173 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
|
|
|
3174
|
|
|
3175 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
3176 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
|
|
|
3177 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
|
|
|
3178 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
|
|
|
3179 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
|
|
|
3180 /**
|
|
|
3181 * @brief EXTI0 configuration
|
|
|
3182 */
|
|
|
3183 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
|
|
|
3184 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
|
|
|
3185 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
|
|
|
3186 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
|
|
|
3187 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
|
|
|
3188 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
|
|
|
3189
|
|
|
3190 /**
|
|
|
3191 * @brief EXTI1 configuration
|
|
|
3192 */
|
|
|
3193 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
|
|
|
3194 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
|
|
|
3195 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
|
|
|
3196 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
|
|
|
3197 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
|
|
|
3198 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
|
|
|
3199
|
|
|
3200 /**
|
|
|
3201 * @brief EXTI2 configuration
|
|
|
3202 */
|
|
|
3203 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
|
|
|
3204 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
|
|
|
3205 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
|
|
|
3206 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
|
|
|
3207 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
|
|
|
3208 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
|
|
|
3209
|
|
|
3210 /**
|
|
|
3211 * @brief EXTI3 configuration
|
|
|
3212 */
|
|
|
3213 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
|
|
|
3214 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
|
|
|
3215 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
|
|
|
3216 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
|
|
|
3217 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
|
|
|
3218 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
|
|
|
3219
|
|
|
3220 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
3221 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
|
|
|
3222 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
|
|
|
3223 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
|
|
|
3224 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
|
|
|
3225 /**
|
|
|
3226 * @brief EXTI4 configuration
|
|
|
3227 */
|
|
|
3228 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
|
|
|
3229 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
|
|
|
3230 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
|
|
|
3231 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
|
|
|
3232 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
|
|
|
3233 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
|
|
|
3234
|
|
|
3235 /**
|
|
|
3236 * @brief EXTI5 configuration
|
|
|
3237 */
|
|
|
3238 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
|
|
|
3239 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
|
|
|
3240 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
|
|
|
3241 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
|
|
|
3242 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
|
|
|
3243 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
|
|
|
3244
|
|
|
3245 /**
|
|
|
3246 * @brief EXTI6 configuration
|
|
|
3247 */
|
|
|
3248 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
|
|
|
3249 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
|
|
|
3250 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
|
|
|
3251 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
|
|
|
3252 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
|
|
|
3253 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
|
|
|
3254
|
|
|
3255 /**
|
|
|
3256 * @brief EXTI7 configuration
|
|
|
3257 */
|
|
|
3258 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
|
|
|
3259 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
|
|
|
3260 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
|
|
|
3261 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
|
|
|
3262 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
|
|
|
3263 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
|
|
|
3264
|
|
|
3265
|
|
|
3266 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
3267 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
|
|
|
3268 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
|
|
|
3269 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
|
|
|
3270 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
|
|
|
3271
|
|
|
3272 /**
|
|
|
3273 * @brief EXTI8 configuration
|
|
|
3274 */
|
|
|
3275 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
|
|
|
3276 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
|
|
|
3277 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
|
|
|
3278 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
|
|
|
3279 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
|
|
|
3280 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
|
|
|
3281
|
|
|
3282 /**
|
|
|
3283 * @brief EXTI9 configuration
|
|
|
3284 */
|
|
|
3285 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
|
|
|
3286 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
|
|
|
3287 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
|
|
|
3288 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
|
|
|
3289 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
|
|
|
3290 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
|
|
|
3291
|
|
|
3292 /**
|
|
|
3293 * @brief EXTI10 configuration
|
|
|
3294 */
|
|
|
3295 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
|
|
|
3296 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
|
|
|
3297 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
|
|
|
3298 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
|
|
|
3299 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
|
|
|
3300 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
|
|
|
3301
|
|
|
3302 /**
|
|
|
3303 * @brief EXTI11 configuration
|
|
|
3304 */
|
|
|
3305 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
|
|
|
3306 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
|
|
|
3307 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
|
|
|
3308 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
|
|
|
3309 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
|
|
|
3310 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
|
|
|
3311
|
|
|
3312 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
3313 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
|
|
|
3314 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
|
|
|
3315 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
|
|
|
3316 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
|
|
|
3317 /**
|
|
|
3318 * @brief EXTI12 configuration
|
|
|
3319 */
|
|
|
3320 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
|
|
|
3321 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
|
|
|
3322 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
|
|
|
3323 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
|
|
|
3324 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
|
|
|
3325 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
|
|
|
3326
|
|
|
3327 /**
|
|
|
3328 * @brief EXTI13 configuration
|
|
|
3329 */
|
|
|
3330 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
|
|
|
3331 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
|
|
|
3332 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
|
|
|
3333 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
|
|
|
3334 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
|
|
|
3335 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
|
|
|
3336
|
|
|
3337 /**
|
|
|
3338 * @brief EXTI14 configuration
|
|
|
3339 */
|
|
|
3340 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
|
|
|
3341 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
|
|
|
3342 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
|
|
|
3343 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
|
|
|
3344 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
|
|
|
3345 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
|
|
|
3346
|
|
|
3347 /**
|
|
|
3348 * @brief EXTI15 configuration
|
|
|
3349 */
|
|
|
3350 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
|
|
|
3351 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
|
|
|
3352 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
|
|
|
3353 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
|
|
|
3354 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
|
|
|
3355 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
|
|
|
3356
|
|
|
3357 /****************** Bit definition for SYSCFG_CMPCR register ****************/
|
|
|
3358 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
|
|
|
3359 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
|
|
|
3360
|
|
|
3361 /******************************************************************************/
|
|
|
3362 /* */
|
|
|
3363 /* TIM */
|
|
|
3364 /* */
|
|
|
3365 /******************************************************************************/
|
|
|
3366 /******************* Bit definition for TIM_CR1 register ********************/
|
|
|
3367 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
|
|
|
3368 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
|
|
|
3369 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
|
|
|
3370 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
|
|
|
3371 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
|
|
|
3372
|
|
|
3373 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
3374 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
|
|
|
3375 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
|
|
|
3376
|
|
|
3377 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
|
|
|
3378
|
|
|
3379 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
|
|
|
3380 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3381 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3382
|
|
|
3383 /******************* Bit definition for TIM_CR2 register ********************/
|
|
|
3384 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
|
|
|
3385 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
|
|
|
3386 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
|
|
|
3387
|
|
|
3388 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
3389 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3390 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3391 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3392
|
|
|
3393 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
|
|
|
3394 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
|
|
|
3395 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
|
|
|
3396 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
|
|
|
3397 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
|
|
|
3398 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
|
|
|
3399 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
|
|
|
3400 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
|
|
|
3401
|
|
|
3402 /******************* Bit definition for TIM_SMCR register *******************/
|
|
|
3403 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
|
|
|
3404 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3405 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3406 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
3407
|
|
|
3408 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
|
|
|
3409 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3410 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3411 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3412
|
|
|
3413 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
|
|
|
3414
|
|
|
3415 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
|
|
|
3416 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3417 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3418 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
3419 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
3420
|
|
|
3421 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
|
|
3422 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3423 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3424
|
|
|
3425 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
|
|
|
3426 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
|
|
|
3427
|
|
|
3428 /******************* Bit definition for TIM_DIER register *******************/
|
|
|
3429 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
|
|
|
3430 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
|
|
|
3431 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
|
|
|
3432 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
|
|
|
3433 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
|
|
|
3434 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
|
|
|
3435 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
|
|
|
3436 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
|
|
|
3437 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
|
|
|
3438 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
|
|
|
3439 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
|
|
|
3440 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
|
|
|
3441 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
|
|
|
3442 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
|
|
|
3443 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
|
|
|
3444
|
|
|
3445 /******************** Bit definition for TIM_SR register ********************/
|
|
|
3446 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
|
|
|
3447 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
|
|
|
3448 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
|
|
|
3449 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
|
|
|
3450 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
|
|
|
3451 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
|
|
|
3452 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
|
|
|
3453 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
|
|
|
3454 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
|
|
|
3455 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
|
|
|
3456 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
|
|
|
3457 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
|
|
|
3458
|
|
|
3459 /******************* Bit definition for TIM_EGR register ********************/
|
|
|
3460 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
|
|
|
3461 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
|
|
|
3462 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
|
|
|
3463 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
|
|
|
3464 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
|
|
|
3465 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
|
|
|
3466 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
|
|
|
3467 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
|
|
|
3468
|
|
|
3469 /****************** Bit definition for TIM_CCMR1 register *******************/
|
|
|
3470 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
|
|
3471 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3472 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3473
|
|
|
3474 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
|
|
|
3475 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
|
|
|
3476
|
|
|
3477 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
|
|
3478 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3479 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3480 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3481
|
|
|
3482 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
|
|
|
3483
|
|
|
3484 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
3485 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3486 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3487
|
|
|
3488 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
|
|
|
3489 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
|
|
|
3490
|
|
|
3491 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
3492 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3493 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3494 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
3495
|
|
|
3496 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
|
|
|
3497
|
|
|
3498 /*----------------------------------------------------------------------------*/
|
|
|
3499
|
|
|
3500 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
|
|
3501 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
3502 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
3503
|
|
|
3504 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
|
|
3505 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3506 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3507 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3508 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
3509
|
|
|
3510 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
|
|
3511 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
3512 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
3513
|
|
|
3514 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
|
|
3515 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3516 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3517 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
3518 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
3519
|
|
|
3520 /****************** Bit definition for TIM_CCMR2 register *******************/
|
|
|
3521 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
|
|
3522 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3523 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3524
|
|
|
3525 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
|
|
|
3526 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
|
|
|
3527
|
|
|
3528 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
|
|
3529 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3530 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3531 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3532
|
|
|
3533 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
|
|
|
3534
|
|
|
3535 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
|
|
3536 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3537 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3538
|
|
|
3539 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
|
|
|
3540 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
|
|
|
3541
|
|
|
3542 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
3543 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3544 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3545 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
3546
|
|
|
3547 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
|
|
|
3548
|
|
|
3549 /*----------------------------------------------------------------------------*/
|
|
|
3550
|
|
|
3551 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
|
|
3552 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
3553 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
3554
|
|
|
3555 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
|
|
3556 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
3557 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
3558 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
3559 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
3560
|
|
|
3561 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
|
|
3562 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
3563 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
3564
|
|
|
3565 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
|
|
3566 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3567 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3568 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
3569 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
3570
|
|
|
3571 /******************* Bit definition for TIM_CCER register *******************/
|
|
|
3572 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
|
|
|
3573 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
|
|
|
3574 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
|
|
|
3575 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
|
|
|
3576 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
|
|
|
3577 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
|
|
|
3578 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
|
|
|
3579 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
|
|
|
3580 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
|
|
|
3581 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
|
|
|
3582 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
|
|
|
3583 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
|
|
|
3584 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
|
|
|
3585 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
|
|
|
3586 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
|
|
|
3587
|
|
|
3588 /******************* Bit definition for TIM_CNT register ********************/
|
|
|
3589 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
|
|
|
3590
|
|
|
3591 /******************* Bit definition for TIM_PSC register ********************/
|
|
|
3592 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
|
|
|
3593
|
|
|
3594 /******************* Bit definition for TIM_ARR register ********************/
|
|
|
3595 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
|
|
|
3596
|
|
|
3597 /******************* Bit definition for TIM_RCR register ********************/
|
|
|
3598 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
|
|
|
3599
|
|
|
3600 /******************* Bit definition for TIM_CCR1 register *******************/
|
|
|
3601 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
|
|
|
3602
|
|
|
3603 /******************* Bit definition for TIM_CCR2 register *******************/
|
|
|
3604 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
|
|
|
3605
|
|
|
3606 /******************* Bit definition for TIM_CCR3 register *******************/
|
|
|
3607 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
|
|
|
3608
|
|
|
3609 /******************* Bit definition for TIM_CCR4 register *******************/
|
|
|
3610 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
|
|
|
3611
|
|
|
3612 /******************* Bit definition for TIM_BDTR register *******************/
|
|
|
3613 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
|
|
3614 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3615 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3616 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
3617 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
3618 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
3619 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
3620 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
3621 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
3622
|
|
|
3623 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
|
|
|
3624 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3625 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3626
|
|
|
3627 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
|
|
|
3628 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
|
|
|
3629 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
|
|
|
3630 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
|
|
|
3631 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
|
|
|
3632 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
|
|
|
3633
|
|
|
3634 /******************* Bit definition for TIM_DCR register ********************/
|
|
|
3635 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
|
|
3636 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3637 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3638 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
3639 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
3640 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
3641
|
|
|
3642 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
|
|
3643 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
3644 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
3645 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
3646 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
3647 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
|
|
|
3648
|
|
|
3649 /******************* Bit definition for TIM_DMAR register *******************/
|
|
|
3650 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
|
|
|
3651
|
|
|
3652 /******************* Bit definition for TIM_OR register *********************/
|
|
|
3653 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
|
|
3654 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
|
|
|
3655 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
|
|
|
3656 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
|
|
|
3657 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
3658 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
3659
|
|
|
3660
|
|
|
3661 /******************************************************************************/
|
|
|
3662 /* */
|
|
|
3663 /* Universal Synchronous Asynchronous Receiver Transmitter */
|
|
|
3664 /* */
|
|
|
3665 /******************************************************************************/
|
|
|
3666 /******************* Bit definition for USART_SR register *******************/
|
|
|
3667 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
|
|
|
3668 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
|
|
|
3669 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
|
|
|
3670 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
|
|
|
3671 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
|
|
|
3672 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
|
|
|
3673 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
|
|
|
3674 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
|
|
|
3675 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
|
|
|
3676 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
|
|
|
3677
|
|
|
3678 /******************* Bit definition for USART_DR register *******************/
|
|
|
3679 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
|
|
|
3680
|
|
|
3681 /****************** Bit definition for USART_BRR register *******************/
|
|
|
3682 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
|
|
|
3683 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
|
|
|
3684
|
|
|
3685 /****************** Bit definition for USART_CR1 register *******************/
|
|
|
3686 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
|
|
|
3687 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
|
|
|
3688 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
|
|
|
3689 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
|
|
|
3690 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
|
|
|
3691 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
|
|
|
3692 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
|
|
|
3693 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
|
|
|
3694 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
|
|
|
3695 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
|
|
|
3696 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
|
|
|
3697 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
|
|
|
3698 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
|
|
|
3699 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
|
|
|
3700 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
|
|
|
3701
|
|
|
3702 /****************** Bit definition for USART_CR2 register *******************/
|
|
|
3703 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
|
|
|
3704 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
|
|
|
3705 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
|
|
|
3706 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
|
|
|
3707 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
|
|
|
3708 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
|
|
|
3709 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
|
|
|
3710
|
|
|
3711 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
|
|
|
3712 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
3713 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
3714
|
|
|
3715 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
|
|
|
3716
|
|
|
3717 /****************** Bit definition for USART_CR3 register *******************/
|
|
|
3718 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
|
|
|
3719 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
|
|
|
3720 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
|
|
|
3721 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
|
|
|
3722 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
|
|
|
3723 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
|
|
|
3724 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
|
|
|
3725 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
|
|
|
3726 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
|
|
|
3727 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
|
|
|
3728 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
|
|
|
3729 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
|
|
|
3730
|
|
|
3731 /****************** Bit definition for USART_GTPR register ******************/
|
|
|
3732 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
|
|
3733 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3734 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3735 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
3736 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
3737 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
3738 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
3739 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
3740 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
3741
|
|
|
3742 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
|
|
|
3743
|
|
|
3744 /******************************************************************************/
|
|
|
3745 /* */
|
|
|
3746 /* Window WATCHDOG */
|
|
|
3747 /* */
|
|
|
3748 /******************************************************************************/
|
|
|
3749 /******************* Bit definition for WWDG_CR register ********************/
|
|
|
3750 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
3751 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
3752 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
3753 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
3754 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
|
|
|
3755 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
|
|
|
3756 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
|
|
|
3757 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
|
|
|
3758
|
|
|
3759 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
|
|
|
3760
|
|
|
3761 /******************* Bit definition for WWDG_CFR register *******************/
|
|
|
3762 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
|
|
|
3763 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
3764 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
3765 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
3766 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
3767 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
3768 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
3769 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
3770
|
|
|
3771 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
3772 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
|
|
|
3773 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
|
|
|
3774
|
|
|
3775 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
|
|
|
3776
|
|
|
3777 /******************* Bit definition for WWDG_SR register ********************/
|
|
|
3778 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
|
|
|
3779
|
|
|
3780
|
|
|
3781 /******************************************************************************/
|
|
|
3782 /* */
|
|
|
3783 /* DBG */
|
|
|
3784 /* */
|
|
|
3785 /******************************************************************************/
|
|
|
3786 /******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
3787 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
|
|
|
3788 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
|
|
|
3789
|
|
|
3790 /******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
3791 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
|
|
|
3792 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
|
|
|
3793 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
|
|
|
3794 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
|
|
|
3795
|
|
|
3796 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
|
|
|
3797 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
|
|
|
3798 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
|
|
|
3799
|
|
|
3800 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
|
|
|
3801 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
|
|
|
3802 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
|
|
|
3803 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
|
|
|
3804 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
|
|
|
3805 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
|
|
|
3806 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
|
|
|
3807 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
|
|
|
3808 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
|
|
|
3809 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
|
|
|
3810 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
|
|
|
3811 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
|
|
|
3812 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
|
|
|
3813 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
|
|
3814 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
|
|
3815 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
|
|
|
3816 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
|
|
|
3817 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
|
|
|
3818 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
|
|
|
3819 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
|
|
|
3820
|
|
|
3821 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
|
|
|
3822 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
|
|
|
3823 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
|
|
|
3824 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
|
|
|
3825 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
|
|
|
3826 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
|
|
|
3827
|
|
|
3828 /******************************************************************************/
|
|
|
3829 /* */
|
|
|
3830 /* USB_OTG */
|
|
|
3831 /* */
|
|
|
3832 /******************************************************************************/
|
|
|
3833 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
|
|
|
3834 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
|
|
|
3835 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
|
|
|
3836 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
|
|
|
3837 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
|
|
|
3838 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
|
|
|
3839 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
|
|
|
3840 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
|
|
|
3841 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
|
|
|
3842 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
|
|
|
3843 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
|
|
|
3844
|
|
|
3845 /******************** Bit definition forUSB_OTG_HCFG register ********************/
|
|
|
3846
|
|
|
3847 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
|
|
|
3848 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3849 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3850 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
|
|
|
3851
|
|
|
3852 /******************** Bit definition forUSB_OTG_DCFG register ********************/
|
|
|
3853
|
|
|
3854 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
|
|
|
3855 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3856 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3857 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
|
|
|
3858
|
|
|
3859 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
|
|
|
3860 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3861 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3862 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3863 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3864 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
|
|
|
3865 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
|
|
|
3866 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
|
|
|
3867
|
|
|
3868 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
|
|
|
3869 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
3870 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
3871
|
|
|
3872 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
|
|
|
3873 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3874 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3875
|
|
|
3876 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
|
|
|
3877 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
|
|
|
3878 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
|
|
|
3879 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
|
|
|
3880
|
|
|
3881 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
|
|
|
3882 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
|
|
|
3883 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
|
|
|
3884 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
|
|
|
3885 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
|
|
|
3886 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
|
|
|
3887 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
|
|
|
3888
|
|
|
3889 /******************** Bit definition forUSB_OTG_DCTL register ********************/
|
|
|
3890 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
|
|
|
3891 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
|
|
|
3892 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
|
|
|
3893 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
|
|
|
3894
|
|
|
3895 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
|
|
|
3896 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3897 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3898 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3899 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
|
|
|
3900 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
|
|
|
3901 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
|
|
|
3902 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
|
|
|
3903 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
|
|
|
3904
|
|
|
3905 /******************** Bit definition forUSB_OTG_HFIR register ********************/
|
|
|
3906 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
|
|
|
3907
|
|
|
3908 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
|
|
|
3909 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
|
|
|
3910 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
|
|
|
3911
|
|
|
3912 /******************** Bit definition forUSB_OTG_DSTS register ********************/
|
|
|
3913 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
|
|
|
3914
|
|
|
3915 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
|
|
|
3916 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
3917 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
3918 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
|
|
|
3919 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
|
|
|
3920
|
|
|
3921 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
|
|
|
3922 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
|
|
|
3923
|
|
|
3924 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
|
|
|
3925 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
3926 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
3927 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
|
|
|
3928 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
|
|
|
3929 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
|
|
|
3930 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
|
|
|
3931 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
|
|
|
3932
|
|
|
3933 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
|
|
|
3934
|
|
|
3935 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
|
|
|
3936 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3937 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3938 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3939 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
|
|
|
3940 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
|
|
|
3941 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
|
|
|
3942
|
|
|
3943 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
|
|
|
3944 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
3945 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
3946 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
3947 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
3948 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
|
|
|
3949 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
|
|
|
3950 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
|
|
|
3951 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
|
|
|
3952 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
|
|
|
3953 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
|
|
|
3954 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
|
|
|
3955 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
|
|
|
3956 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
|
|
|
3957 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
|
|
|
3958 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
|
|
|
3959 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
|
|
|
3960 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
|
|
|
3961
|
|
|
3962 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
|
|
3963 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
|
|
|
3964 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
|
|
|
3965 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
|
|
|
3966 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
|
|
|
3967 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
|
|
|
3968
|
|
|
3969 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
|
|
|
3970 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
3971 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
3972 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
3973 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
|
|
|
3974 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
|
|
|
3975 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
|
|
|
3976 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
|
|
|
3977
|
|
|
3978 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
|
|
|
3979 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
3980 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
3981 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
3982 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
3983 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
3984 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
3985 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
3986 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
3987
|
|
|
3988 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
|
|
|
3989 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
|
|
|
3990
|
|
|
3991 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
|
|
|
3992 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3993 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3994 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3995 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3996 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
3997 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
3998 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
3999 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4000
|
|
|
4001 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
|
|
|
4002 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4003 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4004 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4005 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4006 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4007 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4008 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4009 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4010
|
|
|
4011 /******************** Bit definition forUSB_OTG_HAINT register ********************/
|
|
|
4012 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
|
|
|
4013
|
|
|
4014 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
|
|
|
4015 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
4016 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
4017 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
|
|
|
4018 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
|
|
|
4019 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
|
|
|
4020 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
4021 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
4022
|
|
|
4023 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
|
|
|
4024 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
|
|
|
4025 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
|
|
|
4026 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
|
|
|
4027 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
|
|
|
4028 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
|
|
|
4029 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
|
|
|
4030 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
|
|
|
4031 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
|
|
|
4032 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
|
|
|
4033 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
|
|
|
4034 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
|
|
|
4035 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
|
|
|
4036 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
|
|
|
4037 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
|
|
|
4038 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
|
|
|
4039 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
|
|
|
4040 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
|
|
|
4041 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
|
|
|
4042 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
|
|
|
4043 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
|
|
|
4044 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
|
|
|
4045 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
|
|
|
4046 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
|
|
|
4047 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
|
|
|
4048 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
|
|
|
4049 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
|
|
|
4050
|
|
|
4051 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
|
|
|
4052 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
|
|
|
4053 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
|
|
|
4054 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
|
|
|
4055 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
|
|
|
4056 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
|
|
|
4057 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
|
|
|
4058 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
|
|
|
4059 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
|
|
|
4060 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
|
|
|
4061 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
|
|
|
4062 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
|
|
|
4063 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
|
|
|
4064 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
|
|
|
4065 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
|
|
|
4066 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
|
|
|
4067 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
|
|
|
4068 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
|
|
|
4069 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
|
|
|
4070 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
|
|
|
4071 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
|
|
|
4072 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
|
|
|
4073 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
|
|
|
4074 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
|
|
|
4075 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
|
|
|
4076 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
|
|
|
4077 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
|
|
|
4078
|
|
|
4079 /******************** Bit definition forUSB_OTG_DAINT register ********************/
|
|
|
4080 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
|
|
|
4081 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
|
|
|
4082
|
|
|
4083 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
|
|
|
4084 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
|
|
|
4085
|
|
|
4086 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
|
|
|
4087 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
|
|
|
4088 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
|
|
|
4089 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
|
|
|
4090 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
|
|
|
4091
|
|
|
4092 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
|
|
|
4093 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
|
|
|
4094 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
|
|
|
4095
|
|
|
4096 /******************** Bit definition for OTG register ********************/
|
|
|
4097
|
|
|
4098 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
4099 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4100 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4101 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4102 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4103 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
4104
|
|
|
4105 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
4106 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
4107 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
4108
|
|
|
4109 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
4110 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4111 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4112 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4113 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
4114
|
|
|
4115 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
4116 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4117 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4118 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4119 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4120
|
|
|
4121 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
4122 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
4123 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
4124 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
4125 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
4126
|
|
|
4127 /******************** Bit definition for OTG register ********************/
|
|
|
4128
|
|
|
4129 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
4130 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4131 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4132 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4133 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4134 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
4135
|
|
|
4136 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
4137 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
4138 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
4139
|
|
|
4140 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
4141 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4142 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4143 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4144 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
4145
|
|
|
4146 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
4147 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4148 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4149 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4150 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4151
|
|
|
4152 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
4153 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
4154 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
4155 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
4156 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
4157
|
|
|
4158 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
|
|
|
4159 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
|
|
|
4160
|
|
|
4161 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
|
|
|
4162 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
|
|
|
4163
|
|
|
4164 /******************** Bit definition for OTG register ********************/
|
|
|
4165 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
|
|
|
4166 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
|
|
|
4167 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
|
|
|
4168 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
|
|
|
4169
|
|
|
4170 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
|
|
|
4171 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
|
|
|
4172
|
|
|
4173 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
|
|
|
4174 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
|
|
|
4175
|
|
|
4176 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
|
|
|
4177 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4178 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4179 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4180 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4181 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4182 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4183 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4184 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4185
|
|
|
4186 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
|
|
|
4187 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4188 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4189 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4190 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4191 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4192 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4193 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4194
|
|
|
4195 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
|
|
|
4196 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
|
|
|
4197 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
|
|
|
4198
|
|
|
4199 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
|
|
|
4200 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
4201 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
4202 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
|
|
|
4203 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
|
|
|
4204 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
|
|
|
4205 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
|
|
|
4206 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
|
|
|
4207 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
|
|
|
4208 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
|
|
|
4209 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
|
|
|
4210
|
|
|
4211 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
|
|
|
4212 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4213 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4214 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
4215 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
4216 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
|
|
|
4217 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
|
|
|
4218 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
|
|
|
4219 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
|
|
|
4220 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
|
|
|
4221 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
|
|
|
4222
|
|
|
4223 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
|
|
|
4224 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
|
|
|
4225
|
|
|
4226 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
|
|
|
4227 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
|
|
|
4228 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
|
|
|
4229
|
|
|
4230 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
|
|
|
4231 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
|
|
|
4232 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
|
|
|
4233 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
|
|
|
4234 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
|
|
|
4235 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
|
|
|
4236 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
|
|
|
4237
|
|
|
4238 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
|
|
|
4239 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
|
|
|
4240 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
|
|
|
4241
|
|
|
4242 /******************** Bit definition forUSB_OTG_CID register ********************/
|
|
|
4243 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
|
|
|
4244
|
|
|
4245 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
|
|
|
4246 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
4247 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
4248 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
4249 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
4250 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
4251 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
4252 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
4253 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
4254 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
4255
|
|
|
4256 /******************** Bit definition forUSB_OTG_HPRT register ********************/
|
|
|
4257 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
|
|
|
4258 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
|
|
|
4259 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
|
|
|
4260 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
|
|
|
4261 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
|
|
|
4262 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
|
|
|
4263 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
|
|
|
4264 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
|
|
|
4265 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
|
|
|
4266
|
|
|
4267 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
|
|
|
4268 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
4269 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
4270 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
|
|
|
4271
|
|
|
4272 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
|
|
|
4273 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
4274 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
4275 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
4276 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
4277
|
|
|
4278 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
|
|
|
4279 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
4280 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
4281
|
|
|
4282 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
|
|
|
4283 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
4284 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
4285 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
|
|
|
4286 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
4287 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
4288 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
4289 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
4290 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
4291 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
|
|
|
4292 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
4293 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
|
|
|
4294
|
|
|
4295 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
|
|
|
4296 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
|
|
|
4297 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
|
|
|
4298
|
|
|
4299 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
|
|
|
4300 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
4301 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
4302 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
|
|
|
4303 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
4304
|
|
|
4305 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
4306 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
4307 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
4308 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
4309
|
|
|
4310 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
|
|
|
4311 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
4312 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
4313 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
4314 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
4315 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
4316 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
4317 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
4318 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
4319 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
4320 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
4321
|
|
|
4322 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
|
|
|
4323 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
4324
|
|
|
4325 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
|
|
|
4326 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
4327 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
4328 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
|
|
|
4329 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
|
|
|
4330 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
|
|
|
4331 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
|
|
|
4332
|
|
|
4333 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
4334 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
4335 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
4336
|
|
|
4337 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
|
|
|
4338 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
4339 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
4340
|
|
|
4341 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
|
|
|
4342 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
4343 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
4344 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
4345 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
4346 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
|
|
|
4347 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
|
|
|
4348 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
|
|
|
4349 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
|
|
|
4350 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
|
|
|
4351 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
|
|
|
4352
|
|
|
4353 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
|
|
|
4354
|
|
|
4355 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
|
|
|
4356 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4357 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4358 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4359 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4360 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4361 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4362 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4363
|
|
|
4364 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
|
|
|
4365 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
4366 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
4367 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
|
|
|
4368 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
|
|
|
4369 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
|
|
|
4370 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
|
|
|
4371 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
|
|
|
4372
|
|
|
4373 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
|
|
|
4374 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
4375 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
4376 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
|
|
|
4377 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
|
|
|
4378
|
|
|
4379 /******************** Bit definition forUSB_OTG_HCINT register ********************/
|
|
|
4380 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
|
|
|
4381 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
|
|
|
4382 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
4383 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
|
|
|
4384 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
|
|
|
4385 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
|
|
|
4386 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
|
|
|
4387 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
|
|
|
4388 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
|
|
|
4389 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
|
|
|
4390 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
|
|
|
4391
|
|
|
4392 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
|
|
|
4393 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
4394 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
4395 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
|
|
|
4396 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
|
|
|
4397 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
|
|
|
4398 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
|
|
|
4399 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
|
|
|
4400 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
|
|
|
4401 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
|
|
|
4402 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
|
|
|
4403 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
|
|
|
4404
|
|
|
4405 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
|
|
|
4406 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
|
|
|
4407 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
|
|
|
4408 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
4409 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
|
|
|
4410 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
|
|
|
4411 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
|
|
|
4412 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
|
|
|
4413 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
|
|
|
4414 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
|
|
|
4415 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
|
|
|
4416 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
|
|
|
4417
|
|
|
4418 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
|
|
|
4419
|
|
|
4420 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
4421 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
4422 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
|
|
|
4423 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
|
|
|
4424 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
4425 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
4426 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
|
|
|
4427 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
|
|
|
4428 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
4429 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
4430
|
|
|
4431 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
|
|
|
4432 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
4433
|
|
|
4434 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
|
|
|
4435 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
4436
|
|
|
4437 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
|
|
|
4438 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
|
|
|
4439
|
|
|
4440 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
|
|
|
4441 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
|
|
|
4442 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
|
|
|
4443
|
|
|
4444 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
|
|
|
4445
|
|
|
4446 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
|
|
|
4447 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
4448 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
4449 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
4450 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
4451 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
4452 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
4453 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
4454 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
|
|
|
4455 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
4456 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
4457 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
4458 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
4459 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
4460
|
|
|
4461 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
|
|
|
4462 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
4463 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
4464 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
|
|
|
4465 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
|
|
|
4466 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
|
|
|
4467 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
|
|
|
4468
|
|
|
4469 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
|
|
|
4470
|
|
|
4471 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
4472 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
4473
|
|
|
4474 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
|
|
|
4475 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
4476 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
4477
|
|
|
4478 /******************** Bit definition for PCGCCTL register ********************/
|
|
|
4479 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
|
|
|
4480 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
4481 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
4482
|
|
|
4483 /**
|
|
|
4484 * @}
|
|
|
4485 */
|
|
|
4486
|
|
|
4487 /**
|
|
|
4488 * @}
|
|
|
4489 */
|
|
|
4490
|
|
|
4491 /** @addtogroup Exported_macros
|
|
|
4492 * @{
|
|
|
4493 */
|
|
|
4494
|
|
|
4495 /******************************* ADC Instances ********************************/
|
|
|
4496 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
|
|
4497
|
|
|
4498 /******************************* CRC Instances ********************************/
|
|
|
4499 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
4500
|
|
|
4501 /******************************** DMA Instances *******************************/
|
|
|
4502 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
|
|
|
4503 ((INSTANCE) == DMA1_Stream1) || \
|
|
|
4504 ((INSTANCE) == DMA1_Stream2) || \
|
|
|
4505 ((INSTANCE) == DMA1_Stream3) || \
|
|
|
4506 ((INSTANCE) == DMA1_Stream4) || \
|
|
|
4507 ((INSTANCE) == DMA1_Stream5) || \
|
|
|
4508 ((INSTANCE) == DMA1_Stream6) || \
|
|
|
4509 ((INSTANCE) == DMA1_Stream7) || \
|
|
|
4510 ((INSTANCE) == DMA2_Stream0) || \
|
|
|
4511 ((INSTANCE) == DMA2_Stream1) || \
|
|
|
4512 ((INSTANCE) == DMA2_Stream2) || \
|
|
|
4513 ((INSTANCE) == DMA2_Stream3) || \
|
|
|
4514 ((INSTANCE) == DMA2_Stream4) || \
|
|
|
4515 ((INSTANCE) == DMA2_Stream5) || \
|
|
|
4516 ((INSTANCE) == DMA2_Stream6) || \
|
|
|
4517 ((INSTANCE) == DMA2_Stream7))
|
|
|
4518
|
|
|
4519 /******************************* GPIO Instances *******************************/
|
|
|
4520 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
4521 ((INSTANCE) == GPIOB) || \
|
|
|
4522 ((INSTANCE) == GPIOC) || \
|
|
|
4523 ((INSTANCE) == GPIOD) || \
|
|
|
4524 ((INSTANCE) == GPIOE) || \
|
|
|
4525 ((INSTANCE) == GPIOH))
|
|
|
4526
|
|
|
4527 /******************************** I2C Instances *******************************/
|
|
|
4528 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
4529 ((INSTANCE) == I2C2) || \
|
|
|
4530 ((INSTANCE) == I2C3))
|
|
|
4531
|
|
|
4532 /******************************** I2S Instances *******************************/
|
|
|
4533 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
4534 ((INSTANCE) == SPI2) || \
|
|
|
4535 ((INSTANCE) == SPI3) || \
|
|
|
4536 ((INSTANCE) == SPI4) || \
|
|
|
4537 ((INSTANCE) == SPI5))
|
|
|
4538
|
|
|
4539 /*************************** I2S Extended Instances ***************************/
|
|
|
4540 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
|
|
|
4541 ((INSTANCE) == SPI3) || \
|
|
|
4542 ((INSTANCE) == I2S2ext) || \
|
|
|
4543 ((INSTANCE) == I2S3ext))
|
|
|
4544
|
|
|
4545
|
|
|
4546 /****************************** RTC Instances *********************************/
|
|
|
4547 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
4548
|
|
|
4549 /******************************** SPI Instances *******************************/
|
|
|
4550 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
4551 ((INSTANCE) == SPI2) || \
|
|
|
4552 ((INSTANCE) == SPI3) || \
|
|
|
4553 ((INSTANCE) == SPI4) || \
|
|
|
4554 ((INSTANCE) == SPI5))
|
|
|
4555 /*************************** SPI Extended Instances ***************************/
|
|
|
4556 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
4557 ((INSTANCE) == SPI2) || \
|
|
|
4558 ((INSTANCE) == SPI3) || \
|
|
|
4559 ((INSTANCE) == SPI4) || \
|
|
|
4560 ((INSTANCE) == SPI5) || \
|
|
|
4561 ((INSTANCE) == I2S2ext) || \
|
|
|
4562 ((INSTANCE) == I2S3ext))
|
|
|
4563
|
|
|
4564 /****************** TIM Instances : All supported instances *******************/
|
|
|
4565 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4566 ((INSTANCE) == TIM2) || \
|
|
|
4567 ((INSTANCE) == TIM3) || \
|
|
|
4568 ((INSTANCE) == TIM4) || \
|
|
|
4569 ((INSTANCE) == TIM5) || \
|
|
|
4570 ((INSTANCE) == TIM9) || \
|
|
|
4571 ((INSTANCE) == TIM10) || \
|
|
|
4572 ((INSTANCE) == TIM11))
|
|
|
4573
|
|
|
4574 /************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
4575 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4576 ((INSTANCE) == TIM2) || \
|
|
|
4577 ((INSTANCE) == TIM3) || \
|
|
|
4578 ((INSTANCE) == TIM4) || \
|
|
|
4579 ((INSTANCE) == TIM5) || \
|
|
|
4580 ((INSTANCE) == TIM9) || \
|
|
|
4581 ((INSTANCE) == TIM10) || \
|
|
|
4582 ((INSTANCE) == TIM11))
|
|
|
4583
|
|
|
4584 /************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
4585 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4586 ((INSTANCE) == TIM2) || \
|
|
|
4587 ((INSTANCE) == TIM3) || \
|
|
|
4588 ((INSTANCE) == TIM4) || \
|
|
|
4589 ((INSTANCE) == TIM5) || \
|
|
|
4590 ((INSTANCE) == TIM9))
|
|
|
4591
|
|
|
4592 /************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
4593 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4594 ((INSTANCE) == TIM2) || \
|
|
|
4595 ((INSTANCE) == TIM3) || \
|
|
|
4596 ((INSTANCE) == TIM4) || \
|
|
|
4597 ((INSTANCE) == TIM5))
|
|
|
4598
|
|
|
4599 /************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
4600 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4601 ((INSTANCE) == TIM2) || \
|
|
|
4602 ((INSTANCE) == TIM3) || \
|
|
|
4603 ((INSTANCE) == TIM4) || \
|
|
|
4604 ((INSTANCE) == TIM5))
|
|
|
4605
|
|
|
4606 /******************** TIM Instances : Advanced-control timers *****************/
|
|
|
4607 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
|
|
4608
|
|
|
4609 /******************* TIM Instances : Timer input XOR function *****************/
|
|
|
4610 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4611 ((INSTANCE) == TIM2) || \
|
|
|
4612 ((INSTANCE) == TIM3) || \
|
|
|
4613 ((INSTANCE) == TIM4) || \
|
|
|
4614 ((INSTANCE) == TIM5))
|
|
|
4615
|
|
|
4616 /****************** TIM Instances : DMA requests generation (UDE) *************/
|
|
|
4617 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4618 ((INSTANCE) == TIM2) || \
|
|
|
4619 ((INSTANCE) == TIM3) || \
|
|
|
4620 ((INSTANCE) == TIM4) || \
|
|
|
4621 ((INSTANCE) == TIM5))
|
|
|
4622
|
|
|
4623 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
|
|
|
4624 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4625 ((INSTANCE) == TIM2) || \
|
|
|
4626 ((INSTANCE) == TIM3) || \
|
|
|
4627 ((INSTANCE) == TIM4) || \
|
|
|
4628 ((INSTANCE) == TIM5))
|
|
|
4629
|
|
|
4630 /************ TIM Instances : DMA requests generation (COMDE) *****************/
|
|
|
4631 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4632 ((INSTANCE) == TIM2) || \
|
|
|
4633 ((INSTANCE) == TIM3) || \
|
|
|
4634 ((INSTANCE) == TIM4) || \
|
|
|
4635 ((INSTANCE) == TIM5))
|
|
|
4636
|
|
|
4637 /******************** TIM Instances : DMA burst feature ***********************/
|
|
|
4638 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4639 ((INSTANCE) == TIM2) || \
|
|
|
4640 ((INSTANCE) == TIM3) || \
|
|
|
4641 ((INSTANCE) == TIM4) || \
|
|
|
4642 ((INSTANCE) == TIM5))
|
|
|
4643
|
|
|
4644 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
|
|
4645 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4646 ((INSTANCE) == TIM2) || \
|
|
|
4647 ((INSTANCE) == TIM3) || \
|
|
|
4648 ((INSTANCE) == TIM4) || \
|
|
|
4649 ((INSTANCE) == TIM5) || \
|
|
|
4650 ((INSTANCE) == TIM9))
|
|
|
4651
|
|
|
4652 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
4653 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4654 ((INSTANCE) == TIM2) || \
|
|
|
4655 ((INSTANCE) == TIM3) || \
|
|
|
4656 ((INSTANCE) == TIM4) || \
|
|
|
4657 ((INSTANCE) == TIM5) || \
|
|
|
4658 ((INSTANCE) == TIM9))
|
|
|
4659
|
|
|
4660 /********************** TIM Instances : 32 bit Counter ************************/
|
|
|
4661 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
|
|
|
4662 ((INSTANCE) == TIM5))
|
|
|
4663
|
|
|
4664 /***************** TIM Instances : external trigger input availabe ************/
|
|
|
4665 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
4666 ((INSTANCE) == TIM2) || \
|
|
|
4667 ((INSTANCE) == TIM3) || \
|
|
|
4668 ((INSTANCE) == TIM4) || \
|
|
|
4669 ((INSTANCE) == TIM5))
|
|
|
4670
|
|
|
4671 /****************** TIM Instances : remapping capability **********************/
|
|
|
4672 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
|
|
4673 ((INSTANCE) == TIM5) || \
|
|
|
4674 ((INSTANCE) == TIM11))
|
|
|
4675
|
|
|
4676 /******************* TIM Instances : output(s) available **********************/
|
|
|
4677 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
4678 ((((INSTANCE) == TIM1) && \
|
|
|
4679 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4680 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4681 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
4682 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
4683 || \
|
|
|
4684 (((INSTANCE) == TIM2) && \
|
|
|
4685 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4686 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4687 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
4688 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
4689 || \
|
|
|
4690 (((INSTANCE) == TIM3) && \
|
|
|
4691 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4692 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4693 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
4694 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
4695 || \
|
|
|
4696 (((INSTANCE) == TIM4) && \
|
|
|
4697 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4698 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4699 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
4700 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
4701 || \
|
|
|
4702 (((INSTANCE) == TIM5) && \
|
|
|
4703 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4704 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4705 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
4706 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
4707 || \
|
|
|
4708 (((INSTANCE) == TIM9) && \
|
|
|
4709 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4710 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
4711 || \
|
|
|
4712 (((INSTANCE) == TIM10) && \
|
|
|
4713 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
4714 || \
|
|
|
4715 (((INSTANCE) == TIM11) && \
|
|
|
4716 (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
4717
|
|
|
4718 /************ TIM Instances : complementary output(s) available ***************/
|
|
|
4719 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
4720 ((((INSTANCE) == TIM1) && \
|
|
|
4721 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
4722 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
4723 ((CHANNEL) == TIM_CHANNEL_3))))
|
|
|
4724
|
|
|
4725 /******************** USART Instances : Synchronous mode **********************/
|
|
|
4726 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
4727 ((INSTANCE) == USART2) || \
|
|
|
4728 ((INSTANCE) == USART6))
|
|
|
4729
|
|
|
4730 /******************** UART Instances : Asynchronous mode **********************/
|
|
|
4731 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
4732 ((INSTANCE) == USART2) || \
|
|
|
4733 ((INSTANCE) == USART6))
|
|
|
4734
|
|
|
4735 /****************** UART Instances : Hardware Flow control ********************/
|
|
|
4736 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
4737 ((INSTANCE) == USART2) || \
|
|
|
4738 ((INSTANCE) == USART6))
|
|
|
4739
|
|
|
4740 /********************* UART Instances : Smard card mode ***********************/
|
|
|
4741 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
4742 ((INSTANCE) == USART2) || \
|
|
|
4743 ((INSTANCE) == USART6))
|
|
|
4744
|
|
|
4745 /*********************** UART Instances : IRDA mode ***************************/
|
|
|
4746 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
4747 ((INSTANCE) == USART2) || \
|
|
|
4748 ((INSTANCE) == USART6))
|
|
|
4749
|
|
|
4750 /****************************** IWDG Instances ********************************/
|
|
|
4751 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
4752
|
|
|
4753 /****************************** WWDG Instances ********************************/
|
|
|
4754 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
4755
|
|
|
4756 /****************************** SDIO Instances ********************************/
|
|
|
4757 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
|
|
|
4758
|
|
|
4759 /****************************** USB Exported Constants ************************/
|
|
|
4760 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
|
|
|
4761 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
|
|
|
4762 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
|
|
|
4763 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
|
|
|
4764
|
|
|
4765 /**
|
|
|
4766 * @}
|
|
|
4767 */
|
|
|
4768
|
|
|
4769 /**
|
|
|
4770 * @}
|
|
|
4771 */
|
|
|
4772
|
|
|
4773 /**
|
|
|
4774 * @}
|
|
|
4775 */
|
|
|
4776
|
|
|
4777 #ifdef __cplusplus
|
|
|
4778 }
|
|
|
4779 #endif /* __cplusplus */
|
|
|
4780
|
|
|
4781 #endif /* __STM32F411xE_H */
|
|
|
4782
|
|
|
4783
|
|
|
4784
|
|
|
4785 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
