annotate Common/Drivers/STM32F4xx_v220/Include/stm32f427xx.h @ 119:76fa42fc0b20 FlipDisplay

Cleanup writechar pointers Fill screen with 0 if a line is skipped
author Ideenmodellierer
date Sun, 06 Jan 2019 22:33:26 +0100
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1 /**
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2 ******************************************************************************
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3 * @file stm32f427xx.h
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief CMSIS STM32F427xx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral’s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS_Device
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32f427xx
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49 * @{
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50 */
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51
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52 #ifndef __stm32f427xx_H
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53 #define __stm32f427xx_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59 /** @addtogroup Configuration_section_for_CMSIS
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60 * @{
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61 */
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62
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63 /**
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64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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65 */
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66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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70 #define __FPU_PRESENT 1 /*!< FPU present */
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71
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72 /**
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73 * @}
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74 */
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75
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76 /** @addtogroup Peripheral_interrupt_number_definition
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77 * @{
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78 */
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79
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80 /**
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81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
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82 * in @ref Library_configuration_section
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83 */
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84 typedef enum
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85 {
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86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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95 /****** STM32 specific Interrupt Numbers **********************************************************************/
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96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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101 RCC_IRQn = 5, /*!< RCC global Interrupt */
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102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
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136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
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140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
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141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
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142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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144 FMC_IRQn = 48, /*!< FMC global Interrupt */
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145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
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149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
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150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
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158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
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159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
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160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
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161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
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162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
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163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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167 USART6_IRQn = 71, /*!< USART6 global interrupt */
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168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
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171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
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172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
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173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
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174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
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175 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
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176 FPU_IRQn = 81, /*!< FPU global interrupt */
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177 UART7_IRQn = 82, /*!< UART7 global interrupt */
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178 UART8_IRQn = 83, /*!< UART8 global interrupt */
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179 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
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180 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
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181 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
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182 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
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183 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
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184 } IRQn_Type;
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185
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186 /**
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187 * @}
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188 */
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189
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190 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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191 #include "system_stm32f4xx.h"
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192 #include <stdint.h>
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193
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194 /** @addtogroup Peripheral_registers_structures
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195 * @{
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196 */
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197
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198 /**
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199 * @brief Analog to Digital Converter
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200 */
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201
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202 typedef struct
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203 {
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204 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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205 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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206 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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207 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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208 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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209 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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210 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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211 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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212 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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213 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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214 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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215 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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216 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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217 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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218 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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219 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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220 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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221 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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222 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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223 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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224 } ADC_TypeDef;
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225
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226 typedef struct
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227 {
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228 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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229 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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230 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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231 AND triple modes, Address offset: ADC1 base address + 0x308 */
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232 } ADC_Common_TypeDef;
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233
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234
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235 /**
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236 * @brief Controller Area Network TxMailBox
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237 */
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238
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239 typedef struct
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240 {
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241 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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242 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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243 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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244 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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245 } CAN_TxMailBox_TypeDef;
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246
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247 /**
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248 * @brief Controller Area Network FIFOMailBox
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249 */
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250
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251 typedef struct
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252 {
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253 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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254 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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255 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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256 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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257 } CAN_FIFOMailBox_TypeDef;
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258
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259 /**
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260 * @brief Controller Area Network FilterRegister
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261 */
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262
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263 typedef struct
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264 {
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265 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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266 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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267 } CAN_FilterRegister_TypeDef;
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268
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269 /**
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270 * @brief Controller Area Network
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271 */
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272
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273 typedef struct
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274 {
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275 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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276 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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277 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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278 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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279 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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280 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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281 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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282 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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283 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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284 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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285 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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286 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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287 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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288 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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289 uint32_t RESERVED2; /*!< Reserved, 0x208 */
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290 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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291 uint32_t RESERVED3; /*!< Reserved, 0x210 */
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292 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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293 uint32_t RESERVED4; /*!< Reserved, 0x218 */
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294 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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295 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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296 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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297 } CAN_TypeDef;
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298
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299 /**
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300 * @brief CRC calculation unit
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301 */
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302
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303 typedef struct
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304 {
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305 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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306 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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307 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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308 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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309 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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310 } CRC_TypeDef;
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311
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312 /**
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313 * @brief Digital to Analog Converter
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314 */
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315
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316 typedef struct
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317 {
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318 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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319 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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320 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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321 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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322 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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323 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
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324 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
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325 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
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326 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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327 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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328 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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329 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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330 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
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331 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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332 } DAC_TypeDef;
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333
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334 /**
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335 * @brief Debug MCU
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336 */
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337
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338 typedef struct
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339 {
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340 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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341 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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342 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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343 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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344 }DBGMCU_TypeDef;
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345
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346 /**
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347 * @brief DCMI
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348 */
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349
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350 typedef struct
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351 {
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352 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
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353 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
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354 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
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355 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
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356 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
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357 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
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358 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
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359 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
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360 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
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361 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
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362 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
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363 } DCMI_TypeDef;
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364
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365 /**
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366 * @brief DMA Controller
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367 */
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368
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369 typedef struct
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370 {
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371 __IO uint32_t CR; /*!< DMA stream x configuration register */
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372 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
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373 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
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374 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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375 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
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376 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
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377 } DMA_Stream_TypeDef;
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378
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379 typedef struct
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380 {
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381 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
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382 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
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383 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
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384 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
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385 } DMA_TypeDef;
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386
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387 /**
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388 * @brief DMA2D Controller
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389 */
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390
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391 typedef struct
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392 {
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393 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
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394 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
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395 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
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396 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
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397 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
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398 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
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399 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
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400 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
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401 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
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402 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
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403 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
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404 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
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405 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
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406 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
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407 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
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408 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
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409 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
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410 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
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411 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
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412 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
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413 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
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414 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
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415 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
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416 } DMA2D_TypeDef;
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417
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418 /**
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419 * @brief Ethernet MAC
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420 */
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421
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422 typedef struct
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423 {
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424 __IO uint32_t MACCR;
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425 __IO uint32_t MACFFR;
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426 __IO uint32_t MACHTHR;
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427 __IO uint32_t MACHTLR;
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428 __IO uint32_t MACMIIAR;
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429 __IO uint32_t MACMIIDR;
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430 __IO uint32_t MACFCR;
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431 __IO uint32_t MACVLANTR; /* 8 */
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432 uint32_t RESERVED0[2];
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433 __IO uint32_t MACRWUFFR; /* 11 */
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434 __IO uint32_t MACPMTCSR;
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435 uint32_t RESERVED1[2];
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436 __IO uint32_t MACSR; /* 15 */
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437 __IO uint32_t MACIMR;
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438 __IO uint32_t MACA0HR;
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439 __IO uint32_t MACA0LR;
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440 __IO uint32_t MACA1HR;
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441 __IO uint32_t MACA1LR;
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442 __IO uint32_t MACA2HR;
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443 __IO uint32_t MACA2LR;
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444 __IO uint32_t MACA3HR;
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445 __IO uint32_t MACA3LR; /* 24 */
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446 uint32_t RESERVED2[40];
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447 __IO uint32_t MMCCR; /* 65 */
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448 __IO uint32_t MMCRIR;
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449 __IO uint32_t MMCTIR;
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450 __IO uint32_t MMCRIMR;
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451 __IO uint32_t MMCTIMR; /* 69 */
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452 uint32_t RESERVED3[14];
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453 __IO uint32_t MMCTGFSCCR; /* 84 */
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454 __IO uint32_t MMCTGFMSCCR;
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455 uint32_t RESERVED4[5];
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456 __IO uint32_t MMCTGFCR;
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457 uint32_t RESERVED5[10];
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458 __IO uint32_t MMCRFCECR;
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459 __IO uint32_t MMCRFAECR;
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460 uint32_t RESERVED6[10];
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461 __IO uint32_t MMCRGUFCR;
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462 uint32_t RESERVED7[334];
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463 __IO uint32_t PTPTSCR;
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464 __IO uint32_t PTPSSIR;
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465 __IO uint32_t PTPTSHR;
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466 __IO uint32_t PTPTSLR;
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467 __IO uint32_t PTPTSHUR;
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468 __IO uint32_t PTPTSLUR;
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469 __IO uint32_t PTPTSAR;
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470 __IO uint32_t PTPTTHR;
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471 __IO uint32_t PTPTTLR;
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472 __IO uint32_t RESERVED8;
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473 __IO uint32_t PTPTSSR;
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474 uint32_t RESERVED9[565];
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475 __IO uint32_t DMABMR;
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476 __IO uint32_t DMATPDR;
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477 __IO uint32_t DMARPDR;
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478 __IO uint32_t DMARDLAR;
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479 __IO uint32_t DMATDLAR;
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480 __IO uint32_t DMASR;
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481 __IO uint32_t DMAOMR;
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482 __IO uint32_t DMAIER;
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483 __IO uint32_t DMAMFBOCR;
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484 __IO uint32_t DMARSWTR;
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485 uint32_t RESERVED10[8];
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486 __IO uint32_t DMACHTDR;
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487 __IO uint32_t DMACHRDR;
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488 __IO uint32_t DMACHTBAR;
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489 __IO uint32_t DMACHRBAR;
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490 } ETH_TypeDef;
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491
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492 /**
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493 * @brief External Interrupt/Event Controller
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494 */
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495
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496 typedef struct
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497 {
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498 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
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499 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
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500 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
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501 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
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502 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
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503 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
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504 } EXTI_TypeDef;
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505
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506 /**
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507 * @brief FLASH Registers
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508 */
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509
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510 typedef struct
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511 {
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512 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
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513 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
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514 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
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515 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
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516 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
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517 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
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518 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
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519 } FLASH_TypeDef;
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520
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521 /**
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522 * @brief Flexible Memory Controller
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523 */
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524
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525 typedef struct
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526 {
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527 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
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528 } FMC_Bank1_TypeDef;
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529
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530 /**
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531 * @brief Flexible Memory Controller Bank1E
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532 */
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533
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534 typedef struct
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535 {
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536 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
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537 } FMC_Bank1E_TypeDef;
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538
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539 /**
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540 * @brief Flexible Memory Controller Bank2
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541 */
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542
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543 typedef struct
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544 {
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545 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
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546 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
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547 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
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548 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
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549 uint32_t RESERVED0; /*!< Reserved, 0x70 */
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550 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
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551 uint32_t RESERVED1; /*!< Reserved, 0x78 */
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552 uint32_t RESERVED2; /*!< Reserved, 0x7C */
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553 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
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554 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
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555 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
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556 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
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557 uint32_t RESERVED3; /*!< Reserved, 0x90 */
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558 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
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559 } FMC_Bank2_3_TypeDef;
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560
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561 /**
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562 * @brief Flexible Memory Controller Bank4
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563 */
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564
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565 typedef struct
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566 {
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567 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
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568 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
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569 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
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570 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
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571 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
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572 } FMC_Bank4_TypeDef;
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573
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574 /**
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575 * @brief Flexible Memory Controller Bank5_6
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576 */
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577
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578 typedef struct
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579 {
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580 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
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581 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
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582 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
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583 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
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584 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
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585 } FMC_Bank5_6_TypeDef;
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586
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587 /**
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588 * @brief General Purpose I/O
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589 */
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590
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591 typedef struct
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592 {
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593 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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594 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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595 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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596 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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597 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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598 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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599 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
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600 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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601 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
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602 } GPIO_TypeDef;
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603
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604 /**
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605 * @brief System configuration controller
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606 */
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607
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608 typedef struct
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609 {
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610 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
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611 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
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612 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
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613 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
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614 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
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615 } SYSCFG_TypeDef;
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616
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617 /**
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618 * @brief Inter-integrated Circuit Interface
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619 */
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620
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621 typedef struct
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622 {
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623 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
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624 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
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625 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
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626 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
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627 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
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628 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
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629 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
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630 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
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631 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
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632 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
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633 } I2C_TypeDef;
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634
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635 /**
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636 * @brief Independent WATCHDOG
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637 */
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638
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639 typedef struct
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640 {
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641 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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642 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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643 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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644 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
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645 } IWDG_TypeDef;
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646
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647 /**
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648 * @brief Power Control
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649 */
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650
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651 typedef struct
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652 {
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653 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
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654 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
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655 } PWR_TypeDef;
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656
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657 /**
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658 * @brief Reset and Clock Control
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659 */
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660
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661 typedef struct
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662 {
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663 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
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664 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
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665 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
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666 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
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667 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
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668 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
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669 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
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670 uint32_t RESERVED0; /*!< Reserved, 0x1C */
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671 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
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672 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
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673 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
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674 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
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675 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
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676 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
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677 uint32_t RESERVED2; /*!< Reserved, 0x3C */
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678 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
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679 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
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680 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
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681 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
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682 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
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683 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
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684 uint32_t RESERVED4; /*!< Reserved, 0x5C */
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685 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
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686 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
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687 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
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688 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
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689 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
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690 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
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691 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
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692 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
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693 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
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694 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
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695
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696 } RCC_TypeDef;
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697
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698 /**
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699 * @brief Real-Time Clock
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700 */
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701
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702 typedef struct
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703 {
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704 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
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705 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
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706 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
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707 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
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708 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
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709 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
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710 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
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711 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
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712 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
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713 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
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714 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
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715 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
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716 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
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717 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
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718 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
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719 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
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720 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
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721 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
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722 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
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723 uint32_t RESERVED7; /*!< Reserved, 0x4C */
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724 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
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725 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
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726 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
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727 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
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728 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
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729 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
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730 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
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731 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
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732 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
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733 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
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734 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
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735 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
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736 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
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737 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
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738 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
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739 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
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740 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
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741 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
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742 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
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743 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
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744 } RTC_TypeDef;
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745
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746 /**
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747 * @brief Serial Audio Interface
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748 */
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749
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750 typedef struct
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751 {
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752 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
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753 } SAI_TypeDef;
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754
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755 typedef struct
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756 {
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757 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
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758 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
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759 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
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760 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
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761 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
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762 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
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763 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
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764 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
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765 } SAI_Block_TypeDef;
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766
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767 /**
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768 * @brief SD host Interface
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769 */
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770
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771 typedef struct
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772 {
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773 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
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774 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
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775 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
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776 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
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777 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
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778 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
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779 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
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780 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
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781 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
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782 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
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783 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
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784 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
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785 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
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786 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
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787 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
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788 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
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789 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
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790 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
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791 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
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792 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
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793 } SDIO_TypeDef;
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794
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795 /**
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796 * @brief Serial Peripheral Interface
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797 */
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798
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799 typedef struct
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800 {
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801 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
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802 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
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803 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
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804 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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805 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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806 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
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807 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
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808 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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809 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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810 } SPI_TypeDef;
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811
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812 /**
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813 * @brief TIM
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814 */
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815
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816 typedef struct
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817 {
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818 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
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819 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
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820 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
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821 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
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822 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
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823 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
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824 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
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825 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
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826 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
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827 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
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828 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
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829 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
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830 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
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831 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
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832 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
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833 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
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834 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
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835 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
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836 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
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837 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
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838 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
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839 } TIM_TypeDef;
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840
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841 /**
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842 * @brief Universal Synchronous Asynchronous Receiver Transmitter
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843 */
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844
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845 typedef struct
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846 {
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847 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
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848 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
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849 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
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850 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
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851 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
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852 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
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853 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
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854 } USART_TypeDef;
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855
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856 /**
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857 * @brief Window WATCHDOG
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858 */
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859
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860 typedef struct
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861 {
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862 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
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863 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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864 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
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865 } WWDG_TypeDef;
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866
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867
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868 /**
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869 * @brief RNG
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870 */
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871
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872 typedef struct
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873 {
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874 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
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875 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
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876 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
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877 } RNG_TypeDef;
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878
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879
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880 /**
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881 * @brief __USB_OTG_Core_register
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882 */
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883 typedef struct
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884 {
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885 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
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886 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
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887 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
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888 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
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889 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
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890 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
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891 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
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892 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
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893 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
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894 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
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895 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
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896 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
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897 uint32_t Reserved30[2]; /* Reserved 030h*/
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898 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
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899 __IO uint32_t CID; /* User ID Register 03Ch*/
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900 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
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901 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
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902 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
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903 }
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904 USB_OTG_GlobalTypeDef;
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905
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906
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907 /**
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908 * @brief __device_Registers
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909 */
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910 typedef struct
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911 {
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912 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
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913 __IO uint32_t DCTL; /* dev Control Register 804h*/
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914 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
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915 uint32_t Reserved0C; /* Reserved 80Ch*/
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916 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
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917 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
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918 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
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919 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
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920 uint32_t Reserved20; /* Reserved 820h*/
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921 uint32_t Reserved9; /* Reserved 824h*/
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922 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
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923 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
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924 __IO uint32_t DTHRCTL; /* dev thr 830h*/
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925 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
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926 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
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927 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
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928 uint32_t Reserved40; /* dedicated EP mask 840h*/
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929 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
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930 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
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931 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
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932 }
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933 USB_OTG_DeviceTypeDef;
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934
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935
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936 /**
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937 * @brief __IN_Endpoint-Specific_Register
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938 */
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939 typedef struct
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940 {
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941 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
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942 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
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943 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
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944 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
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945 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
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946 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
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947 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
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948 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
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949 }
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950 USB_OTG_INEndpointTypeDef;
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951
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952
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953 /**
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954 * @brief __OUT_Endpoint-Specific_Registers
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955 */
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956 typedef struct
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957 {
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958 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
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959 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
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960 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
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961 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
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962 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
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963 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
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964 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
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965 }
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966 USB_OTG_OUTEndpointTypeDef;
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967
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968
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969 /**
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970 * @brief __Host_Mode_Register_Structures
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971 */
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972 typedef struct
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973 {
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974 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
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975 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
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976 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
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977 uint32_t Reserved40C; /* Reserved 40Ch*/
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978 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
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979 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
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980 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
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981 }
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982 USB_OTG_HostTypeDef;
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983
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984 /**
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985 * @brief __Host_Channel_Specific_Registers
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986 */
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987 typedef struct
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988 {
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989 __IO uint32_t HCCHAR;
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990 __IO uint32_t HCSPLT;
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991 __IO uint32_t HCINT;
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992 __IO uint32_t HCINTMSK;
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993 __IO uint32_t HCTSIZ;
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994 __IO uint32_t HCDMA;
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995 uint32_t Reserved[2];
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996 }
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997 USB_OTG_HostChannelTypeDef;
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998 /**
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999 * @}
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1000 */
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1001
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1002 /** @addtogroup Peripheral_memory_map
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1003 * @{
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1004 */
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1005 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */
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1006 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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1007 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
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1008 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
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1009 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
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1010 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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1011 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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1012 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
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1013 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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1014 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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1015 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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1016 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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1017 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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1018 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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1019 #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
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1020 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
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1021
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1022 /* Legacy defines */
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1023 #define SRAM_BASE SRAM1_BASE
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1024 #define SRAM_BB_BASE SRAM1_BB_BASE
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1025
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1026
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1027 /*!< Peripheral memory map */
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1028 #define APB1PERIPH_BASE PERIPH_BASE
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1029 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
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1030 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
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1031 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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1032
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1033 /*!< APB1 peripherals */
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1034 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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1035 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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1036 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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1037 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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1038 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
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1039 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
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1040 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
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1041 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
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1042 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
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1043 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
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1044 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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1045 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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1046 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
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1047 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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1048 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
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1049 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
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1050 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
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1051 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
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1052 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
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1053 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
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1054 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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1055 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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1056 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
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1057 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
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1058 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
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1059 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
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1060 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
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1061 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
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1062 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
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1063
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1064 /*!< APB2 peripherals */
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1065 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
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1066 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
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1067 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
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1068 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
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1069 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
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1070 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
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1071 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
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1072 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
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1073 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
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1074 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
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1075 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
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1076 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
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1077 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
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1078 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
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1079 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
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1080 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
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1081 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
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1082 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
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1083 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
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1084 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
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1085 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
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1086
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1087 /*!< AHB1 peripherals */
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1088 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
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1089 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
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1090 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
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1091 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
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1092 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
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1093 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
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1094 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
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1095 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
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1096 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
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1097 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
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1098 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
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1099 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
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1100 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
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1101 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
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1102 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
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1103 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
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1104 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
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1105 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
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1106 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
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1107 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
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1108 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
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1109 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
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1110 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
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1111 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
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1112 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
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1113 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
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1114 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
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1115 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
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1116 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
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1117 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
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1118 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
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1119 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
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1120 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
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1121 #define ETH_MAC_BASE (ETH_BASE)
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1122 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
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1123 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
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1124 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
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1125 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
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1126
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1127 /*!< AHB2 peripherals */
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1128 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
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1129 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
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1130
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1131 /*!< FMC Bankx registers base address */
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1132 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
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1133 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
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1134 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
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1135 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
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1136 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
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1137
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1138 /* Debug MCU registers base address */
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1139 #define DBGMCU_BASE ((uint32_t )0xE0042000)
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1140
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1141 /*!< USB registers base address */
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1142 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
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1143 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
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1144
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1145 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
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1146 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
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1147 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
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1148 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
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1149 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
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1150 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
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1151 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
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1152 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
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1153 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
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1154 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
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1155 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
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1156 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
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1157
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1158 /**
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1159 * @}
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1160 */
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1161
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1162 /** @addtogroup Peripheral_declaration
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1163 * @{
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1164 */
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1165 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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1166 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
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1167 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
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1168 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
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1169 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
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1170 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
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1171 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
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1172 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
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1173 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
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1174 #define RTC ((RTC_TypeDef *) RTC_BASE)
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1175 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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1176 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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1177 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
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1178 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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1179 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
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1180 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
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1181 #define USART2 ((USART_TypeDef *) USART2_BASE)
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1182 #define USART3 ((USART_TypeDef *) USART3_BASE)
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1183 #define UART4 ((USART_TypeDef *) UART4_BASE)
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1184 #define UART5 ((USART_TypeDef *) UART5_BASE)
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1185 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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1186 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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1187 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
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1188 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
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1189 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
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1190 #define PWR ((PWR_TypeDef *) PWR_BASE)
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1191 #define DAC ((DAC_TypeDef *) DAC_BASE)
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1192 #define UART7 ((USART_TypeDef *) UART7_BASE)
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1193 #define UART8 ((USART_TypeDef *) UART8_BASE)
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1194 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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1195 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
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1196 #define USART1 ((USART_TypeDef *) USART1_BASE)
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1197 #define USART6 ((USART_TypeDef *) USART6_BASE)
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1198 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
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1199 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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1200 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
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1201 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
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1202 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
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1203 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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1204 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
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1205 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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1206 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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1207 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
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1208 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
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1209 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
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1210 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
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1211 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
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1212 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
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1213 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
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1214 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
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1215
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1216 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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1217 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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1218 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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1219 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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1220 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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1221 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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1222 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
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1223 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
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1224 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
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1225 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
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1226 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
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1227 #define CRC ((CRC_TypeDef *) CRC_BASE)
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1228 #define RCC ((RCC_TypeDef *) RCC_BASE)
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1229 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
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1230 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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1231 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
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1232 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
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1233 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
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1234 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
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1235 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
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1236 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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1237 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
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1238 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
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1239 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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1240 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
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1241 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
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1242 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
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1243 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
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1244 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
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1245 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
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1246 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
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1247 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
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1248 #define ETH ((ETH_TypeDef *) ETH_BASE)
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1249 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
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1250 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
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1251 #define RNG ((RNG_TypeDef *) RNG_BASE)
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1252 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
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1253 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
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1254 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
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1255 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
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1256 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
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1257
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1258 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
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1259
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1260 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
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1261 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
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1262
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1263 /**
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1264 * @}
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1265 */
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1266
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1267 /** @addtogroup Exported_constants
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1268 * @{
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1269 */
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1270
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1271 /** @addtogroup Peripheral_Registers_Bits_Definition
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1272 * @{
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1273 */
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1274
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1275 /******************************************************************************/
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1276 /* Peripheral Registers_Bits_Definition */
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1277 /******************************************************************************/
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1278
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1279 /******************************************************************************/
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1280 /* */
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1281 /* Analog to Digital Converter */
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1282 /* */
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1283 /******************************************************************************/
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1284 /******************** Bit definition for ADC_SR register ********************/
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1285 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
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1286 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
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1287 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
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1288 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
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diff changeset
1289 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
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1290 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
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1291
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diff changeset
1292 /******************* Bit definition for ADC_CR1 register ********************/
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diff changeset
1293 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
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1294 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1295 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1296 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1297 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1298 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1299 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
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1300 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
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1301 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
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1302 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
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1303 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
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1304 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
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1305 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
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1306 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
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1307 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
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1308 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
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1309 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
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1310 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
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diff changeset
1311 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
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1312 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
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1313 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
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1314 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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1315 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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1316 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
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1317
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1318 /******************* Bit definition for ADC_CR2 register ********************/
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1319 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
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1320 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
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1321 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
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1322 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
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1323 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
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1324 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
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1325 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
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1326 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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1327 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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1328 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
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1329 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
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1330 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
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1331 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1332 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1333 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
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1334 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
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1335 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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1336 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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1337 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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1338 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
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1339 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
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1340 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
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1341 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
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1342 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
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1343
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1344 /****************** Bit definition for ADC_SMPR1 register *******************/
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1345 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
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1346 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1347 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1348 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1349 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
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1350 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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1351 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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1352 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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1353 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
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1354 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
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1355 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
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1356 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
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1357 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
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1358 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
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1359 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
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1360 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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1361 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
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1362 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
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1363 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
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1364 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
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1365 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
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1366 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1367 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1368 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1369 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
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1370 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
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1371 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
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1372 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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1373 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
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1374 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
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1375 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
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1376 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
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1377 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
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1378 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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1379 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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1380 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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1381
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1382 /****************** Bit definition for ADC_SMPR2 register *******************/
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1383 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
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1384 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1385 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1386 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1387 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
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1388 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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1389 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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1390 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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1391 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
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1392 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
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1393 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
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1394 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
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1395 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
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1396 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
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1397 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
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1398 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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1399 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
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1400 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
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1401 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
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1402 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
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1403 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
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1404 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1405 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1406 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1407 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
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1408 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
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diff changeset
1409 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1410 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1411 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1412 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1413 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1414 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1415 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1416 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1417 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1418 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1419 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1420 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1421 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1422 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1423
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1424 /****************** Bit definition for ADC_JOFR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1425 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1426
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1427 /****************** Bit definition for ADC_JOFR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1428 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1429
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1430 /****************** Bit definition for ADC_JOFR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1431 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1432
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heinrichsweikamp
parents:
diff changeset
1433 /****************** Bit definition for ADC_JOFR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1434 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1435
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1436 /******************* Bit definition for ADC_HTR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1437 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1438
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1439 /******************* Bit definition for ADC_LTR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1440 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1441
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1442 /******************* Bit definition for ADC_SQR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1443 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1444 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1445 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1446 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1447 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1448 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1449 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
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heinrichsweikamp
parents:
diff changeset
1450 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1451 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1452 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1453 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1454 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1455 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1456 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1457 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1458 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1459 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1460 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1461 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1462 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1463 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1464 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1465 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1466 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1467 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
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parents:
diff changeset
1468 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1469 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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parents:
diff changeset
1470 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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parents:
diff changeset
1471 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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parents:
diff changeset
1472
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parents:
diff changeset
1473 /******************* Bit definition for ADC_SQR2 register *******************/
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parents:
diff changeset
1474 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
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parents:
diff changeset
1475 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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parents:
diff changeset
1476 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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parents:
diff changeset
1477 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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parents:
diff changeset
1478 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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parents:
diff changeset
1479 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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diff changeset
1480 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
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parents:
diff changeset
1481 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1482 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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parents:
diff changeset
1483 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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parents:
diff changeset
1484 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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parents:
diff changeset
1485 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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parents:
diff changeset
1486 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
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parents:
diff changeset
1487 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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parents:
diff changeset
1488 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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parents:
diff changeset
1489 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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parents:
diff changeset
1490 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1491 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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parents:
diff changeset
1492 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
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parents:
diff changeset
1493 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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parents:
diff changeset
1494 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1495 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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heinrichsweikamp
parents:
diff changeset
1496 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1497 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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parents:
diff changeset
1498 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
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parents:
diff changeset
1499 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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diff changeset
1500 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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diff changeset
1501 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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parents:
diff changeset
1502 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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parents:
diff changeset
1503 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
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parents:
diff changeset
1504 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
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parents:
diff changeset
1505 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
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parents:
diff changeset
1506 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
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parents:
diff changeset
1507 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
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parents:
diff changeset
1508 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
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parents:
diff changeset
1509 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
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heinrichsweikamp
parents:
diff changeset
1510
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1511 /******************* Bit definition for ADC_SQR3 register *******************/
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heinrichsweikamp
parents:
diff changeset
1512 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
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diff changeset
1513 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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parents:
diff changeset
1514 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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parents:
diff changeset
1515 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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parents:
diff changeset
1516 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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parents:
diff changeset
1517 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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heinrichsweikamp
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diff changeset
1518 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
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heinrichsweikamp
parents:
diff changeset
1519 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1520 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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parents:
diff changeset
1521 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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parents:
diff changeset
1522 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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parents:
diff changeset
1523 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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diff changeset
1524 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
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heinrichsweikamp
parents:
diff changeset
1525 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1526 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
1527 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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parents:
diff changeset
1528 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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parents:
diff changeset
1529 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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diff changeset
1530 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
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heinrichsweikamp
parents:
diff changeset
1531 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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parents:
diff changeset
1532 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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parents:
diff changeset
1533 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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parents:
diff changeset
1534 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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diff changeset
1535 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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heinrichsweikamp
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diff changeset
1536 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
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heinrichsweikamp
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diff changeset
1537 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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parents:
diff changeset
1538 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1539 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1540 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1541 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1542 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1543 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1544 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1545 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1546 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1547 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1548
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1549 /******************* Bit definition for ADC_JSQR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1550 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1551 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1552 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1553 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1554 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1555 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1556 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1557 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1558 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1559 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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parents:
diff changeset
1560 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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parents:
diff changeset
1561 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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parents:
diff changeset
1562 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
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heinrichsweikamp
parents:
diff changeset
1563 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1564 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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parents:
diff changeset
1565 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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parents:
diff changeset
1566 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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parents:
diff changeset
1567 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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parents:
diff changeset
1568 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
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parents:
diff changeset
1569 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1570 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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parents:
diff changeset
1571 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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parents:
diff changeset
1572 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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parents:
diff changeset
1573 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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parents:
diff changeset
1574 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
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diff changeset
1575 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1576 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
1577
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heinrichsweikamp
parents:
diff changeset
1578 /******************* Bit definition for ADC_JDR1 register *******************/
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heinrichsweikamp
parents:
diff changeset
1579 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1580
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1581 /******************* Bit definition for ADC_JDR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1582 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1583
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1584 /******************* Bit definition for ADC_JDR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1585 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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heinrichsweikamp
parents:
diff changeset
1586
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1587 /******************* Bit definition for ADC_JDR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1588 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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heinrichsweikamp
parents:
diff changeset
1589
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1590 /******************** Bit definition for ADC_DR register ********************/
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heinrichsweikamp
parents:
diff changeset
1591 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
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parents:
diff changeset
1592 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
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heinrichsweikamp
parents:
diff changeset
1593
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1594 /******************* Bit definition for ADC_CSR register ********************/
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heinrichsweikamp
parents:
diff changeset
1595 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
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parents:
diff changeset
1596 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
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heinrichsweikamp
parents:
diff changeset
1597 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
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heinrichsweikamp
parents:
diff changeset
1598 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
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heinrichsweikamp
parents:
diff changeset
1599 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
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parents:
diff changeset
1600 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
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heinrichsweikamp
parents:
diff changeset
1601 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1602 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1603 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1604 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
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heinrichsweikamp
parents:
diff changeset
1605 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1606 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1607 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
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heinrichsweikamp
parents:
diff changeset
1608 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
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heinrichsweikamp
parents:
diff changeset
1609 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
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heinrichsweikamp
parents:
diff changeset
1610 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
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heinrichsweikamp
parents:
diff changeset
1611 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1612 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
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heinrichsweikamp
parents:
diff changeset
1613
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1614 /******************* Bit definition for ADC_CCR register ********************/
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heinrichsweikamp
parents:
diff changeset
1615 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
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parents:
diff changeset
1616 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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parents:
diff changeset
1617 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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parents:
diff changeset
1618 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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heinrichsweikamp
parents:
diff changeset
1619 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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heinrichsweikamp
parents:
diff changeset
1620 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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heinrichsweikamp
parents:
diff changeset
1621 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
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parents:
diff changeset
1622 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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parents:
diff changeset
1623 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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parents:
diff changeset
1624 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
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parents:
diff changeset
1625 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
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heinrichsweikamp
parents:
diff changeset
1626 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1627 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
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heinrichsweikamp
parents:
diff changeset
1628 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1629 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
1630 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
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heinrichsweikamp
parents:
diff changeset
1631 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1632 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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parents:
diff changeset
1633 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
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heinrichsweikamp
parents:
diff changeset
1634 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
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heinrichsweikamp
parents:
diff changeset
1635
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parents:
diff changeset
1636 /******************* Bit definition for ADC_CDR register ********************/
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heinrichsweikamp
parents:
diff changeset
1637 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1638 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
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heinrichsweikamp
parents:
diff changeset
1639
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heinrichsweikamp
parents:
diff changeset
1640 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1641 /* */
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heinrichsweikamp
parents:
diff changeset
1642 /* Controller Area Network */
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heinrichsweikamp
parents:
diff changeset
1643 /* */
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heinrichsweikamp
parents:
diff changeset
1644 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1645 /*!<CAN control and status registers */
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heinrichsweikamp
parents:
diff changeset
1646 /******************* Bit definition for CAN_MCR register ********************/
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parents:
diff changeset
1647 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
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diff changeset
1648 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
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parents:
diff changeset
1649 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
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parents:
diff changeset
1650 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
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parents:
diff changeset
1651 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
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parents:
diff changeset
1652 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
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heinrichsweikamp
parents:
diff changeset
1653 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
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heinrichsweikamp
parents:
diff changeset
1654 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
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heinrichsweikamp
parents:
diff changeset
1655 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
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parents:
diff changeset
1656 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
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heinrichsweikamp
parents:
diff changeset
1657 /******************* Bit definition for CAN_MSR register ********************/
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parents:
diff changeset
1658 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
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parents:
diff changeset
1659 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
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heinrichsweikamp
parents:
diff changeset
1660 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
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parents:
diff changeset
1661 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
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heinrichsweikamp
parents:
diff changeset
1662 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
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parents:
diff changeset
1663 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
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parents:
diff changeset
1664 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
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diff changeset
1665 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
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diff changeset
1666 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
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heinrichsweikamp
parents:
diff changeset
1667
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parents:
diff changeset
1668 /******************* Bit definition for CAN_TSR register ********************/
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heinrichsweikamp
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diff changeset
1669 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
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heinrichsweikamp
parents:
diff changeset
1670 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
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heinrichsweikamp
parents:
diff changeset
1671 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
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heinrichsweikamp
parents:
diff changeset
1672 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1673 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1674 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1675 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1676 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1677 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1678 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1679 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1680 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1681 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1682 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1683 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1684 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1685
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1686 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1687 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1688 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1689 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1690
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1691 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1692 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1693 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1694 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1695
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1696 /******************* Bit definition for CAN_RF0R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1697 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1698 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1699 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1700 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1701
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1702 /******************* Bit definition for CAN_RF1R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1703 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1704 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1705 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1706 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1707
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1708 /******************** Bit definition for CAN_IER register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1709 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1710 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1711 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1712 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1713 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1714 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1715 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1716 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1717 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1718 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1719 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1720 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1721 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1722 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1723 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1724 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1725 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1726 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1727 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1728
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1729
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1730 /******************** Bit definition for CAN_ESR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1731 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1732 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1733 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1734
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1735 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1736 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1737 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1738 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1739
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1740 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1741 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1742
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1743 /******************* Bit definition for CAN_BTR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1744 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1745 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1746 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1747 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1748 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1749 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1750 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1751 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1752 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1753 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1754 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1755 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1756 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1757 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1758 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1759
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1760
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1761 /*!<Mailbox registers */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1762 /****************** Bit definition for CAN_TI0R register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1763 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1764 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1765 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1766 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1767 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1768
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1769 /****************** Bit definition for CAN_TDT0R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1770 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1771 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1772 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1773
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1774 /****************** Bit definition for CAN_TDL0R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1775 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1776 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1777 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1778 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1779
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1780 /****************** Bit definition for CAN_TDH0R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1781 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1782 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1783 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1784 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1785
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1786 /******************* Bit definition for CAN_TI1R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1787 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1788 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1789 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1790 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1791 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1792
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1793 /******************* Bit definition for CAN_TDT1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1794 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1795 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1796 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1797
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1798 /******************* Bit definition for CAN_TDL1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1799 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1800 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1801 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1802 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1803
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1804 /******************* Bit definition for CAN_TDH1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1805 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1806 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1807 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1808 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1809
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1810 /******************* Bit definition for CAN_TI2R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1811 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1812 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1813 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1814 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1815 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1816
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1817 /******************* Bit definition for CAN_TDT2R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1818 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1819 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1820 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1821
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1822 /******************* Bit definition for CAN_TDL2R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1823 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1824 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1825 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1826 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1827
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1828 /******************* Bit definition for CAN_TDH2R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1829 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1830 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1831 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1832 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1833
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1834 /******************* Bit definition for CAN_RI0R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1835 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1836 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1837 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1838 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1839
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1840 /******************* Bit definition for CAN_RDT0R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1841 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1842 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1843 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1844
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1845 /******************* Bit definition for CAN_RDL0R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1846 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1847 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1848 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1849 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1850
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1851 /******************* Bit definition for CAN_RDH0R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1852 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1853 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1854 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1855 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1856
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1857 /******************* Bit definition for CAN_RI1R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1858 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1859 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1860 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1861 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1862
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1863 /******************* Bit definition for CAN_RDT1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1864 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1865 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1866 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1867
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1868 /******************* Bit definition for CAN_RDL1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1869 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1870 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1871 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1872 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1873
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1874 /******************* Bit definition for CAN_RDH1R register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1875 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1876 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1877 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1878 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1879
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1880 /*!<CAN filter registers */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1881 /******************* Bit definition for CAN_FMR register ********************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1882 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1883 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1884
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1885 /******************* Bit definition for CAN_FM1R register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1886 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1887 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1888 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1889 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1890 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1891 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1892 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1893 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1894 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1895 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1896 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1897 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1898 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1899 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1900 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1901 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1902 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1903 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1904 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1905 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1906 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1907 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1908 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1909 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1910 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1911 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1912 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1913 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1914 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1915
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1916 /******************* Bit definition for CAN_FS1R register *******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
1917 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
5f11787b4f42 include in ostc4 repository
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diff changeset
1918 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1919 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1920 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
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diff changeset
1921 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
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parents:
diff changeset
1922 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
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diff changeset
1923 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1924 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
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diff changeset
1925 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1926 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
5f11787b4f42 include in ostc4 repository
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diff changeset
1927 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
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diff changeset
1928 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
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diff changeset
1929 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
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diff changeset
1930 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
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diff changeset
1931 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
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diff changeset
1932 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
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diff changeset
1933 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
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1934 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
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diff changeset
1935 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
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diff changeset
1936 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
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diff changeset
1937 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
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diff changeset
1938 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
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diff changeset
1939 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
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diff changeset
1940 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
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diff changeset
1941 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
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diff changeset
1942 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
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diff changeset
1943 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
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1944 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
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1945 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
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1946
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diff changeset
1947 /****************** Bit definition for CAN_FFA1R register *******************/
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1948 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
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1949 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
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1950 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
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1951 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
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1952 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
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1953 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
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1954 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
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1955 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
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1956 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
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1957 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
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1958 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
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1959 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
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1960 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
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1961 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
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1962 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
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1963 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
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1964 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
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1965 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
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1966 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
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1967 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
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1968 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
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1969 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
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1970 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
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1971 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
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1972 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
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1973 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
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1974 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
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1975 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
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1976 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
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1977
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1978 /******************* Bit definition for CAN_FA1R register *******************/
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1979 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
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1980 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
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1981 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
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1982 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
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1983 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
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1984 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
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1985 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
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1986 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
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1987 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
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1988 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
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1989 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
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1990 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
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1991 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
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1992 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
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1993 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
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1994 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
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1995 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
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1996 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
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1997 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
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1998 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
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1999 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
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2000 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
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2001 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
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2002 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
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2003 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
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2004 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
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2005 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
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2006 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
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2007 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
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2008
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2009 /******************* Bit definition for CAN_F0R1 register *******************/
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2010 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
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2011 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
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2012 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
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2013 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
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2014 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
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2015 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
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2016 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
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2017 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
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2018 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
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2019 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
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2020 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
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2021 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
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2022 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
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2023 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
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2024 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
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2025 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
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2026 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
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2027 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
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2028 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
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2029 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
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2030 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
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2031 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
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2032 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
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2033 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
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2034 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
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2035 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
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2036 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
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2037 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
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2038 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
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2039 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
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2040 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
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2041 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
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2042
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2043 /******************* Bit definition for CAN_F1R1 register *******************/
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2044 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
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2045 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
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2046 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
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2047 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
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2048 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
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2049 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
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2050 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
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2051 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
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2052 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
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2053 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
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2054 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
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2055 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
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2056 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
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2057 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
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2058 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
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2059 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
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2060 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
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2061 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
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2062 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
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2063 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
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2064 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
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2065 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
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2066 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
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2067 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
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2068 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
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2069 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
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2070 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
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2071 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
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diff changeset
2072 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2073 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2074 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2075 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2076
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2077 /******************* Bit definition for CAN_F2R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2078 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2079 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2080 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2081 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2082 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2083 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2084 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2085 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2086 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2087 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2088 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2089 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2090 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2091 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2092 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2093 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2094 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2095 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2096 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2097 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2098 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2099 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2100 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2101 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2102 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2103 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2104 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2105 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2106 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2107 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2108 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2109 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2110
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2111 /******************* Bit definition for CAN_F3R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2112 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2113 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2114 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2115 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2116 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2117 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2118 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2119 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2120 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2121 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2122 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2123 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2124 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2125 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2126 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2127 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2128 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2129 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2130 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2131 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2132 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2133 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2134 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2135 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2136 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2137 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2138 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2139 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2140 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2141 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2142 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2143 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2144
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2145 /******************* Bit definition for CAN_F4R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2146 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2147 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2148 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2149 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2150 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2151 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2152 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2153 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2154 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2155 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2156 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2157 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2158 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2159 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2160 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2161 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2162 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2163 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2164 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2165 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2166 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2167 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2168 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2169 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2170 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2171 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2172 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2173 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2174 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2175 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2176 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2177 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2178
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2179 /******************* Bit definition for CAN_F5R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2180 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2181 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2182 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2183 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2184 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2185 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2186 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2187 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2188 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2189 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2190 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2191 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2192 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
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heinrichsweikamp
parents:
diff changeset
2193 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
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heinrichsweikamp
parents:
diff changeset
2194 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
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heinrichsweikamp
parents:
diff changeset
2195 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
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heinrichsweikamp
parents:
diff changeset
2196 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
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heinrichsweikamp
parents:
diff changeset
2197 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
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heinrichsweikamp
parents:
diff changeset
2198 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
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heinrichsweikamp
parents:
diff changeset
2199 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2200 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2201 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2202 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2203 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2204 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2205 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2206 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2207 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2208 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2209 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2210 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2211 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2212
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2213 /******************* Bit definition for CAN_F6R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2214 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2215 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2216 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2217 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2218 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2219 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2220 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2221 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2222 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2223 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2224 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2225 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2226 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2227 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2228 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2229 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2230 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2231 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2232 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2233 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2234 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2235 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2236 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2237 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2238 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2239 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2240 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2241 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2242 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2243 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2244 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2245 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2246
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2247 /******************* Bit definition for CAN_F7R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2248 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2249 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2250 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2251 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2252 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2253 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2254 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2255 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2256 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2257 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2258 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2259 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2260 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2261 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2262 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2263 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2264 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2265 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2266 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2267 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2268 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2269 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2270 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2271 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2272 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2273 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2274 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2275 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2276 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2277 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2278 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2279 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2280
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2281 /******************* Bit definition for CAN_F8R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2282 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2283 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2284 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2285 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2286 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2287 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2288 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2289 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2290 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2291 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2292 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2293 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2294 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2295 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2296 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2297 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2298 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2299 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2300 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2301 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2302 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2303 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2304 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2305 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2306 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2307 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2308 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2309 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2310 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2311 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2312 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2313 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2314
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2315 /******************* Bit definition for CAN_F9R1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2316 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2317 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2318 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2319 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2320 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2321 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2322 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2323 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2324 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2325 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2326 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2327 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2328 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2329 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2330 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2331 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2332 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2333 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2334 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2335 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2336 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2337 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2338 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2339 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2340 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2341 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2342 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2343 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2344 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2345 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2346 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2347 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2348
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2349 /******************* Bit definition for CAN_F10R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2350 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2351 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2352 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2353 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2354 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2355 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2356 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2357 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2358 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2359 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2360 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2361 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2362 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2363 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2364 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2365 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2366 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2367 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2368 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2369 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2370 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2371 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2372 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2373 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2374 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2375 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2376 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2377 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2378 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2379 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2380 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2381 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2382
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2383 /******************* Bit definition for CAN_F11R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2384 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2385 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2386 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2387 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2388 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2389 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2390 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2391 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2392 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2393 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2394 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2395 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2396 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2397 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2398 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2399 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2400 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2401 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2402 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2403 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2404 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2405 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2406 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2407 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2408 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2409 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2410 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2411 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2412 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2413 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2414 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2415 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2416
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2417 /******************* Bit definition for CAN_F12R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2418 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2419 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2420 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2421 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2422 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2423 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2424 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2425 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2426 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2427 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2428 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2429 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2430 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2431 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2432 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2433 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2434 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2435 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2436 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2437 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2438 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2439 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2440 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2441 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2442 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2443 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2444 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2445 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2446 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2447 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2448 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2449 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2450
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2451 /******************* Bit definition for CAN_F13R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2452 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2453 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2454 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2455 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2456 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2457 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2458 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2459 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2460 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2461 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2462 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2463 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2464 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2465 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2466 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2467 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2468 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2469 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2470 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2471 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2472 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2473 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2474 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2475 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2476 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2477 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2478 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2479 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2480 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2481 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2482 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2483 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2484
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2485 /******************* Bit definition for CAN_F0R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2486 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2487 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2488 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2489 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2490 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2491 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2492 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2493 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2494 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2495 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2496 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2497 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2498 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2499 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2500 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2501 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2502 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2503 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2504 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2505 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2506 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2507 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2508 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2509 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2510 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2511 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2512 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2513 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2514 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2515 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2516 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2517 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2518
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2519 /******************* Bit definition for CAN_F1R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2520 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2521 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2522 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2523 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2524 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2525 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2526 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2527 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2528 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2529 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2530 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2531 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2532 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2533 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2534 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2535 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2536 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2537 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2538 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2539 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2540 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2541 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2542 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2543 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2544 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2545 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2546 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2547 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2548 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2549 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2550 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2551 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2552
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2553 /******************* Bit definition for CAN_F2R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2554 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2555 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2556 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2557 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2558 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2559 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2560 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2561 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2562 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2563 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2564 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2565 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2566 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2567 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2568 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2569 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2570 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2571 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2572 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2573 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2574 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2575 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2576 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2577 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2578 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2579 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2580 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2581 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2582 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2583 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2584 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2585 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2586
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2587 /******************* Bit definition for CAN_F3R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2588 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2589 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2590 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2591 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2592 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2593 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2594 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2595 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2596 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2597 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2598 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2599 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2600 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2601 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2602 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2603 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2604 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2605 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2606 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2607 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2608 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2609 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2610 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2611 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2612 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2613 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2614 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2615 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2616 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2617 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2618 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2619 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2620
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2621 /******************* Bit definition for CAN_F4R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2622 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2623 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2624 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2625 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2626 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2627 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2628 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2629 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2630 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2631 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2632 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2633 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2634 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2635 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2636 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2637 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2638 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2639 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2640 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2641 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2642 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2643 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2644 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2645 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2646 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2647 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2648 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2649 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2650 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2651 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2652 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2653 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2654
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2655 /******************* Bit definition for CAN_F5R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2656 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2657 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2658 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2659 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2660 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2661 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2662 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2663 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2664 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2665 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2666 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2667 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2668 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2669 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2670 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2671 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2672 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2673 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2674 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2675 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2676 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2677 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2678 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2679 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2680 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2681 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2682 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2683 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2684 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2685 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2686 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2687 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2688
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2689 /******************* Bit definition for CAN_F6R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2690 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2691 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2692 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2693 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2694 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2695 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2696 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2697 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2698 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2699 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2700 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2701 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2702 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2703 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2704 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2705 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2706 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2707 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2708 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2709 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2710 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2711 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2712 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2713 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2714 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2715 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2716 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2717 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2718 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2719 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2720 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2721 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2722
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2723 /******************* Bit definition for CAN_F7R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2724 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2725 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2726 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2727 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2728 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2729 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2730 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2731 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2732 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2733 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2734 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2735 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2736 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2737 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2738 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2739 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2740 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2741 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2742 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2743 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2744 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2745 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2746 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2747 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2748 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2749 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2750 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2751 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2752 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2753 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2754 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2755 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2756
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2757 /******************* Bit definition for CAN_F8R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2758 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2759 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2760 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2761 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2762 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2763 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2764 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2765 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2766 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2767 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2768 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2769 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2770 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2771 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2772 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2773 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2774 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2775 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2776 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2777 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2778 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2779 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2780 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2781 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2782 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2783 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2784 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2785 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2786 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2787 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2788 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2789 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2790
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2791 /******************* Bit definition for CAN_F9R2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2792 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2793 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2794 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2795 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2796 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2797 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2798 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2799 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2800 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2801 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2802 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2803 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2804 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2805 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2806 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2807 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2808 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2809 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2810 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2811 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2812 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2813 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2814 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2815 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2816 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2817 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2818 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2819 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2820 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2821 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2822 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2823 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2824
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2825 /******************* Bit definition for CAN_F10R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2826 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2827 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2828 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2829 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2830 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2831 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2832 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2833 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2834 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2835 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2836 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2837 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2838 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2839 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2840 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2841 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2842 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2843 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2844 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2845 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2846 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2847 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2848 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2849 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2850 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2851 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2852 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2853 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2854 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2855 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2856 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2857 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2858
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2859 /******************* Bit definition for CAN_F11R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2860 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2861 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2862 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2863 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2864 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2865 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2866 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2867 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2868 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2869 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2870 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2871 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2872 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2873 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2874 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2875 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2876 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2877 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2878 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2879 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2880 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2881 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2882 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2883 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2884 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2885 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2886 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2887 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2888 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2889 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2890 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2891 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2892
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2893 /******************* Bit definition for CAN_F12R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2894 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2895 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2896 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2897 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2898 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2899 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2900 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2901 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2902 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2903 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2904 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2905 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2906 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2907 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2908 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2909 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2910 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2911 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2912 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2913 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2914 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2915 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2916 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2917 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2918 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2919 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2920 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2921 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2922 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2923 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2924 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2925 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2926
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2927 /******************* Bit definition for CAN_F13R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2928 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2929 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2930 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2931 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2932 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2933 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2934 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2935 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2936 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2937 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2938 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2939 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2940 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2941 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2942 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2943 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2944 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2945 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2946 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2947 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2948 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2949 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2950 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2951 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2952 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2953 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2954 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2955 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2956 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2957 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2958 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2959 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2960
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2961 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2962 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2963 /* CRC calculation unit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2964 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2965 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2966 /******************* Bit definition for CRC_DR register *********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2967 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2968
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2969
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2970 /******************* Bit definition for CRC_IDR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2971 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2972
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2973
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2974 /******************** Bit definition for CRC_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2975 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2976
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2977 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2978 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2979 /* Digital to Analog Converter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2980 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2981 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2982 /******************** Bit definition for DAC_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2983 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2984 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2985 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2986
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2987 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2988 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2989 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2990 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2991
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2992 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2993 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2994 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2995
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2996 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2997 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2998 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2999 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3000 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3001
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3002 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3003 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3004 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3005 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3006
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3007 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3008 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3009 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3010 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3011
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3012 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3013 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3014 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3015
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3016 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3017 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3018 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3019 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3020 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3021
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3022 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3023
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3024 /***************** Bit definition for DAC_SWTRIGR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3025 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3026 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3027
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3028 /***************** Bit definition for DAC_DHR12R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3029 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3030
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3031 /***************** Bit definition for DAC_DHR12L1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3032 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3033
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3034 /****************** Bit definition for DAC_DHR8R1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3035 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3036
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3037 /***************** Bit definition for DAC_DHR12R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3038 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3039
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3040 /***************** Bit definition for DAC_DHR12L2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3041 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3042
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3043 /****************** Bit definition for DAC_DHR8R2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3044 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3045
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3046 /***************** Bit definition for DAC_DHR12RD register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3047 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3048 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3049
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3050 /***************** Bit definition for DAC_DHR12LD register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3051 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3052 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3053
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3054 /****************** Bit definition for DAC_DHR8RD register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3055 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3056 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3057
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3058 /******************* Bit definition for DAC_DOR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3059 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3060
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3061 /******************* Bit definition for DAC_DOR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3062 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3063
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3064 /******************** Bit definition for DAC_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3065 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3066 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3067
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3068 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3069 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3070 /* Debug MCU */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3071 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3072 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3073
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3074 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3075 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3076 /* DCMI */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3077 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3078 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3079 /******************** Bits definition for DCMI_CR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3080 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3081 #define DCMI_CR_CM ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3082 #define DCMI_CR_CROP ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3083 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3084 #define DCMI_CR_ESS ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3085 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3086 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3087 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3088 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3089 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3090 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3091 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3092 #define DCMI_CR_CRE ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3093 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3094
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3095 /******************** Bits definition for DCMI_SR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3096 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3097 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3098 #define DCMI_SR_FNE ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3099
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3100 /******************** Bits definition for DCMI_RISR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3101 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3102 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3103 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3104 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3105 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3106
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3107 /******************** Bits definition for DCMI_IER register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3108 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3109 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3110 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3111 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3112 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3113
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3114 /******************** Bits definition for DCMI_MISR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3115 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3116 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3117 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3118 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3119 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3120
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3121 /******************** Bits definition for DCMI_ICR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3122 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3123 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3124 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3125 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3126 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3127
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3128 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3129 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3130 /* DMA Controller */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3131 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3132 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3133 /******************** Bits definition for DMA_SxCR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3134 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3135 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3136 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3137 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3138 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3139 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3140 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3141 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3142 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3143 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3144 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3145 #define DMA_SxCR_CT ((uint32_t)0x00080000)
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heinrichsweikamp
parents:
diff changeset
3146 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3147 #define DMA_SxCR_PL ((uint32_t)0x00030000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3148 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3149 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3150 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3151 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3152 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3153 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3154 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3155 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3156 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3157 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3158 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3159 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
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parents:
diff changeset
3160 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3161 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3162 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3163 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
3164 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
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parents:
diff changeset
3165 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
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parents:
diff changeset
3166 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
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parents:
diff changeset
3167 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3168 #define DMA_SxCR_EN ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
3169
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3170 /******************** Bits definition for DMA_SxCNDTR register **************/
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heinrichsweikamp
parents:
diff changeset
3171 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
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parents:
diff changeset
3172 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
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parents:
diff changeset
3173 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
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parents:
diff changeset
3174 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
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parents:
diff changeset
3175 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
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parents:
diff changeset
3176 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
3177 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
3178 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
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parents:
diff changeset
3179 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
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parents:
diff changeset
3180 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
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parents:
diff changeset
3181 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
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parents:
diff changeset
3182 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
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parents:
diff changeset
3183 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3184 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
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parents:
diff changeset
3185 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
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parents:
diff changeset
3186 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
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parents:
diff changeset
3187 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
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heinrichsweikamp
parents:
diff changeset
3188
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heinrichsweikamp
parents:
diff changeset
3189 /******************** Bits definition for DMA_SxFCR register ****************/
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heinrichsweikamp
parents:
diff changeset
3190 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3191 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
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heinrichsweikamp
parents:
diff changeset
3192 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
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parents:
diff changeset
3193 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
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parents:
diff changeset
3194 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
3195 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
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parents:
diff changeset
3196 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
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parents:
diff changeset
3197 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
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parents:
diff changeset
3198 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3199
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3200 /******************** Bits definition for DMA_LISR register *****************/
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heinrichsweikamp
parents:
diff changeset
3201 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3202 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3203 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3204 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3205 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
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parents:
diff changeset
3206 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3207 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
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parents:
diff changeset
3208 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3209 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3210 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
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parents:
diff changeset
3211 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3212 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3213 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
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parents:
diff changeset
3214 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
3215 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
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heinrichsweikamp
parents:
diff changeset
3216 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
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parents:
diff changeset
3217 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3218 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3219 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3220 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
3221
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3222 /******************** Bits definition for DMA_HISR register *****************/
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heinrichsweikamp
parents:
diff changeset
3223 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3224 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3225 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3226 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3227 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
3228 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3229 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3230 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3231 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3232 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
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parents:
diff changeset
3233 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
3234 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
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heinrichsweikamp
parents:
diff changeset
3235 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
3236 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
3237 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
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heinrichsweikamp
parents:
diff changeset
3238 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
3239 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
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parents:
diff changeset
3240 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
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parents:
diff changeset
3241 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
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parents:
diff changeset
3242 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
3243
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heinrichsweikamp
parents:
diff changeset
3244 /******************** Bits definition for DMA_LIFCR register ****************/
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heinrichsweikamp
parents:
diff changeset
3245 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3246 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
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heinrichsweikamp
parents:
diff changeset
3247 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
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heinrichsweikamp
parents:
diff changeset
3248 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
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heinrichsweikamp
parents:
diff changeset
3249 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
3250 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
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heinrichsweikamp
parents:
diff changeset
3251 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
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heinrichsweikamp
parents:
diff changeset
3252 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
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heinrichsweikamp
parents:
diff changeset
3253 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
3254 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
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heinrichsweikamp
parents:
diff changeset
3255 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
3256 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
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heinrichsweikamp
parents:
diff changeset
3257 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
3258 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
3259 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
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heinrichsweikamp
parents:
diff changeset
3260 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
3261 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
3262 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
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heinrichsweikamp
parents:
diff changeset
3263 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
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heinrichsweikamp
parents:
diff changeset
3264 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
3265
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heinrichsweikamp
parents:
diff changeset
3266 /******************** Bits definition for DMA_HIFCR register ****************/
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heinrichsweikamp
parents:
diff changeset
3267 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
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heinrichsweikamp
parents:
diff changeset
3268 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
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heinrichsweikamp
parents:
diff changeset
3269 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
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heinrichsweikamp
parents:
diff changeset
3270 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
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heinrichsweikamp
parents:
diff changeset
3271 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
3272 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
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heinrichsweikamp
parents:
diff changeset
3273 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
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heinrichsweikamp
parents:
diff changeset
3274 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
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parents:
diff changeset
3275 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
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diff changeset
3276 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3277 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3278 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3279 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3280 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3281 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3282 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3283 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3284 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3285 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3286 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3287
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3288
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3289 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3290 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3291 /* AHB Master DMA2D Controller (DMA2D) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3292 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3293 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3294
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3295 /******************** Bit definition for DMA2D_CR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3296
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3297 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3298 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3299 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3300 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3301 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3302 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3303 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3304 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3305 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3306 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3307
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3308 /******************** Bit definition for DMA2D_ISR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3309
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3310 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3311 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3312 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3313 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3314 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3315 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3316
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3317 /******************** Bit definition for DMA2D_IFSR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3318
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3319 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3320 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3321 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3322 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3323 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3324 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3325
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3326 /******************** Bit definition for DMA2D_FGMAR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3327
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3328 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3329
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3330 /******************** Bit definition for DMA2D_FGOR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3331
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3332 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3333
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3334 /******************** Bit definition for DMA2D_BGMAR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3335
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3336 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3337
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3338 /******************** Bit definition for DMA2D_BGOR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3339
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3340 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3341
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3342 /******************** Bit definition for DMA2D_FGPFCCR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3343
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3344 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3345 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3346 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3347 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3348 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3349 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3350
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3351 /******************** Bit definition for DMA2D_FGCOLR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3352
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3353 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3354 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3355 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3356
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3357 /******************** Bit definition for DMA2D_BGPFCCR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3358
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3359 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3360 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3361 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3362 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3363 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3364 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3365
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3366 /******************** Bit definition for DMA2D_BGCOLR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3367
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3368 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3369 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3370 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3371
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3372 /******************** Bit definition for DMA2D_FGCMAR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3373
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3374 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3375
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3376 /******************** Bit definition for DMA2D_BGCMAR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3377
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3378 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3379
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3380 /******************** Bit definition for DMA2D_OPFCCR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3381
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3382 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3383
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3384 /******************** Bit definition for DMA2D_OCOLR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3385
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3386 /*!<Mode_ARGB8888/RGB888 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3387
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3388 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3389 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3390 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3391 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3392
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3393 /*!<Mode_RGB565 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3394 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3395 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3396 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3397
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3398 /*!<Mode_ARGB1555 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3399 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3400 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3401 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3402 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3403
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3404 /*!<Mode_ARGB4444 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3405 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3406 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3407 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3408 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3409
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3410 /******************** Bit definition for DMA2D_OMAR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3411
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3412 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3413
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3414 /******************** Bit definition for DMA2D_OOR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3415
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3416 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3417
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3418 /******************** Bit definition for DMA2D_NLR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3419
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3420 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3421 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3422
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3423 /******************** Bit definition for DMA2D_LWR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3424
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3425 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3426
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3427 /******************** Bit definition for DMA2D_AMTCR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3428
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3429 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3430 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3431
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3432
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3433 /******************** Bit definition for DMA2D_FGCLUT register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3434
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3435 /******************** Bit definition for DMA2D_BGCLUT register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3436
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3437
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3438
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3439 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3440 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3441 /* External Interrupt/Event Controller */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3442 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3443 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3444 /******************* Bit definition for EXTI_IMR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3445 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3446 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3447 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3448 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3449 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3450 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3451 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3452 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3453 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3454 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3455 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3456 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3457 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3458 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3459 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3460 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3461 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3462 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3463 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3464 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3465
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3466 /******************* Bit definition for EXTI_EMR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3467 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3468 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3469 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3470 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3471 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3472 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3473 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3474 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3475 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3476 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3477 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3478 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3479 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3480 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3481 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3482 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3483 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3484 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3485 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3486 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3487
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3488 /****************** Bit definition for EXTI_RTSR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3489 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3490 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3491 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3492 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3493 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3494 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3495 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3496 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3497 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3498 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3499 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3500 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3501 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3502 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3503 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3504 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3505 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3506 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3507 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3508 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3509
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3510 /****************** Bit definition for EXTI_FTSR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3511 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3512 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3513 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3514 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3515 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3516 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3517 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3518 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3519 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3520 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3521 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3522 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3523 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3524 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3525 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3526 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3527 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3528 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3529 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3530 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3531
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3532 /****************** Bit definition for EXTI_SWIER register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3533 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3534 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3535 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3536 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3537 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3538 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3539 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3540 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3541 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3542 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3543 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3544 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3545 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3546 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3547 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3548 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3549 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3550 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3551 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3552 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3553
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3554 /******************* Bit definition for EXTI_PR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3555 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3556 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3557 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3558 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3559 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3560 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3561 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3562 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3563 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3564 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3565 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3566 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3567 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3568 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3569 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3570 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3571 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3572 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3573 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3574 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
3575
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parents:
diff changeset
3576 /******************************************************************************/
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parents:
diff changeset
3577 /* */
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parents:
diff changeset
3578 /* FLASH */
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parents:
diff changeset
3579 /* */
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parents:
diff changeset
3580 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3581 /******************* Bits definition for FLASH_ACR register *****************/
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parents:
diff changeset
3582 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
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parents:
diff changeset
3583 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
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parents:
diff changeset
3584 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
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parents:
diff changeset
3585 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
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parents:
diff changeset
3586 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
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parents:
diff changeset
3587 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
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parents:
diff changeset
3588 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
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parents:
diff changeset
3589 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
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parents:
diff changeset
3590 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
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parents:
diff changeset
3591 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
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parents:
diff changeset
3592 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
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parents:
diff changeset
3593 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
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parents:
diff changeset
3594 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
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parents:
diff changeset
3595 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
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parents:
diff changeset
3596 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
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parents:
diff changeset
3597 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
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parents:
diff changeset
3598 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
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parents:
diff changeset
3599 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
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diff changeset
3600 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
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parents:
diff changeset
3601 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
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diff changeset
3602 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
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parents:
diff changeset
3603 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
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parents:
diff changeset
3604 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
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parents:
diff changeset
3605 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
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parents:
diff changeset
3606
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parents:
diff changeset
3607 /******************* Bits definition for FLASH_SR register ******************/
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parents:
diff changeset
3608 #define FLASH_SR_EOP ((uint32_t)0x00000001)
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parents:
diff changeset
3609 #define FLASH_SR_SOP ((uint32_t)0x00000002)
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parents:
diff changeset
3610 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
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parents:
diff changeset
3611 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
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parents:
diff changeset
3612 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
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parents:
diff changeset
3613 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
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parents:
diff changeset
3614 #define FLASH_SR_BSY ((uint32_t)0x00010000)
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parents:
diff changeset
3615
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parents:
diff changeset
3616 /******************* Bits definition for FLASH_CR register ******************/
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parents:
diff changeset
3617 #define FLASH_CR_PG ((uint32_t)0x00000001)
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parents:
diff changeset
3618 #define FLASH_CR_SER ((uint32_t)0x00000002)
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parents:
diff changeset
3619 #define FLASH_CR_MER ((uint32_t)0x00000004)
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parents:
diff changeset
3620 #define FLASH_CR_MER1 FLASH_CR_MER
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parents:
diff changeset
3621 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
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parents:
diff changeset
3622 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
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parents:
diff changeset
3623 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
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parents:
diff changeset
3624 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
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parents:
diff changeset
3625 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
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parents:
diff changeset
3626 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
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parents:
diff changeset
3627 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
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parents:
diff changeset
3628 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
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parents:
diff changeset
3629 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
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parents:
diff changeset
3630 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
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parents:
diff changeset
3631 #define FLASH_CR_STRT ((uint32_t)0x00010000)
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parents:
diff changeset
3632 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
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parents:
diff changeset
3633 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
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parents:
diff changeset
3634
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parents:
diff changeset
3635 /******************* Bits definition for FLASH_OPTCR register ***************/
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parents:
diff changeset
3636 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
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parents:
diff changeset
3637 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
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parents:
diff changeset
3638 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
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parents:
diff changeset
3639 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
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parents:
diff changeset
3640 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
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parents:
diff changeset
3641 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
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parents:
diff changeset
3642 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
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parents:
diff changeset
3643 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
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parents:
diff changeset
3644 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
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parents:
diff changeset
3645 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
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parents:
diff changeset
3646 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
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parents:
diff changeset
3647 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
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parents:
diff changeset
3648 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
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parents:
diff changeset
3649 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
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parents:
diff changeset
3650 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
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parents:
diff changeset
3651 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
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parents:
diff changeset
3652 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
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parents:
diff changeset
3653 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
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parents:
diff changeset
3654 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
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parents:
diff changeset
3655 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
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parents:
diff changeset
3656 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
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parents:
diff changeset
3657 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
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parents:
diff changeset
3658 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
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parents:
diff changeset
3659 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
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parents:
diff changeset
3660 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
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parents:
diff changeset
3661 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
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parents:
diff changeset
3662 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
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parents:
diff changeset
3663 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
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parents:
diff changeset
3664 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
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parents:
diff changeset
3665 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
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parents:
diff changeset
3666 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
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parents:
diff changeset
3667 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
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parents:
diff changeset
3668 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
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parents:
diff changeset
3669
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parents:
diff changeset
3670 /****************** Bits definition for FLASH_OPTCR1 register ***************/
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heinrichsweikamp
parents:
diff changeset
3671 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
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parents:
diff changeset
3672 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
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diff changeset
3673 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
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parents:
diff changeset
3674 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
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diff changeset
3675 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
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diff changeset
3676 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
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diff changeset
3677 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
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parents:
diff changeset
3678 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
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diff changeset
3679 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
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diff changeset
3680 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
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diff changeset
3681 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
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diff changeset
3682 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
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diff changeset
3683 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
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diff changeset
3684
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parents:
diff changeset
3685 /******************************************************************************/
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parents:
diff changeset
3686 /* */
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parents:
diff changeset
3687 /* Flexible Memory Controller */
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parents:
diff changeset
3688 /* */
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heinrichsweikamp
parents:
diff changeset
3689 /******************************************************************************/
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parents:
diff changeset
3690 /****************** Bit definition for FMC_BCR1 register *******************/
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parents:
diff changeset
3691 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
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diff changeset
3692 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
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diff changeset
3693
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diff changeset
3694 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
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parents:
diff changeset
3695 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
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parents:
diff changeset
3696 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
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parents:
diff changeset
3697
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diff changeset
3698 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
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heinrichsweikamp
parents:
diff changeset
3699 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
3700 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3701
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3702 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3703 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3704 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3705 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3706 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3707 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3708 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3709 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3710 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3711 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3712 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3713
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3714 /****************** Bit definition for FMC_BCR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3715 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3716 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3717
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3718 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3719 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3720 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3721
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3722 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3723 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3724 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3725
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3726 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3727 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3728 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3729 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3730 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3731 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3732 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3733 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3734 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3735 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3736
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3737 /****************** Bit definition for FMC_BCR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3738 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3739 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3740
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3741 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3742 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3743 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3744
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3745 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3746 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3747 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3748
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3749 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3750 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3751 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3752 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3753 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3754 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3755 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3756 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3757 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3758 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3759
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3760 /****************** Bit definition for FMC_BCR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3761 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3762 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3763
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3764 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3765 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3766 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3767
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3768 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3769 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3770 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3771
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3772 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3773 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3774 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3775 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3776 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3777 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3778 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3779 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3780 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3781 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3782
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3783 /****************** Bit definition for FMC_BTR1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3784 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3785 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3786 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3787 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3788 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3789
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3790 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3791 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3792 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3793 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3794 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3795
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3796 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3797 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3798 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3799 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3800 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3801 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3802 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3803 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3804 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3805
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3806 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3807 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3808 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3809 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3810 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3811
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3812 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3813 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3814 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3815 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3816 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3817
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3818 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3819 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3820 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3821 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3822 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3823
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3824 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3825 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3826 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3827
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3828 /****************** Bit definition for FMC_BTR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3829 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3830 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3831 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3832 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3833 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3834
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3835 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3836 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3837 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3838 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3839 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3840
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3841 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3842 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3843 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3844 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3845 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3846 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3847 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3848 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3849 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3850
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3851 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3852 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3853 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3854 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3855 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3856
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3857 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3858 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3859 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3860 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3861 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3862
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3863 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3864 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3865 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3866 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3867 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3868
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3869 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3870 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3871 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3872
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3873 /******************* Bit definition for FMC_BTR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3874 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3875 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3876 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3877 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3878 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3879
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3880 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3881 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3882 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3883 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3884 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3885
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3886 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3887 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3888 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3889 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3890 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3891 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3892 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3893 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3894 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3895
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3896 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3897 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3898 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3899 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3900 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3901
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3902 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3903 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3904 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3905 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3906 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3907
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3908 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3909 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3910 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3911 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3912 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3913
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3914 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3915 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3916 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3917
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3918 /****************** Bit definition for FMC_BTR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3919 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3920 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3921 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3922 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3923 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3924
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3925 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3926 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3927 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3928 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3929 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3930
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3931 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3932 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3933 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3934 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3935 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3936 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3937 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3938 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3939 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3940
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3941 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3942 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3943 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3944 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3945 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3946
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3947 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3948 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3949 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3950 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3951 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3952
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3953 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3954 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3955 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3956 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3957 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3958
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3959 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3960 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3961 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3962
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3963 /****************** Bit definition for FMC_BWTR1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3964 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3965 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3966 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3967 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3968 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3969
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3970 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3971 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3972 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3973 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3974 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3975
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3976 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3977 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3978 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3979 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3980 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3981 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3982 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3983 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3984 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3985
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3986 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3987 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3988 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3989 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3990 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3991
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3992 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3993 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3994 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3995 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3996 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3997
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3998 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3999 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4000 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4001 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4002 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4003
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4004 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4005 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4006 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4007
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4008 /****************** Bit definition for FMC_BWTR2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4009 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4010 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4011 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4012 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4013 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4014
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4015 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4016 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4017 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4018 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4019 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4020
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4021 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4022 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4023 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4024 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4025 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4026 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4027 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4028 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4029 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4030
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4031 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4032 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4033 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4034 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4035 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4036
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4037 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4038 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4039 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4040 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4041 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4042
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4043 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4044 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4045 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4046 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4047 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4048
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4049 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4050 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4051 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4052
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4053 /****************** Bit definition for FMC_BWTR3 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4054 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4055 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4056 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4057 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4058 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4059
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4060 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4061 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4062 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4063 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4064 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4065
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4066 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4067 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4068 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4069 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4070 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4071 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4072 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4073 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4074 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4075
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4076 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4077 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4078 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4079 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4080 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4081
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4082 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4083 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4084 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4085 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4086 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4087
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4088 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4089 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4090 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4091 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4092 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4093
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4094 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4095 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4096 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4097
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4098 /****************** Bit definition for FMC_BWTR4 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4099 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4100 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4101 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4102 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4103 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4104
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4105 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4106 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4107 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4108 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4109 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4110
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4111 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4112 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4113 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4114 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4115 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4116 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4117 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4118 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4119 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4120
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4121 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4122 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4123 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4124 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4125 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4126
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4127 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4128 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4129 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4130 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4131 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4132
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4133 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4134 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4135 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4136 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4137 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4138
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4139 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4140 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4141 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4142
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4143 /****************** Bit definition for FMC_PCR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4144 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4145 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4146 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4147
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4148 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4149 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4150 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4151
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4152 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4153
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4154 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4155 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4156 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4157 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4158 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4159
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4160 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4161 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4162 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4163 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4164 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4165
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4166 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4167 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4168 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4169 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4170
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4171 /****************** Bit definition for FMC_PCR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4172 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4173 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4174 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4175
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4176 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4177 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4178 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4179
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4180 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4181
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4182 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4183 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4184 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4185 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4186 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4187
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4188 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4189 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4190 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4191 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4192 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4193
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4194 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4195 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4196 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4197 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4198
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4199 /****************** Bit definition for FMC_PCR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4200 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4201 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4202 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4203
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4204 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4205 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4206 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4207
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4208 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4209
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4210 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4211 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4212 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4213 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4214 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4215
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4216 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4217 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4218 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4219 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4220 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4221
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4222 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4223 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4224 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4225 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4226
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4227 /******************* Bit definition for FMC_SR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4228 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4229 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4230 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4231 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4232 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4233 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4234 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4235
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4236 /******************* Bit definition for FMC_SR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4237 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4238 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4239 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4240 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4241 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4242 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4243 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4244
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4245 /******************* Bit definition for FMC_SR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4246 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4247 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4248 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4249 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4250 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4251 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4252 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4253
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4254 /****************** Bit definition for FMC_PMEM2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4255 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4256 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4257 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4258 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4259 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4260 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4261 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4262 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4263 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4264
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4265 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4266 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4267 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4268 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4269 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4270 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4271 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4272 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4273 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4274
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4275 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4276 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4277 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4278 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4279 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4280 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4281 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4282 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4283 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4284
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4285 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4286 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4287 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4288 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4289 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4290 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4291 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4292 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4293 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4294
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4295 /****************** Bit definition for FMC_PMEM3 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4296 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4297 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4298 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4299 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4300 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4301 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4302 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4303 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4304 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4305
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4306 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4307 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4308 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4309 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4310 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4311 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4312 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4313 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4314 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4315
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4316 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4317 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4318 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4319 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4320 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4321 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4322 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4323 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4324 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4325
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4326 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4327 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4328 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4329 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4330 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4331 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4332 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4333 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4334 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4335
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4336 /****************** Bit definition for FMC_PMEM4 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4337 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4338 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4339 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4340 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4341 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4342 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4343 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4344 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4345 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4346
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4347 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4348 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4349 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4350 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4351 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4352 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4353 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4354 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4355 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4356
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4357 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4358 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4359 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4360 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4361 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4362 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4363 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4364 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4365 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4366
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4367 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4368 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4369 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4370 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4371 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4372 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4373 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4374 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4375 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4376
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4377 /****************** Bit definition for FMC_PATT2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4378 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4379 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4380 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4381 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4382 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4383 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4384 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4385 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4386 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4387
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4388 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4389 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4390 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4391 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4392 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4393 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4394 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4395 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4396 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4397
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4398 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4399 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4400 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4401 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4402 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4403 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4404 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4405 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4406 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4407
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4408 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4409 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4410 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4411 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4412 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4413 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4414 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4415 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4416 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4417
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4418 /****************** Bit definition for FMC_PATT3 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4419 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4420 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4421 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4422 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4423 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4424 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4425 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4426 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4427 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4428
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4429 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4430 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4431 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4432 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4433 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4434 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4435 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4436 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4437 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4438
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4439 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4440 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4441 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4442 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4443 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4444 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4445 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4446 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4447 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4448
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4449 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4450 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4451 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4452 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4453 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4454 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4455 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4456 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4457 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4458
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4459 /****************** Bit definition for FMC_PATT4 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4460 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4461 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4462 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4463 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4464 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4465 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4466 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4467 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4468 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4469
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4470 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4471 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4472 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4473 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4474 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4475 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4476 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4477 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4478 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4479
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4480 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4481 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4482 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4483 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4484 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4485 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4486 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4487 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4488 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4489
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4490 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4491 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4492 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4493 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4494 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4495 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4496 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4497 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4498 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4499
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4500 /****************** Bit definition for FMC_PIO4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4501 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4502 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4503 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4504 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4505 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4506 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4507 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4508 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4509 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4510
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4511 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4512 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4513 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4514 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4515 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4516 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4517 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4518 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4519 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4520
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4521 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4522 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4523 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4524 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4525 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4526 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4527 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4528 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4529 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4530
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4531 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4532 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4533 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4534 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4535 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4536 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4537 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4538 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4539 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4540
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4541 /****************** Bit definition for FMC_ECCR2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4542 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4543
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4544 /****************** Bit definition for FMC_ECCR3 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4545 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4546
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4547 /****************** Bit definition for FMC_SDCR1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4548 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4549 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4550 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4551
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4552 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4553 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4554 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4555
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4556 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4557 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4558 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4559
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4560 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4561
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4562 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4563 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4564 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4565
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4566 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4567
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4568 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4569 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4570 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4571
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4572 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4573
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4574 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4575 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4576 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4577
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4578 /****************** Bit definition for FMC_SDCR2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4579 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4580 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4581 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4582
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4583 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4584 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4585 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4586
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4587 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4588 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4589 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4590
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4591 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4592
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4593 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4594 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4595 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4596
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4597 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4598
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4599 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4600 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4601 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4602
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4603 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4604
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4605 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4606 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4607 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4608
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4609 /****************** Bit definition for FMC_SDTR1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4610 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4611 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4612 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4613 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4614 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4615
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4616 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4617 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4618 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4619 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4620 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4621
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4622 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4623 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4624 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4625 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4626 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4627
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4628 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4629 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4630 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4631 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4632
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4633 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4634 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4635 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4636 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4637
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4638 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4639 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4640 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4641 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4642
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4643 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4644 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4645 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4646 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4647
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4648 /****************** Bit definition for FMC_SDTR2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4649 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4650 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4651 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4652 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4653 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4654
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4655 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4656 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4657 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4658 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4659 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4660
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4661 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4662 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4663 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4664 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4665 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4666
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4667 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4668 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4669 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4670 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4671
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4672 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4673 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4674 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4675 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4676
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4677 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4678 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4679 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4680 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4681
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4682 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4683 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4684 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4685 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4686
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4687 /****************** Bit definition for FMC_SDCMR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4688 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4689 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4690 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4691 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4692
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4693 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4694
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4695 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4696
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4697 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4698 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4699 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4700 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4701 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4702
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4703 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4704
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4705 /****************** Bit definition for FMC_SDRTR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4706 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4707
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4708 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4709
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4710 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4711
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4712 /****************** Bit definition for FMC_SDSR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4713 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4714
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4715 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4716 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4717 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4718
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4719 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4720 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4721 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4722 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4723
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4724
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4725
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4726 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4727 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4728 /* General Purpose I/O */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4729 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4730 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4731 /****************** Bits definition for GPIO_MODER register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4732 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4733 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4734 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4735
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4736 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4737 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4738 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4739
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4740 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4741 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4742 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4743
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4744 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4745 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4746 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4747
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4748 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4749 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4750 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4751
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4752 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4753 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4754 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4755
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4756 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4757 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4758 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4759
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4760 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4761 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4762 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4763
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4764 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4765 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4766 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4767
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4768 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4769 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4770 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4771
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4772 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4773 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4774 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4775
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4776 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4777 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4778 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4779
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4780 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4781 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4782 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4783
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4784 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4785 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4786 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4787
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4788 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4789 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4790 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4791
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4792 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4793 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4794 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4795
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4796 /****************** Bits definition for GPIO_OTYPER register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4797 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4798 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4799 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4800 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4801 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4802 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4803 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4804 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4805 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4806 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4807 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4808 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4809 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4810 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4811 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4812 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4813
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4814 /****************** Bits definition for GPIO_OSPEEDR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4815 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4816 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4817 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4818
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4819 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4820 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4821 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4822
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4823 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4824 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4825 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4826
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4827 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4828 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4829 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4830
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4831 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4832 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4833 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4834
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4835 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4836 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4837 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4838
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4839 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4840 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4841 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4842
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4843 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4844 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4845 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4846
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4847 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4848 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4849 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4850
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4851 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4852 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4853 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4854
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4855 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4856 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4857 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4858
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4859 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4860 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4861 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4862
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4863 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4864 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4865 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4866
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4867 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4868 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4869 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4870
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4871 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4872 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4873 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
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heinrichsweikamp
parents:
diff changeset
4874
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4875 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
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heinrichsweikamp
parents:
diff changeset
4876 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4877 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4878
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4879 /****************** Bits definition for GPIO_PUPDR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4880 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
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heinrichsweikamp
parents:
diff changeset
4881 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
4882 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
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heinrichsweikamp
parents:
diff changeset
4883
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4884 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
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heinrichsweikamp
parents:
diff changeset
4885 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4886 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
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heinrichsweikamp
parents:
diff changeset
4887
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4888 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
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heinrichsweikamp
parents:
diff changeset
4889 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
4890 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
4891
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heinrichsweikamp
parents:
diff changeset
4892 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
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heinrichsweikamp
parents:
diff changeset
4893 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
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heinrichsweikamp
parents:
diff changeset
4894 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
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heinrichsweikamp
parents:
diff changeset
4895
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4896 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
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heinrichsweikamp
parents:
diff changeset
4897 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
4898 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
4899
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heinrichsweikamp
parents:
diff changeset
4900 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
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heinrichsweikamp
parents:
diff changeset
4901 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
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heinrichsweikamp
parents:
diff changeset
4902 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
4903
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4904 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
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4905 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
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4906 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
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4907
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4908 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
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4909 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
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4910 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
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4911
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4912 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
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4913 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
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4914 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
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4915
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4916 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
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4917 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
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4918 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
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4919
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4920 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
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4921 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
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4922 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
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4923
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4924 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
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4925 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
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4926 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
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4927
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4928 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
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4929 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
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4930 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
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4931
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4932 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
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4933 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
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4934 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
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4935
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4936 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
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4937 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
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4938 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
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4939
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4940 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
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4941 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
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4942 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
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4943
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4944 /****************** Bits definition for GPIO_IDR register *******************/
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4945 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
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4946 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
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4947 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
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4948 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
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4949 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
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4950 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
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4951 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
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4952 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
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4953 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
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4954 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
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4955 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
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4956 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
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4957 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
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4958 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
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4959 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
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4960 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
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4961 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
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4962 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
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4963 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
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4964 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
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4965 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
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4966 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
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4967 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
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4968 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
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4969 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
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4970 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
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4971 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
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4972 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
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4973 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
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4974 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
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4975 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
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4976 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
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4977 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
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4978
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4979 /****************** Bits definition for GPIO_ODR register *******************/
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4980 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
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4981 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
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4982 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
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4983 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
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4984 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
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4985 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
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4986 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
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4987 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
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4988 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
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4989 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
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4990 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
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4991 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
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4992 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
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4993 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
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4994 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
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4995 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
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4996 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
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4997 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
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4998 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
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4999 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
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5000 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
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5001 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
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5002 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
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5003 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
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5004 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
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5005 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
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5006 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
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5007 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
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5008 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
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5009 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
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5010 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
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5011 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
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5012 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
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5013
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5014 /****************** Bits definition for GPIO_BSRR register ******************/
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5015 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
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5016 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
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5017 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
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5018 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
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5019 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
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5020 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
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5021 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
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5022 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
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5023 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
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5024 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
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5025 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
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5026 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
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5027 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
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5028 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
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5029 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
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5030 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
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5031 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
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5032 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
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5033 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
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5034 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
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5035 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
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5036 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
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5037 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
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5038 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
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5039 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
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5040 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
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5041 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
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5042 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
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5043 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
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5044 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
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5045 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
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5046 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
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parents:
diff changeset
5047
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5048 /****************** Bit definition for GPIO_LCKR register *********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5049 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5050 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5051 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5052 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5053 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5054 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5055 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5056 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5057 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5058 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5059 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5060 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5061 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5062 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5063 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5064 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5065 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5066
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5067 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5068 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5069 /* Inter-integrated Circuit Interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5070 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5071 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5072 /******************* Bit definition for I2C_CR1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5073 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5074 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5075 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5076 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5077 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5078 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5079 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5080 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5081 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5082 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5083 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5084 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5085 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5086 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5087
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5088 /******************* Bit definition for I2C_CR2 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5089 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5090 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5091 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5092 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5093 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5094 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5095 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5096
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5097 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5098 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5099 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5100 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5101 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5102
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5103 /******************* Bit definition for I2C_OAR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5104 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5105 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5106
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5107 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5108 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5109 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5110 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5111 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5112 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5113 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5114 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5115 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5116 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5117
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5118 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5119
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5120 /******************* Bit definition for I2C_OAR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5121 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5122 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5123
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5124 /******************** Bit definition for I2C_DR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5125 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5126
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5127 /******************* Bit definition for I2C_SR1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5128 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5129 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5130 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5131 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5132 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5133 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5134 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5135 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5136 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5137 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5138 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5139 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5140 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5141 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5142
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5143 /******************* Bit definition for I2C_SR2 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5144 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5145 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5146 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5147 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5148 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5149 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5150 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5151 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5152
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5153 /******************* Bit definition for I2C_CCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5154 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5155 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5156 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5157
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5158 /****************** Bit definition for I2C_TRISE register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5159 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5160
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5161 /****************** Bit definition for I2C_FLTR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5162 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5163 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5164
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5165 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5166 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5167 /* Independent WATCHDOG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5168 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5169 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5170 /******************* Bit definition for IWDG_KR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5171 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5172
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5173 /******************* Bit definition for IWDG_PR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5174 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5175 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5176 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5177 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5178
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5179 /******************* Bit definition for IWDG_RLR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5180 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5181
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5182 /******************* Bit definition for IWDG_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5183 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5184 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5185
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5186
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5187 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5188 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5189 /* Power Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5190 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5191 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5192 /******************** Bit definition for PWR_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5193 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5194 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5195 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5196 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5197 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5198
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
5199 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5200 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5201 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5202 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5203
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5204 /*!< PVD level configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5205 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5206 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5207 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5208 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5209 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5210 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5211 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5212 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5213 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5214 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5215 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5216 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5217 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5218 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5219 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5220 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5221 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5222 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5223 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5224 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5225 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5226
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5227 /* Legacy define */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5228 #define PWR_CR_PMODE PWR_CR_VOS
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5229 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5230 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5231
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5232 /******************* Bit definition for PWR_CSR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5233 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5234 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5235 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5236 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5237 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5238 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5239 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5240 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5241 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5242 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5243
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5244 /* Legacy define */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5245 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5246
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5247 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5248 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5249 /* Reset and Clock Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5250 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5251 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5252 /******************** Bit definition for RCC_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5253 #define RCC_CR_HSION ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5254 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5255
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5256 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5257 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5258 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5259 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5260 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5261 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5262
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5263 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5264 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5265 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5266 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5267 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5268 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5269 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5270 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5271 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5272
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5273 #define RCC_CR_HSEON ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5274 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5275 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5276 #define RCC_CR_CSSON ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5277 #define RCC_CR_PLLON ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5278 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5279 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5280 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5281 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5282 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5283
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5284 /******************** Bit definition for RCC_PLLCFGR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5285 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5286 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5287 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5288 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5289 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5290 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5291 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5292
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5293 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5294 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5295 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5296 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5297 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5298 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5299 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5300 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5301 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5302 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
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heinrichsweikamp
parents:
diff changeset
5303
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5304 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
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parents:
diff changeset
5305 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5306 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
5307
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5308 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
5309 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5310 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
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heinrichsweikamp
parents:
diff changeset
5311
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parents:
diff changeset
5312 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
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parents:
diff changeset
5313 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5314 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5315 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5316 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5317
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heinrichsweikamp
parents:
diff changeset
5318 /******************** Bit definition for RCC_CFGR register ******************/
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heinrichsweikamp
parents:
diff changeset
5319 /*!< SW configuration */
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heinrichsweikamp
parents:
diff changeset
5320 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5321 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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heinrichsweikamp
parents:
diff changeset
5322 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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heinrichsweikamp
parents:
diff changeset
5323
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5324 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5325 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5326 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
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heinrichsweikamp
parents:
diff changeset
5327
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heinrichsweikamp
parents:
diff changeset
5328 /*!< SWS configuration */
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heinrichsweikamp
parents:
diff changeset
5329 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5330 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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heinrichsweikamp
parents:
diff changeset
5331 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5332
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5333 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5334 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5335 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5336
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5337 /*!< HPRE configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5338 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5339 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5340 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5341 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5342 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5343
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5344 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5345 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5346 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5347 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5348 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5349 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5350 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5351 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5352 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5353
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5354 /*!< PPRE1 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5355 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5356 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5357 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5358 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5359
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5360 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5361 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5362 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5363 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5364 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5365
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5366 /*!< PPRE2 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5367 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5368 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5369 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5370 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5371
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5372 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5373 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5374 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5375 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5376 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5377
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5378 /*!< RTCPRE configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5379 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5380 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5381 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5382 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5383 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5384 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5385
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5386 /*!< MCO1 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5387 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5388 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5389 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5390
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5391 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5392
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5393 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5394 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5395 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5396 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5397
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5398 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5399 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5400 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5401 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5402
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5403 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5404 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5405 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5406
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5407 /******************** Bit definition for RCC_CIR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5408 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5409 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5410 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5411 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5412 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5413 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5414 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5415 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5416 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5417 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5418 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5419 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5420 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5421 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5422 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5423 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5424 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5425 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5426 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5427 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5428 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5429 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5430 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5431
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5432 /******************** Bit definition for RCC_AHB1RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5433 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5434 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5435 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5436 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5437 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5438 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5439 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5440 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5441 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5442 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5443 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5444 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5445 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5446 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5447 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5448 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5449 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5450
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5451 /******************** Bit definition for RCC_AHB2RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5452 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5453 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5454 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5455
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5456 /******************** Bit definition for RCC_AHB3RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5457 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5458
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5459 /******************** Bit definition for RCC_APB1RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5460 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5461 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5462 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5463 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5464 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5465 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5466 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5467 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5468 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
5469 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
5470 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5471 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5472 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
5473 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
5474 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
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heinrichsweikamp
parents:
diff changeset
5475 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
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heinrichsweikamp
parents:
diff changeset
5476 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
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heinrichsweikamp
parents:
diff changeset
5477 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
5478 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
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heinrichsweikamp
parents:
diff changeset
5479 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5480 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
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heinrichsweikamp
parents:
diff changeset
5481 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
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parents:
diff changeset
5482 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
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heinrichsweikamp
parents:
diff changeset
5483 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
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parents:
diff changeset
5484 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
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heinrichsweikamp
parents:
diff changeset
5485
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heinrichsweikamp
parents:
diff changeset
5486 /******************** Bit definition for RCC_APB2RSTR register **************/
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parents:
diff changeset
5487 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
5488 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
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parents:
diff changeset
5489 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
5490 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
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parents:
diff changeset
5491 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
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parents:
diff changeset
5492 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
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parents:
diff changeset
5493 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
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parents:
diff changeset
5494 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
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parents:
diff changeset
5495 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
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parents:
diff changeset
5496 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
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parents:
diff changeset
5497 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
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parents:
diff changeset
5498 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
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parents:
diff changeset
5499 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
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parents:
diff changeset
5500 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
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parents:
diff changeset
5501 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
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parents:
diff changeset
5502
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heinrichsweikamp
parents:
diff changeset
5503 /* Old SPI1RST bit definition, maintained for legacy purpose */
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parents:
diff changeset
5504 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
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heinrichsweikamp
parents:
diff changeset
5505
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heinrichsweikamp
parents:
diff changeset
5506 /******************** Bit definition for RCC_AHB1ENR register ***************/
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parents:
diff changeset
5507 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
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parents:
diff changeset
5508 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
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parents:
diff changeset
5509 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
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parents:
diff changeset
5510 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
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heinrichsweikamp
parents:
diff changeset
5511 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
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parents:
diff changeset
5512 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
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parents:
diff changeset
5513 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
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parents:
diff changeset
5514 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
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parents:
diff changeset
5515 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
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parents:
diff changeset
5516 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
5517 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
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parents:
diff changeset
5518
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parents:
diff changeset
5519 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
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parents:
diff changeset
5520 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
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parents:
diff changeset
5521 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
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parents:
diff changeset
5522 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
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parents:
diff changeset
5523 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
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parents:
diff changeset
5524 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
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parents:
diff changeset
5525
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parents:
diff changeset
5526 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
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parents:
diff changeset
5527 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
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parents:
diff changeset
5528 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
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parents:
diff changeset
5529 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
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parents:
diff changeset
5530 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
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parents:
diff changeset
5531 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
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heinrichsweikamp
parents:
diff changeset
5532
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
5533 /******************** Bit definition for RCC_AHB2ENR register ***************/
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parents:
diff changeset
5534 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
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parents:
diff changeset
5535 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
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parents:
diff changeset
5536 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
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heinrichsweikamp
parents:
diff changeset
5537
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parents:
diff changeset
5538 /******************** Bit definition for RCC_AHB3ENR register ***************/
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heinrichsweikamp
parents:
diff changeset
5539 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
5540
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parents:
diff changeset
5541 /******************** Bit definition for RCC_APB1ENR register ***************/
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parents:
diff changeset
5542 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
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parents:
diff changeset
5543 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
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parents:
diff changeset
5544 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
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parents:
diff changeset
5545 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
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parents:
diff changeset
5546 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
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parents:
diff changeset
5547 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
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parents:
diff changeset
5548 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
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parents:
diff changeset
5549 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
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parents:
diff changeset
5550 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
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parents:
diff changeset
5551 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
5552 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
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heinrichsweikamp
parents:
diff changeset
5553 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
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heinrichsweikamp
parents:
diff changeset
5554 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
5555 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
5556 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
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parents:
diff changeset
5557 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
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parents:
diff changeset
5558 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
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parents:
diff changeset
5559 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
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parents:
diff changeset
5560 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
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parents:
diff changeset
5561 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
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heinrichsweikamp
parents:
diff changeset
5562 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
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parents:
diff changeset
5563 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
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heinrichsweikamp
parents:
diff changeset
5564 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
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parents:
diff changeset
5565 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
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parents:
diff changeset
5566 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
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heinrichsweikamp
parents:
diff changeset
5567
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
5568 /******************** Bit definition for RCC_APB2ENR register ***************/
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heinrichsweikamp
parents:
diff changeset
5569 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
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parents:
diff changeset
5570 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
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parents:
diff changeset
5571 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
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parents:
diff changeset
5572 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
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parents:
diff changeset
5573 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
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parents:
diff changeset
5574 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
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parents:
diff changeset
5575 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
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parents:
diff changeset
5576 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
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parents:
diff changeset
5577 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
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parents:
diff changeset
5578 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
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parents:
diff changeset
5579 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
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parents:
diff changeset
5580 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
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parents:
diff changeset
5581 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
5582 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
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parents:
diff changeset
5583 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
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parents:
diff changeset
5584 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
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parents:
diff changeset
5585 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
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heinrichsweikamp
parents:
diff changeset
5586
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parents:
diff changeset
5587 /******************** Bit definition for RCC_AHB1LPENR register *************/
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heinrichsweikamp
parents:
diff changeset
5588 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
5589 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
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heinrichsweikamp
parents:
diff changeset
5590 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
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heinrichsweikamp
parents:
diff changeset
5591 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
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heinrichsweikamp
parents:
diff changeset
5592 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
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parents:
diff changeset
5593 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
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parents:
diff changeset
5594 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
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parents:
diff changeset
5595 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
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parents:
diff changeset
5596 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
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parents:
diff changeset
5597 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
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parents:
diff changeset
5598 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
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parents:
diff changeset
5599
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5600 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
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diff changeset
5601 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
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diff changeset
5602 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
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diff changeset
5603 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
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diff changeset
5604 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
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diff changeset
5605 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
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diff changeset
5606 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
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diff changeset
5607 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
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diff changeset
5608 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5609
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5610 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5611 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5612 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5613 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5614 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5615 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5616
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5617 /******************** Bit definition for RCC_AHB2LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5618 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5619 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5620 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5621
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5622 /******************** Bit definition for RCC_AHB3LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5623 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5624
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5625 /******************** Bit definition for RCC_APB1LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5626 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5627 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5628 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5629 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5630 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5631 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5632 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5633 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5634 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5635 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5636 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5637 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5638 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5639 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5640 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5641 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5642 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5643 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5644 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5645 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5646 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5647 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5648 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5649 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5650 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5651
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5652 /******************** Bit definition for RCC_APB2LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5653 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5654 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5655 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5656 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5657 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5658 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5659 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5660 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5661 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5662 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5663 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5664 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5665 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5666 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5667 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5668 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5669 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5670
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5671 /******************** Bit definition for RCC_BDCR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5672 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5673 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5674 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5675
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5676 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5677 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5678 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5679
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5680 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5681 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5682
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5683 /******************** Bit definition for RCC_CSR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5684 #define RCC_CSR_LSION ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5685 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5686 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5687 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5688 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5689 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5690 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5691 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5692 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5693 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5694
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5695 /******************** Bit definition for RCC_SSCGR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5696 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5697 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5698 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5699 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5700
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5701 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5702 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5703 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5704 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5705 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5706 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5707 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5708 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5709 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5710 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5711 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5712
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5713 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5714 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5715 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5716 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5717 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5718
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5719 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5720 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5721 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5722 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5723
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5724
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5725 /******************** Bit definition for RCC_PLLSAICFGR register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5726 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5727 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5728 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5729 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5730 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5731 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5732 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5733 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5734 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5735 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5736
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5737 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5738 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5739 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5740 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5741 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5742
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5743 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5744 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5745 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5746 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5747
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5748 /******************** Bit definition for RCC_DCKCFGR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5749 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5750 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5751 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5752 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5753 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5754 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5755
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5756
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5757 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5758 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5759 /* RNG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5760 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5761 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5762 /******************** Bits definition for RNG_CR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5763 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5764 #define RNG_CR_IE ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5765
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5766 /******************** Bits definition for RNG_SR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5767 #define RNG_SR_DRDY ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5768 #define RNG_SR_CECS ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5769 #define RNG_SR_SECS ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5770 #define RNG_SR_CEIS ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5771 #define RNG_SR_SEIS ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5772
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5773 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5774 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5775 /* Real-Time Clock (RTC) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5776 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5777 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5778 /******************** Bits definition for RTC_TR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5779 #define RTC_TR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5780 #define RTC_TR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5781 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5782 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5783 #define RTC_TR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5784 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5785 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5786 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5787 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5788 #define RTC_TR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5789 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5790 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5791 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5792 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5793 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5794 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5795 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5796 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5797 #define RTC_TR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5798 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5799 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5800 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5801 #define RTC_TR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5802 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5803 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5804 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5805 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5806
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5807 /******************** Bits definition for RTC_DR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5808 #define RTC_DR_YT ((uint32_t)0x00F00000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5809 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5810 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5811 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5812 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5813 #define RTC_DR_YU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5814 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5815 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5816 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5817 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5818 #define RTC_DR_WDU ((uint32_t)0x0000E000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5819 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5820 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5821 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5822 #define RTC_DR_MT ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5823 #define RTC_DR_MU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5824 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5825 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5826 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5827 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5828 #define RTC_DR_DT ((uint32_t)0x00000030)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5829 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5830 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5831 #define RTC_DR_DU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5832 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5833 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5834 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5835 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5836
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5837 /******************** Bits definition for RTC_CR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5838 #define RTC_CR_COE ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5839 #define RTC_CR_OSEL ((uint32_t)0x00600000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5840 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5841 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5842 #define RTC_CR_POL ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5843 #define RTC_CR_COSEL ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5844 #define RTC_CR_BCK ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5845 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5846 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5847 #define RTC_CR_TSIE ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5848 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5849 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5850 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5851 #define RTC_CR_TSE ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5852 #define RTC_CR_WUTE ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5853 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5854 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5855 #define RTC_CR_DCE ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5856 #define RTC_CR_FMT ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5857 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5858 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5859 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5860 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5861 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5862 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5863 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5864
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5865 /******************** Bits definition for RTC_ISR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5866 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5867 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5868 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5869 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5870 #define RTC_ISR_TSF ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5871 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5872 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5873 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5874 #define RTC_ISR_INIT ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5875 #define RTC_ISR_INITF ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5876 #define RTC_ISR_RSF ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5877 #define RTC_ISR_INITS ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5878 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5879 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5880 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5881 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5882
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5883 /******************** Bits definition for RTC_PRER register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5884 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5885 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5886
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5887 /******************** Bits definition for RTC_WUTR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5888 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5889
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5890 /******************** Bits definition for RTC_CALIBR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5891 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5892 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5893
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5894 /******************** Bits definition for RTC_ALRMAR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5895 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5896 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5897 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5898 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5899 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5900 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5901 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5902 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5903 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5904 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5905 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5906 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5907 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5908 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5909 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5910 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5911 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5912 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5913 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5914 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5915 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5916 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5917 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5918 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5919 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5920 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5921 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5922 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5923 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5924 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5925 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5926 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5927 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5928 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5929 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5930 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5931 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5932 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5933 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5934 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5935
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5936 /******************** Bits definition for RTC_ALRMBR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5937 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5938 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5939 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5940 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5941 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5942 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5943 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5944 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5945 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5946 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5947 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5948 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5949 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5950 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5951 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5952 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5953 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5954 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5955 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5956 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5957 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5958 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5959 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5960 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5961 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5962 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5963 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5964 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5965 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5966 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5967 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5968 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5969 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5970 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5971 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5972 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5973 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5974 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5975 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5976 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5977
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5978 /******************** Bits definition for RTC_WPR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5979 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5980
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5981 /******************** Bits definition for RTC_SSR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5982 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5983
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5984 /******************** Bits definition for RTC_SHIFTR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5985 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5986 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5987
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5988 /******************** Bits definition for RTC_TSTR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5989 #define RTC_TSTR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5990 #define RTC_TSTR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5991 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5992 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5993 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5994 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5995 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5996 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5997 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5998 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
5999 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6000 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6001 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6002 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6003 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6004 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6005 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6006 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6007 #define RTC_TSTR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6008 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6009 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6010 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6011 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6012 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6013 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6014 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6015 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6016
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6017 /******************** Bits definition for RTC_TSDR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6018 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6019 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6020 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6021 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6022 #define RTC_TSDR_MT ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6023 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6024 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6025 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6026 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6027 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6028 #define RTC_TSDR_DT ((uint32_t)0x00000030)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6029 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6030 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6031 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6032 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6033 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6034 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6035 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6036
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6037 /******************** Bits definition for RTC_TSSSR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6038 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6039
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6040 /******************** Bits definition for RTC_CAL register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6041 #define RTC_CALR_CALP ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6042 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6043 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6044 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6045 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6046 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6047 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6048 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6049 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6050 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6051 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6052 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6053 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6054
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6055 /******************** Bits definition for RTC_TAFCR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6056 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6057 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6058 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6059 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6060 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6061 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6062 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6063 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6064 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6065 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6066 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6067 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6068 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6069 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6070 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6071 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6072 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6073 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6074 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6075 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6076
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6077 /******************** Bits definition for RTC_ALRMASSR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6078 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6079 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6080 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6081 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6082 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6083 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6084
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6085 /******************** Bits definition for RTC_ALRMBSSR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6086 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6087 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6088 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6089 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6090 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6091 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6092
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6093 /******************** Bits definition for RTC_BKP0R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6094 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6095
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6096 /******************** Bits definition for RTC_BKP1R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6097 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6098
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6099 /******************** Bits definition for RTC_BKP2R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6100 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6101
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6102 /******************** Bits definition for RTC_BKP3R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6103 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6104
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6105 /******************** Bits definition for RTC_BKP4R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6106 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6107
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6108 /******************** Bits definition for RTC_BKP5R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6109 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6110
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6111 /******************** Bits definition for RTC_BKP6R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6112 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6113
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6114 /******************** Bits definition for RTC_BKP7R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6115 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6116
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6117 /******************** Bits definition for RTC_BKP8R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6118 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6119
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6120 /******************** Bits definition for RTC_BKP9R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6121 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6122
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6123 /******************** Bits definition for RTC_BKP10R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6124 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6125
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6126 /******************** Bits definition for RTC_BKP11R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6127 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6128
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6129 /******************** Bits definition for RTC_BKP12R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6130 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6131
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6132 /******************** Bits definition for RTC_BKP13R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6133 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6134
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6135 /******************** Bits definition for RTC_BKP14R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6136 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6137
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6138 /******************** Bits definition for RTC_BKP15R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6139 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6140
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6141 /******************** Bits definition for RTC_BKP16R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6142 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6143
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6144 /******************** Bits definition for RTC_BKP17R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6145 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6146
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6147 /******************** Bits definition for RTC_BKP18R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6148 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6149
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6150 /******************** Bits definition for RTC_BKP19R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6151 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6152
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6153 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6154 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6155 /* Serial Audio Interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6156 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6157 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6158 /******************** Bit definition for SAI_GCR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6159 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6160 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6161 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6162
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6163 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6164 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6165 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6166
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6167 /******************* Bit definition for SAI_xCR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6168 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6169 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6170 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6171
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6172 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6173 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6174 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6175
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6176 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6177 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6178 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6179 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6180
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6181 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6182 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6183
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6184 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6185 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6186 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6187
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6188 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6189 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6190 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6191 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6192 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6193
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6194 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6195 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6196 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6197 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6198 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6199
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6200 /******************* Bit definition for SAI_xCR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6201 #define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6202 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6203 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6204
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6205 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6206 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6207 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6208 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6209
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6210 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6211 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6212 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6213 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6214 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6215 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6216 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6217
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6218 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6219
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6220 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6221 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6222 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6223
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6224 /****************** Bit definition for SAI_xFRCR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6225 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6226 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6227 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6228 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6229 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6230 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6231 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6232 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6233 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6234
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6235 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6236 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6237 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6238 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6239 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6240 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6241 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6242 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6243
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6244 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6245 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6246 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6247
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6248 /****************** Bit definition for SAI_xSLOTR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6249 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6250 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6251 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6252 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6253 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6254 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6255
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6256 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6257 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6258 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6259
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6260 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6261 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6262 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6263 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6264 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6265
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6266 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6267
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6268 /******************* Bit definition for SAI_xIMR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6269 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6270 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6271 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6272 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6273 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6274 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6275 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6276
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6277 /******************** Bit definition for SAI_xSR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6278 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6279 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6280 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6281 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6282 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6283 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6284 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6285
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6286 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6287 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6288 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6289 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6290
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6291 /****************** Bit definition for SAI_xCLRFR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6292 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6293 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6294 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6295 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6296 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6297 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6298 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6299
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6300 /****************** Bit definition for SAI_xDR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6301 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6302
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6303
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6304 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6305 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6306 /* SD host Interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6307 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6308 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6309 /****************** Bit definition for SDIO_POWER register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6310 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6311 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6312 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6313
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6314 /****************** Bit definition for SDIO_CLKCR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6315 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6316 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6317 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6318 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6319
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6320 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6321 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6322 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6323
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6324 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6325 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6326
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6327 /******************* Bit definition for SDIO_ARG register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6328 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6329
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6330 /******************* Bit definition for SDIO_CMD register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6331 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6332
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6333 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
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diff changeset
6334 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
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parents:
diff changeset
6335 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6336
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6337 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6338 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
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diff changeset
6339 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
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heinrichsweikamp
parents:
diff changeset
6340 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6341 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6342 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
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diff changeset
6343 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
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diff changeset
6344
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parents:
diff changeset
6345 /***************** Bit definition for SDIO_RESPCMD register *****************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6346 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6347
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6348 /****************** Bit definition for SDIO_RESP0 register ******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6349 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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heinrichsweikamp
parents:
diff changeset
6350
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6351 /****************** Bit definition for SDIO_RESP1 register ******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6352 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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heinrichsweikamp
parents:
diff changeset
6353
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heinrichsweikamp
parents:
diff changeset
6354 /****************** Bit definition for SDIO_RESP2 register ******************/
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parents:
diff changeset
6355 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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heinrichsweikamp
parents:
diff changeset
6356
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heinrichsweikamp
parents:
diff changeset
6357 /****************** Bit definition for SDIO_RESP3 register ******************/
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parents:
diff changeset
6358 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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heinrichsweikamp
parents:
diff changeset
6359
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heinrichsweikamp
parents:
diff changeset
6360 /****************** Bit definition for SDIO_RESP4 register ******************/
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parents:
diff changeset
6361 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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parents:
diff changeset
6362
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6363 /****************** Bit definition for SDIO_DTIMER register *****************/
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parents:
diff changeset
6364 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
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heinrichsweikamp
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diff changeset
6365
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6366 /****************** Bit definition for SDIO_DLEN register *******************/
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parents:
diff changeset
6367 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6368
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6369 /****************** Bit definition for SDIO_DCTRL register ******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6370 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6371 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6372 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
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parents:
diff changeset
6373 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
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diff changeset
6374
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parents:
diff changeset
6375 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
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diff changeset
6376 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
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parents:
diff changeset
6377 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
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parents:
diff changeset
6378 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
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parents:
diff changeset
6379 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
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diff changeset
6380
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diff changeset
6381 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
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parents:
diff changeset
6382 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
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parents:
diff changeset
6383 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
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heinrichsweikamp
parents:
diff changeset
6384 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6385
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parents:
diff changeset
6386 /****************** Bit definition for SDIO_DCOUNT register *****************/
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heinrichsweikamp
parents:
diff changeset
6387 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6388
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6389 /****************** Bit definition for SDIO_STA register ********************/
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parents:
diff changeset
6390 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
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parents:
diff changeset
6391 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
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diff changeset
6392 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
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parents:
diff changeset
6393 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
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parents:
diff changeset
6394 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
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parents:
diff changeset
6395 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
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parents:
diff changeset
6396 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
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heinrichsweikamp
parents:
diff changeset
6397 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
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parents:
diff changeset
6398 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
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heinrichsweikamp
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diff changeset
6399 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
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parents:
diff changeset
6400 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
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parents:
diff changeset
6401 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
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parents:
diff changeset
6402 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
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parents:
diff changeset
6403 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
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parents:
diff changeset
6404 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
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parents:
diff changeset
6405 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
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diff changeset
6406 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6407 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6408 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6409 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6410 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6411 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
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parents:
diff changeset
6412 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6413 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6414
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6415 /******************* Bit definition for SDIO_ICR register *******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6416 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6417 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6418 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6419 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6420 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6421 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6422 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6423 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6424 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6425 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
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heinrichsweikamp
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diff changeset
6426 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6427 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
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heinrichsweikamp
parents:
diff changeset
6428 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6429
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6430 /****************** Bit definition for SDIO_MASK register *******************/
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
6431 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6432 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6433 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6434 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
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heinrichsweikamp
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diff changeset
6435 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
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heinrichsweikamp
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diff changeset
6436 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6437 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
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heinrichsweikamp
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diff changeset
6438 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
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diff changeset
6439 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
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diff changeset
6440 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6441 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6442 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
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heinrichsweikamp
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diff changeset
6443 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6444 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
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heinrichsweikamp
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diff changeset
6445 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
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heinrichsweikamp
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diff changeset
6446 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
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heinrichsweikamp
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diff changeset
6447 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6448 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6449 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6450 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6451 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6452 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
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heinrichsweikamp
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diff changeset
6453 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
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heinrichsweikamp
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diff changeset
6454 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
6455
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diff changeset
6456 /***************** Bit definition for SDIO_FIFOCNT register *****************/
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diff changeset
6457 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
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diff changeset
6458
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
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diff changeset
6459 /****************** Bit definition for SDIO_FIFO register *******************/
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diff changeset
6460 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
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diff changeset
6461
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diff changeset
6462 /******************************************************************************/
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diff changeset
6463 /* */
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diff changeset
6464 /* Serial Peripheral Interface */
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diff changeset
6465 /* */
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parents:
diff changeset
6466 /******************************************************************************/
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parents:
diff changeset
6467 /******************* Bit definition for SPI_CR1 register ********************/
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diff changeset
6468 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
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parents:
diff changeset
6469 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
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diff changeset
6470 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
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diff changeset
6471
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diff changeset
6472 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
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diff changeset
6473 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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diff changeset
6474 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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diff changeset
6475 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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diff changeset
6476
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parents:
diff changeset
6477 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
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diff changeset
6478 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
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diff changeset
6479 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
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diff changeset
6480 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
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diff changeset
6481 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
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diff changeset
6482 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
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diff changeset
6483 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
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diff changeset
6484 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
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diff changeset
6485 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
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diff changeset
6486 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
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diff changeset
6487
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diff changeset
6488 /******************* Bit definition for SPI_CR2 register ********************/
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diff changeset
6489 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
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diff changeset
6490 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
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diff changeset
6491 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
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diff changeset
6492 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
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diff changeset
6493 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
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diff changeset
6494 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
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diff changeset
6495 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
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diff changeset
6496
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diff changeset
6497 /******************** Bit definition for SPI_SR register ********************/
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diff changeset
6498 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
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diff changeset
6499 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
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diff changeset
6500 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
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diff changeset
6501 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
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diff changeset
6502 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
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diff changeset
6503 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
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diff changeset
6504 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
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diff changeset
6505 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
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diff changeset
6506 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
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diff changeset
6507
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diff changeset
6508 /******************** Bit definition for SPI_DR register ********************/
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diff changeset
6509 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
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diff changeset
6510
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diff changeset
6511 /******************* Bit definition for SPI_CRCPR register ******************/
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diff changeset
6512 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
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diff changeset
6513
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diff changeset
6514 /****************** Bit definition for SPI_RXCRCR register ******************/
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diff changeset
6515 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
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diff changeset
6516
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diff changeset
6517 /****************** Bit definition for SPI_TXCRCR register ******************/
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diff changeset
6518 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
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diff changeset
6519
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diff changeset
6520 /****************** Bit definition for SPI_I2SCFGR register *****************/
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diff changeset
6521 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
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6522
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diff changeset
6523 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
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diff changeset
6524 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
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diff changeset
6525 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
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diff changeset
6526
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diff changeset
6527 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
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diff changeset
6528
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diff changeset
6529 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
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diff changeset
6530 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
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parents:
diff changeset
6531 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
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diff changeset
6532
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diff changeset
6533 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
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diff changeset
6534
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diff changeset
6535 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
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diff changeset
6536 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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parents:
diff changeset
6537 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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diff changeset
6538
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diff changeset
6539 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
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diff changeset
6540 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
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diff changeset
6541
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diff changeset
6542 /****************** Bit definition for SPI_I2SPR register *******************/
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diff changeset
6543 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
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parents:
diff changeset
6544 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
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diff changeset
6545 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
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diff changeset
6546
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diff changeset
6547 /******************************************************************************/
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parents:
diff changeset
6548 /* */
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parents:
diff changeset
6549 /* SYSCFG */
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parents:
diff changeset
6550 /* */
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diff changeset
6551 /******************************************************************************/
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parents:
diff changeset
6552 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
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diff changeset
6553 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
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parents:
diff changeset
6554 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
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diff changeset
6555 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
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diff changeset
6556 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
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diff changeset
6557
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diff changeset
6558 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
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diff changeset
6559 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
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diff changeset
6560
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diff changeset
6561 /****************** Bit definition for SYSCFG_PMC register ******************/
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diff changeset
6562 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
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parents:
diff changeset
6563 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
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parents:
diff changeset
6564 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
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diff changeset
6565 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
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diff changeset
6566
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diff changeset
6567 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
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diff changeset
6568 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
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diff changeset
6569 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
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diff changeset
6570
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diff changeset
6571 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
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diff changeset
6572 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
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diff changeset
6573 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
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diff changeset
6574 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
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6575 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
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parents:
diff changeset
6576 /**
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diff changeset
6577 * @brief EXTI0 configuration
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parents:
diff changeset
6578 */
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diff changeset
6579 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
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diff changeset
6580 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
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diff changeset
6581 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
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diff changeset
6582 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
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6583 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
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6584 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
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diff changeset
6585 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
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6586 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
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6587 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
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6588 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
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6589 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
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diff changeset
6590
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diff changeset
6591 /**
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diff changeset
6592 * @brief EXTI1 configuration
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diff changeset
6593 */
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6594 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
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diff changeset
6595 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
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6596 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
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6597 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
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diff changeset
6598 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
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diff changeset
6599 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
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6600 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
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6601 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6602 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6603 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6604 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6605
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6606
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6607 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6608 * @brief EXTI2 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6609 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6610 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6611 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6612 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6613 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6614 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6615 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6616 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6617 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6618 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6619 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6620 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6621
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6622
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6623 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6624 * @brief EXTI3 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6625 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6626 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6627 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6628 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6629 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6630 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6631 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6632 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6633 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6634 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6635 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6636 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6637
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6638
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6639 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6640 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6641 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6642 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6643 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6644 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6645 * @brief EXTI4 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6646 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6647 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6648 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6649 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6650 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6651 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6652 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6653 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6654 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6655 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6656 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6657 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6658
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6659 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6660 * @brief EXTI5 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6661 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6662 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6663 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6664 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6665 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6666 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6667 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6668 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6669 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6670 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6671 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6672 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6673
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6674 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6675 * @brief EXTI6 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6676 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6677 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6678 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6679 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6680 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6681 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6682 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6683 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6684 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6685 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6686 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6687 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6688
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6689
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6690 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6691 * @brief EXTI7 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6692 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6693 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6694 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6695 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6696 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6697 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6698 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6699 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6700 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6701 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6702 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6703 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6704
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6705 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6706 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6707 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6708 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6709 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6710
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6711 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6712 * @brief EXTI8 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6713 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6714 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6715 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6716 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6717 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6718 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6719 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6720 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6721 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6722 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6723 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6724
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6725 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6726 * @brief EXTI9 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6727 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6728 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6729 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6730 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6731 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6732 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6733 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6734 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6735 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6736 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6737 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6738
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6739
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6740 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6741 * @brief EXTI10 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6742 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6743 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6744 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6745 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6746 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6747 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6748 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6749 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6750 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6751 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6752 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6753
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6754
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6755 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6756 * @brief EXTI11 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6757 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6758 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6759 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6760 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6761 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6762 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6763 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6764 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6765 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6766 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6767 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6768
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6769
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6770 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6771 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6772 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6773 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6774 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6775 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6776 * @brief EXTI12 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6777 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6778 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6779 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6780 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6781 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6782 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6783 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6784 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6785 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6786 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6787 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6788
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6789
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6790 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6791 * @brief EXTI13 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6792 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6793 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6794 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6795 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6796 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6797 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6798 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6799 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6800 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6801 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6802 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6803
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6804
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6805 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6806 * @brief EXTI14 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6807 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6808 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6809 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6810 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6811 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6812 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6813 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6814 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6815 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6816 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6817 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6818
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6819
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6820 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6821 * @brief EXTI15 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6822 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6823 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6824 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6825 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6826 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6827 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6828 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6829 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6830 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6831 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6832 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6833
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6834 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6835 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6836 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6837
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6838 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6839 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6840 /* TIM */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6841 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6842 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6843 /******************* Bit definition for TIM_CR1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6844 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6845 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6846 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6847 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6848 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6849
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6850 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6851 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6852 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6853
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6854 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6855
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6856 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6857 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6858 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6859
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6860 /******************* Bit definition for TIM_CR2 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6861 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6862 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6863 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6864
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6865 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6866 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6867 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6868 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6869
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6870 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6871 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6872 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6873 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6874 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6875 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6876 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6877 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6878
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6879 /******************* Bit definition for TIM_SMCR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6880 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6881 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6882 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6883 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6884
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6885 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6886 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6887 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6888 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6889
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6890 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6891
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6892 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6893 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6894 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6895 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6896 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6897
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6898 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6899 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6900 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6901
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6902 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6903 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6904
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6905 /******************* Bit definition for TIM_DIER register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6906 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6907 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6908 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6909 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6910 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6911 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6912 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6913 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6914 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6915 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6916 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6917 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6918 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6919 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6920 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6921
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6922 /******************** Bit definition for TIM_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6923 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6924 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6925 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6926 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6927 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6928 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6929 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6930 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6931 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6932 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6933 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6934 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6935
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6936 /******************* Bit definition for TIM_EGR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6937 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6938 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6939 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6940 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6941 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6942 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6943 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6944 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6945
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6946 /****************** Bit definition for TIM_CCMR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6947 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6948 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6949 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6950
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6951 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6952 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6953
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6954 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6955 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6956 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6957 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6958
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6959 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6960
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6961 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6962 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6963 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6964
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6965 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6966 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6967
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6968 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6969 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6970 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6971 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6972
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6973 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6974
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6975 /*----------------------------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6976
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6977 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6978 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6979 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6980
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6981 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6982 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6983 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6984 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6985 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6986
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6987 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6988 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6989 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6990
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6991 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6992 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6993 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6994 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6995 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6996
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6997 /****************** Bit definition for TIM_CCMR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6998 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
6999 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7000 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7001
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7002 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7003 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7004
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7005 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7006 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7007 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7008 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7009
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7010 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7011
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7012 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7013 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7014 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7015
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7016 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7017 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7018
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7019 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7020 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7021 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7022 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7023
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7024 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7025
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7026 /*----------------------------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7027
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7028 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7029 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7030 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7031
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7032 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7033 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7034 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7035 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7036 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7037
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7038 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7039 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7040 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7041
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7042 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7043 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7044 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7045 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7046 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7047
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7048 /******************* Bit definition for TIM_CCER register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7049 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7050 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7051 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7052 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7053 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7054 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7055 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7056 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7057 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7058 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7059 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7060 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7061 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7062 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7063 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7064
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7065 /******************* Bit definition for TIM_CNT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7066 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7067
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7068 /******************* Bit definition for TIM_PSC register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7069 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7070
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7071 /******************* Bit definition for TIM_ARR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7072 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7073
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7074 /******************* Bit definition for TIM_RCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7075 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7076
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7077 /******************* Bit definition for TIM_CCR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7078 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7079
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7080 /******************* Bit definition for TIM_CCR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7081 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7082
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7083 /******************* Bit definition for TIM_CCR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7084 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7085
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7086 /******************* Bit definition for TIM_CCR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7087 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7088
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7089 /******************* Bit definition for TIM_BDTR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7090 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7091 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7092 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7093 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7094 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7095 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7096 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7097 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7098 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7099
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7100 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7101 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7102 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7103
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7104 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7105 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7106 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7107 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7108 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7109 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7110
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7111 /******************* Bit definition for TIM_DCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7112 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7113 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7114 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7115 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7116 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7117 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7118
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7119 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7120 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7121 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7122 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7123 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7124 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7125
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7126 /******************* Bit definition for TIM_DMAR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7127 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7128
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7129 /******************* Bit definition for TIM_OR register *********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7130 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7131 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7132 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7133 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7134 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7135 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7136
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7137
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7138 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7139 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7140 /* Universal Synchronous Asynchronous Receiver Transmitter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7141 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7142 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7143 /******************* Bit definition for USART_SR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7144 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7145 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7146 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7147 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7148 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7149 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7150 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7151 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7152 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7153 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7154
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7155 /******************* Bit definition for USART_DR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7156 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7157
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7158 /****************** Bit definition for USART_BRR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7159 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7160 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7161
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7162 /****************** Bit definition for USART_CR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7163 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7164 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7165 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7166 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7167 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7168 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7169 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7170 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7171 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7172 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7173 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7174 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7175 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7176 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7177 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7178
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7179 /****************** Bit definition for USART_CR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7180 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7181 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7182 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7183 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7184 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7185 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7186 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7187
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7188 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7189 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7190 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7191
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7192 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7193
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7194 /****************** Bit definition for USART_CR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7195 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7196 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7197 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7198 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7199 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7200 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7201 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7202 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7203 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7204 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7205 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7206 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7207
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7208 /****************** Bit definition for USART_GTPR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7209 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7210 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7211 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7212 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7213 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7214 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7215 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7216 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7217 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7218
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7219 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7220
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7221 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7222 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7223 /* Window WATCHDOG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7224 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7225 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7226 /******************* Bit definition for WWDG_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7227 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7228 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7229 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7230 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7231 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7232 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7233 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7234 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7235
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7236 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7237
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7238 /******************* Bit definition for WWDG_CFR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7239 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7240 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7241 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7242 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7243 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7244 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7245 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7246 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7247
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7248 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7249 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7250 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7251
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7252 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7253
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7254 /******************* Bit definition for WWDG_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7255 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7256
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7257
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7258 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7259 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7260 /* DBG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7261 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7262 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7263 /******************** Bit definition for DBGMCU_IDCODE register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7264 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7265 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7266
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7267 /******************** Bit definition for DBGMCU_CR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7268 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7269 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7270 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7271 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7272
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7273 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7274 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7275 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7276
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7277 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7278 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7279 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7280 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7281 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7282 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7283 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7284 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7285 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7286 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7287 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7288 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7289 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7290 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7291 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7292 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7293 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7294 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7295 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7296 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7297
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7298 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7299 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7300 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7301 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7302 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7303 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7304
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7305 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7306 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7307 /* Ethernet MAC Registers bits definitions */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7308 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7309 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7310 /* Bit definition for Ethernet MAC Control Register register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7311 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7312 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7313 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7314 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7315 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7316 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7317 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7318 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7319 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7320 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7321 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7322 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7323 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7324 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7325 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7326 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7327 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7328 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7329 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7330 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7331 a transmission attempt during retries after a collision: 0 =< r <2^k */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7332 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7333 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7334 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7335 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7336 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7337 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7338 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7339
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7340 /* Bit definition for Ethernet MAC Frame Filter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7341 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7342 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7343 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7344 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7345 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7346 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7347 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7348 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7349 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7350 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7351 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7352 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7353 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7354 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7355
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7356 /* Bit definition for Ethernet MAC Hash Table High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7357 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7358
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7359 /* Bit definition for Ethernet MAC Hash Table Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7360 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7361
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7362 /* Bit definition for Ethernet MAC MII Address Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7363 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7364 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7365 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7366 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7367 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7368 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7369 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7370 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7371 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7372 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7373
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7374 /* Bit definition for Ethernet MAC MII Data Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7375 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7376
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7377 /* Bit definition for Ethernet MAC Flow Control Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7378 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7379 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7380 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7381 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7382 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7383 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7384 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7385 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7386 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7387 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7388 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7389
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7390 /* Bit definition for Ethernet MAC VLAN Tag Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7391 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7392 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7393
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7394 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7395 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7396 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7397 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7398 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7399 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7400 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7401 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7402 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7403 RSVD - Filter1 Command - RSVD - Filter0 Command
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7404 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7405 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7406 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7407
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7408 /* Bit definition for Ethernet MAC PMT Control and Status Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7409 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7410 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7411 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7412 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7413 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7414 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7415 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
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heinrichsweikamp
parents:
diff changeset
7416
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7417 /* Bit definition for Ethernet MAC Status Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7418 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7419 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7420 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7421 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7422 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7423
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7424 /* Bit definition for Ethernet MAC Interrupt Mask Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7425 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7426 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7427
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7428 /* Bit definition for Ethernet MAC Address0 High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7429 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7430
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7431 /* Bit definition for Ethernet MAC Address0 Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7432 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7433
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7434 /* Bit definition for Ethernet MAC Address1 High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7435 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7436 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7437 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7438 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7439 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7440 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7441 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7442 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7443 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7444 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7445
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7446 /* Bit definition for Ethernet MAC Address1 Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7447 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7448
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7449 /* Bit definition for Ethernet MAC Address2 High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7450 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7451 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7452 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7453 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7454 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7455 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7456 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7457 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7458 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7459 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7460
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7461 /* Bit definition for Ethernet MAC Address2 Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7462 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7463
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7464 /* Bit definition for Ethernet MAC Address3 High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7465 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7466 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7467 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7468 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7469 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7470 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7471 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7472 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7473 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7474 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7475
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7476 /* Bit definition for Ethernet MAC Address3 Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7477 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7478
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7479 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7480 /* Ethernet MMC Registers bits definition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7481 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7482
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7483 /* Bit definition for Ethernet MMC Contol Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7484 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7485 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7486 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7487 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7488 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7489 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7490
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7491 /* Bit definition for Ethernet MMC Receive Interrupt Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7492 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7493 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7494 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7495
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7496 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7497 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7498 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7499 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7500
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7501 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7502 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7503 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7504 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7505
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7506 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7507 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7508 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7509 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7510
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7511 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7512 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7513
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7514 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7515 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7516
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7517 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7518 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7519
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7520 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7521 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7522
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7523 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7524 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7525
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7526 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7527 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7528
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7529 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7530 /* Ethernet PTP Registers bits definition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7531 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7532
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7533 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7534 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7535 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7536 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7537 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7538 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7539 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7540 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7541 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7542 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7543
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7544 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7545 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7546 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7547 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7548 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7549 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7550
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7551 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7552 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7553
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7554 /* Bit definition for Ethernet PTP Time Stamp High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7555 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7556
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7557 /* Bit definition for Ethernet PTP Time Stamp Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7558 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7559 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7560
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7561 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7562 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7563
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7564 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7565 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7566 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7567
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7568 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7569 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7570
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7571 /* Bit definition for Ethernet PTP Target Time High Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7572 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7573
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7574 /* Bit definition for Ethernet PTP Target Time Low Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7575 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7576
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7577 /* Bit definition for Ethernet PTP Time Stamp Status Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7578 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7579 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7580
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7581 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7582 /* Ethernet DMA Registers bits definition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7583 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7584
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7585 /* Bit definition for Ethernet DMA Bus Mode Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7586 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7587 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7588 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7589 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7590 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7591 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7592 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7593 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7594 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7595 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7596 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7597 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7598 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7599 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7600 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7601 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7602 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7603 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7604 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7605 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7606 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7607 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7608 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7609 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7610 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7611 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7612 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7613 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7614 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7615 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7616 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7617 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7618 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7619 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7620 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7621 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7622 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7623 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7624 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7625
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7626 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7627 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7628
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7629 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7630 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7631
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7632 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7633 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7634
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7635 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7636 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7637
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7638 /* Bit definition for Ethernet DMA Status Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7639 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7640 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7641 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7642 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7643 /* combination with EBS[2:0] for GetFlagStatus function */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7644 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7645 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7646 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7647 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7648 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7649 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7650 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7651 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7652 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7653 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7654 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7655 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7656 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7657 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7658 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7659 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7660 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7661 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7662 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7663 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7664 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7665 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7666 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7667 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7668 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7669 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7670 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7671 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7672 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7673 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7674 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7675 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7676
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7677 /* Bit definition for Ethernet DMA Operation Mode Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7678 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7679 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7680 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7681 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7682 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7683 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7684 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7685 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7686 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7687 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7688 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7689 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7690 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7691 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7692 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7693 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7694 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7695 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7696 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7697 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7698 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7699 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7700 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7701 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7702
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7703 /* Bit definition for Ethernet DMA Interrupt Enable Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7704 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7705 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7706 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7707 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7708 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7709 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7710 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7711 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7712 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7713 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7714 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7715 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7716 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7717 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7718 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7719
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7720 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7721 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7722 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7723 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7724 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7725
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7726 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7727 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7728
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7729 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7730 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7731
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7732 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7733 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7734
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7735 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7736 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7737
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7738 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7739 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7740 /* USB_OTG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7741 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7742 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7743 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7744 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7745 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7746 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7747 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7748 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7749 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7750 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7751 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7752 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7753 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7754
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7755 /******************** Bit definition forUSB_OTG_HCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7756
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7757 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7758 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7759 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7760 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7761
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7762 /******************** Bit definition forUSB_OTG_DCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7763
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7764 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7765 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7766 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7767 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7768
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7769 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7770 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7771 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7772 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7773 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7774 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7775 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7776 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7777
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7778 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7779 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7780 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7781
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7782 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7783 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7784 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7785
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7786 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7787 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7788 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7789 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7790
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7791 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7792 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7793 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7794 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7795 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7796 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7797 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7798
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7799 /******************** Bit definition forUSB_OTG_DCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7800 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7801 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7802 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7803 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7804
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7805 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7806 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7807 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7808 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7809 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7810 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7811 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7812 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7813 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7814
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7815 /******************** Bit definition forUSB_OTG_HFIR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7816 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7817
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7818 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7819 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7820 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7821
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7822 /******************** Bit definition forUSB_OTG_DSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7823 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7824
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7825 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7826 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7827 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7828 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7829 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7830
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7831 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7832 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7833
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7834 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7835 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7836 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7837 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7838 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7839 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7840 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7841 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7842
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7843 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7844
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7845 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7846 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7847 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7848 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7849 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7850 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7851 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7852
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7853 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7854 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7855 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7856 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7857 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7858 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7859 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7860 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7861 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7862 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7863 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7864 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7865 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7866 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7867 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7868 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7869 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7870 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7871
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7872 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7873 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7874 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7875 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7876 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7877 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7878
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7879 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7880 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7881 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7882 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7883 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7884 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7885 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7886 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7887
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7888 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7889 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7890 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7891 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7892 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7893 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7894 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7895 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7896 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7897
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7898 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7899 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7900
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7901 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7902 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7903 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7904 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7905 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7906 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7907 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7908 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7909 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7910
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7911 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7912 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7913 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7914 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7915 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7916 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7917 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7918 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7919 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7920
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7921 /******************** Bit definition forUSB_OTG_HAINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7922 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7923
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7924 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7925 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7926 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7927 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7928 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7929 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7930 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7931 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7932
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7933 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7934 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7935 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7936 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7937 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7938 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7939 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7940 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7941 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7942 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7943 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7944 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7945 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7946 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7947 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7948 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7949 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7950 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7951 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7952 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7953 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7954 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7955 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7956 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7957 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7958 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7959 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7960
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7961 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7962 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7963 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7964 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7965 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7966 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7967 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7968 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7969 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7970 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7971 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7972 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7973 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7974 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7975 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7976 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7977 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7978 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7979 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7980 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7981 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7982 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7983 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7984 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7985 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7986 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7987 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7988
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7989 /******************** Bit definition forUSB_OTG_DAINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7990 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7991 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7992
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7993 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7994 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7995
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7996 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7997 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7998 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
7999 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8000 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8001
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8002 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8003 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8004 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8005
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8006 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8007
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8008 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8009 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8010 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8011 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8012 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8013 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8014
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8015 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8016 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8017 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8018
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8019 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8020 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8021 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8022 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8023 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8024
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8025 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8026 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8027 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8028 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8029 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8030
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8031 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8032 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8033 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8034 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8035 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8036
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8037 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8038
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8039 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8040 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8041 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8042 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8043 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8044 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8045
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8046 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8047 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8048 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8049
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8050 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8051 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8052 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8053 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8054 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8055
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8056 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8057 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8058 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8059 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8060 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8061
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8062 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8063 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8064 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8065 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8066 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8067
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8068 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8069 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8070
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8071 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8072 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8073
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8074 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8075 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8076 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8077 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8078 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8079
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8080 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8081 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8082
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8083 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8084 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8085
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8086 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8087 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8088 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8089 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8090 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8091 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8092 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8093 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8094 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8095
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8096 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8097 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8098 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8099 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8100 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8101 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8102 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8103 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8104
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8105 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8106 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8107 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8108
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8109 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8110 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8111 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8112 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8113 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8114 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8115 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8116 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8117 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8118 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8119 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8120
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8121 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8122 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8123 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8124 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8125 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8126 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8127 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8128 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8129 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8130 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8131 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8132
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8133 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8134 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8135
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8136 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8137 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8138 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8139
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8140 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8141 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8142 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8143 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8144 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8145 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8146 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8147
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8148 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8149 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8150 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8151
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8152 /******************** Bit definition forUSB_OTG_CID register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8153 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8154
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8155 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8156 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8157 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8158 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8159 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8160 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8161 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8162 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8163 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8164 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8165
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8166 /******************** Bit definition forUSB_OTG_HPRT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8167 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8168 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8169 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8170 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8171 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8172 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8173 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8174 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8175 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8176
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8177 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8178 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8179 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8180 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8181
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8182 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8183 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8184 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8185 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8186 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8187
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8188 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8189 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8190 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8191
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8192 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8193 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8194 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8195 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8196 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8197 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8198 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8199 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8200 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8201 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8202 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8203 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8204
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8205 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8206 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8207 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8208
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8209 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8210 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8211 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8212 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8213 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8214
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8215 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8216 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8217 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8218 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8219
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8220 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8221 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8222 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8223 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8224 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8225 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8226 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8227 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8228 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8229 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8230 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8231
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8232 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8233 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8234
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8235 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8236 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8237 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8238 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8239 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8240 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8241 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8242
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8243 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8244 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8245 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8246
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8247 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8248 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8249 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8250
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8251 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8252 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8253 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8254 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8255 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8256 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8257 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8258 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8259 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8260 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8261 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8262
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8263 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8264
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8265 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8266 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8267 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8268 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8269 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8270 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8271 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8272 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8273
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8274 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8275 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8276 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8277 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8278 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8279 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8280 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8281 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8282
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8283 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8284 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8285 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8286 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8287 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8288
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8289 /******************** Bit definition forUSB_OTG_HCINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8290 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8291 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8292 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8293 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8294 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8295 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8296 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8297 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8298 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8299 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8300 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8301
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8302 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8303 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8304 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8305 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8306 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8307 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8308 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8309 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8310 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8311 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8312 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8313 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8314
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8315 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8316 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8317 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8318 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8319 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8320 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8321 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8322 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8323 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8324 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8325 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8326 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8327
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8328 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8329
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8330 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8331 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8332 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8333 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8334 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8335 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8336 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8337 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8338 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8339 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8340
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8341 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8342 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8343
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8344 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8345 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8346
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8347 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8348 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8349
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8350 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8351 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8352 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8353
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8354 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8355
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8356 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8357 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8358 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8359 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8360 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8361 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8362 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8363 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8364 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8365 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8366 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8367 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8368 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8369 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8370
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8371 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8372 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8373 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8374 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8375 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8376 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8377 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8378
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8379 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8380
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8381 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8382 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8383
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8384 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8385 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8386 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8387
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8388 /******************** Bit definition for PCGCCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8389 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8390 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8391 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8392
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8393
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8394 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8395 * @}
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8396 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8397
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8398 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8399 * @}
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8400 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8401
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8402 /** @addtogroup Exported_macros
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8403 * @{
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8404 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8405
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8406 /******************************* ADC Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8407 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8408 ((INSTANCE) == ADC2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8409 ((INSTANCE) == ADC3))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8410
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8411 /******************************* CAN Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8412 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8413 ((INSTANCE) == CAN2))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8414
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8415 /******************************* CRC Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8416 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8417
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8418 /******************************* DAC Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8419 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8420
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8421 /******************************* DCMI Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8422 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8423
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8424 /******************************* DMA2D Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8425 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8426
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8427 /******************************** DMA Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8428 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8429 ((INSTANCE) == DMA1_Stream1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8430 ((INSTANCE) == DMA1_Stream2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8431 ((INSTANCE) == DMA1_Stream3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8432 ((INSTANCE) == DMA1_Stream4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8433 ((INSTANCE) == DMA1_Stream5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8434 ((INSTANCE) == DMA1_Stream6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8435 ((INSTANCE) == DMA1_Stream7) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8436 ((INSTANCE) == DMA2_Stream0) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8437 ((INSTANCE) == DMA2_Stream1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8438 ((INSTANCE) == DMA2_Stream2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8439 ((INSTANCE) == DMA2_Stream3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8440 ((INSTANCE) == DMA2_Stream4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8441 ((INSTANCE) == DMA2_Stream5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8442 ((INSTANCE) == DMA2_Stream6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8443 ((INSTANCE) == DMA2_Stream7))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8444
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8445 /******************************* GPIO Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8446 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8447 ((INSTANCE) == GPIOB) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8448 ((INSTANCE) == GPIOC) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8449 ((INSTANCE) == GPIOD) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8450 ((INSTANCE) == GPIOE) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8451 ((INSTANCE) == GPIOF) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8452 ((INSTANCE) == GPIOG) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8453 ((INSTANCE) == GPIOH) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8454 ((INSTANCE) == GPIOI) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8455 ((INSTANCE) == GPIOJ) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8456 ((INSTANCE) == GPIOK))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8457
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8458 /******************************** I2C Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8459 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8460 ((INSTANCE) == I2C2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8461 ((INSTANCE) == I2C3))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8462
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8463 /******************************** I2S Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8464 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8465 ((INSTANCE) == SPI3))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8466
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8467 /*************************** I2S Extended Instances ***************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8468 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8469 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8470 ((INSTANCE) == I2S2ext) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8471 ((INSTANCE) == I2S3ext))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8472
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8473 /******************************* RNG Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8474 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8475
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8476 /****************************** RTC Instances *********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8477 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8478
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8479 /******************************* SAI Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8480 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8481 ((PERIPH) == SAI1_Block_B))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8482
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8483 /******************************** SPI Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8484 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8485 ((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8486 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8487 ((INSTANCE) == SPI4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8488 ((INSTANCE) == SPI5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8489 ((INSTANCE) == SPI6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8490
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8491 /*************************** SPI Extended Instances ***************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8492 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8493 ((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8494 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8495 ((INSTANCE) == SPI4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8496 ((INSTANCE) == SPI5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8497 ((INSTANCE) == SPI6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8498 ((INSTANCE) == I2S2ext) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8499 ((INSTANCE) == I2S3ext))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8500
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8501 /****************** TIM Instances : All supported instances *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8502 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8503 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8504 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8505 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8506 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8507 ((INSTANCE) == TIM6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8508 ((INSTANCE) == TIM7) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8509 ((INSTANCE) == TIM8) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8510 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8511 ((INSTANCE) == TIM10) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8512 ((INSTANCE) == TIM11) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8513 ((INSTANCE) == TIM12) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8514 ((INSTANCE) == TIM13) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8515 ((INSTANCE) == TIM14))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8516
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8517 /************* TIM Instances : at least 1 capture/compare channel *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8518 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8519 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8520 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8521 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8522 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8523 ((INSTANCE) == TIM8) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8524 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8525 ((INSTANCE) == TIM10) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8526 ((INSTANCE) == TIM11) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8527 ((INSTANCE) == TIM12) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8528 ((INSTANCE) == TIM13) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8529 ((INSTANCE) == TIM14))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8530
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8531 /************ TIM Instances : at least 2 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8532 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8533 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8534 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8535 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8536 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8537 ((INSTANCE) == TIM8) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8538 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8539 ((INSTANCE) == TIM12))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8540
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8541 /************ TIM Instances : at least 3 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8542 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8543 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8544 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8545 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8546 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8547 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8548
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8549 /************ TIM Instances : at least 4 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8550 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8551 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8552 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8553 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8554 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8555 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8556
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8557 /******************** TIM Instances : Advanced-control timers *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8558 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8559 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8560
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8561 /******************* TIM Instances : Timer input XOR function *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8562 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8563 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8564 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8565 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8566 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8567 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8568
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8569 /****************** TIM Instances : DMA requests generation (UDE) *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8570 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8571 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8572 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8573 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8574 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8575 ((INSTANCE) == TIM6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8576 ((INSTANCE) == TIM7) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8577 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8578
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8579 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8580 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8581 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8582 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8583 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8584 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8585 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8586
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8587 /************ TIM Instances : DMA requests generation (COMDE) *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8588 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8589 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8590 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8591 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8592 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8593 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8594
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8595 /******************** TIM Instances : DMA burst feature ***********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8596 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8597 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8598 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8599 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8600 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8601 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8602
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8603 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8604 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8605 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8606 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8607 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8608 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8609 ((INSTANCE) == TIM6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8610 ((INSTANCE) == TIM7) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8611 ((INSTANCE) == TIM8) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8612 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8613 ((INSTANCE) == TIM12))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8614
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8615 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8616 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8617 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8618 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8619 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8620 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8621 ((INSTANCE) == TIM8) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8622 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8623 ((INSTANCE) == TIM12))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8624
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8625 /********************** TIM Instances : 32 bit Counter ************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8626 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8627 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8628
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8629 /***************** TIM Instances : external trigger input availabe ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8630 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8631 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8632 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8633 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8634 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8635 ((INSTANCE) == TIM8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8636
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8637 /****************** TIM Instances : remapping capability **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8638 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8639 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8640 ((INSTANCE) == TIM11))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8641
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8642 /******************* TIM Instances : output(s) available **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8643 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8644 ((((INSTANCE) == TIM1) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8645 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8646 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8647 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8648 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8649 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8650 (((INSTANCE) == TIM2) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8651 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8652 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8653 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8654 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8655 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8656 (((INSTANCE) == TIM3) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8657 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8658 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8659 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8660 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8661 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8662 (((INSTANCE) == TIM4) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8663 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8664 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8665 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8666 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8667 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8668 (((INSTANCE) == TIM5) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8669 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8670 ((CHANNEL) == TIM_CHANNEL_2) || \
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heinrichsweikamp
parents:
diff changeset
8671 ((CHANNEL) == TIM_CHANNEL_3) || \
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heinrichsweikamp
parents:
diff changeset
8672 ((CHANNEL) == TIM_CHANNEL_4))) \
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heinrichsweikamp
parents:
diff changeset
8673 || \
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heinrichsweikamp
parents:
diff changeset
8674 (((INSTANCE) == TIM8) && \
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heinrichsweikamp
parents:
diff changeset
8675 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8676 ((CHANNEL) == TIM_CHANNEL_2) || \
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heinrichsweikamp
parents:
diff changeset
8677 ((CHANNEL) == TIM_CHANNEL_3) || \
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heinrichsweikamp
parents:
diff changeset
8678 ((CHANNEL) == TIM_CHANNEL_4))) \
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heinrichsweikamp
parents:
diff changeset
8679 || \
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heinrichsweikamp
parents:
diff changeset
8680 (((INSTANCE) == TIM9) && \
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heinrichsweikamp
parents:
diff changeset
8681 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8682 ((CHANNEL) == TIM_CHANNEL_2))) \
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heinrichsweikamp
parents:
diff changeset
8683 || \
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heinrichsweikamp
parents:
diff changeset
8684 (((INSTANCE) == TIM10) && \
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heinrichsweikamp
parents:
diff changeset
8685 (((CHANNEL) == TIM_CHANNEL_1))) \
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heinrichsweikamp
parents:
diff changeset
8686 || \
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heinrichsweikamp
parents:
diff changeset
8687 (((INSTANCE) == TIM11) && \
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heinrichsweikamp
parents:
diff changeset
8688 (((CHANNEL) == TIM_CHANNEL_1))) \
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heinrichsweikamp
parents:
diff changeset
8689 || \
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heinrichsweikamp
parents:
diff changeset
8690 (((INSTANCE) == TIM12) && \
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heinrichsweikamp
parents:
diff changeset
8691 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8692 ((CHANNEL) == TIM_CHANNEL_2))) \
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heinrichsweikamp
parents:
diff changeset
8693 || \
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heinrichsweikamp
parents:
diff changeset
8694 (((INSTANCE) == TIM13) && \
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heinrichsweikamp
parents:
diff changeset
8695 (((CHANNEL) == TIM_CHANNEL_1))) \
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heinrichsweikamp
parents:
diff changeset
8696 || \
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heinrichsweikamp
parents:
diff changeset
8697 (((INSTANCE) == TIM14) && \
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heinrichsweikamp
parents:
diff changeset
8698 (((CHANNEL) == TIM_CHANNEL_1))))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8699
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heinrichsweikamp
parents:
diff changeset
8700 /************ TIM Instances : complementary output(s) available ***************/
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heinrichsweikamp
parents:
diff changeset
8701 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
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heinrichsweikamp
parents:
diff changeset
8702 ((((INSTANCE) == TIM1) && \
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heinrichsweikamp
parents:
diff changeset
8703 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8704 ((CHANNEL) == TIM_CHANNEL_2) || \
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heinrichsweikamp
parents:
diff changeset
8705 ((CHANNEL) == TIM_CHANNEL_3))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8706 || \
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heinrichsweikamp
parents:
diff changeset
8707 (((INSTANCE) == TIM8) && \
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heinrichsweikamp
parents:
diff changeset
8708 (((CHANNEL) == TIM_CHANNEL_1) || \
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heinrichsweikamp
parents:
diff changeset
8709 ((CHANNEL) == TIM_CHANNEL_2) || \
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heinrichsweikamp
parents:
diff changeset
8710 ((CHANNEL) == TIM_CHANNEL_3))))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8711
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heinrichsweikamp
parents:
diff changeset
8712 /******************** USART Instances : Synchronous mode **********************/
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heinrichsweikamp
parents:
diff changeset
8713 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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heinrichsweikamp
parents:
diff changeset
8714 ((INSTANCE) == USART2) || \
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heinrichsweikamp
parents:
diff changeset
8715 ((INSTANCE) == USART3) || \
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heinrichsweikamp
parents:
diff changeset
8716 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8717
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heinrichsweikamp
parents:
diff changeset
8718 /******************** UART Instances : Asynchronous mode **********************/
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heinrichsweikamp
parents:
diff changeset
8719 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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heinrichsweikamp
parents:
diff changeset
8720 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8721 ((INSTANCE) == USART3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8722 ((INSTANCE) == UART4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8723 ((INSTANCE) == UART5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8724 ((INSTANCE) == USART6) || \
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heinrichsweikamp
parents:
diff changeset
8725 ((INSTANCE) == UART7) || \
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heinrichsweikamp
parents:
diff changeset
8726 ((INSTANCE) == UART8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8727
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heinrichsweikamp
parents:
diff changeset
8728 /****************** UART Instances : Hardware Flow control ********************/
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heinrichsweikamp
parents:
diff changeset
8729 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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heinrichsweikamp
parents:
diff changeset
8730 ((INSTANCE) == USART2) || \
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heinrichsweikamp
parents:
diff changeset
8731 ((INSTANCE) == USART3) || \
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heinrichsweikamp
parents:
diff changeset
8732 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8733
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heinrichsweikamp
parents:
diff changeset
8734 /********************* UART Instances : Smard card mode ***********************/
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heinrichsweikamp
parents:
diff changeset
8735 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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heinrichsweikamp
parents:
diff changeset
8736 ((INSTANCE) == USART2) || \
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heinrichsweikamp
parents:
diff changeset
8737 ((INSTANCE) == USART3) || \
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heinrichsweikamp
parents:
diff changeset
8738 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8739
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heinrichsweikamp
parents:
diff changeset
8740 /*********************** UART Instances : IRDA mode ***************************/
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heinrichsweikamp
parents:
diff changeset
8741 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
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heinrichsweikamp
parents:
diff changeset
8742 ((INSTANCE) == USART2) || \
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heinrichsweikamp
parents:
diff changeset
8743 ((INSTANCE) == USART3) || \
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heinrichsweikamp
parents:
diff changeset
8744 ((INSTANCE) == UART4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8745 ((INSTANCE) == UART5) || \
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heinrichsweikamp
parents:
diff changeset
8746 ((INSTANCE) == USART6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8747 ((INSTANCE) == UART7) || \
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heinrichsweikamp
parents:
diff changeset
8748 ((INSTANCE) == UART8))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8749
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
8750 /****************************** IWDG Instances ********************************/
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heinrichsweikamp
parents:
diff changeset
8751 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
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heinrichsweikamp
parents:
diff changeset
8752
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heinrichsweikamp
parents:
diff changeset
8753 /****************************** WWDG Instances ********************************/
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heinrichsweikamp
parents:
diff changeset
8754 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
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heinrichsweikamp
parents:
diff changeset
8755
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heinrichsweikamp
parents:
diff changeset
8756 /****************************** SDIO Instances ********************************/
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heinrichsweikamp
parents:
diff changeset
8757 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
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heinrichsweikamp
parents:
diff changeset
8758
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heinrichsweikamp
parents:
diff changeset
8759 /****************************** USB Exported Constants ************************/
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parents:
diff changeset
8760 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
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parents:
diff changeset
8761 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
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heinrichsweikamp
parents:
diff changeset
8762 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
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parents:
diff changeset
8763 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
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parents:
diff changeset
8764
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parents:
diff changeset
8765 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
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heinrichsweikamp
parents:
diff changeset
8766 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
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heinrichsweikamp
parents:
diff changeset
8767 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
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heinrichsweikamp
parents:
diff changeset
8768 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
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parents:
diff changeset
8769
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heinrichsweikamp
parents:
diff changeset
8770 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
8771 /* For a painless codes migration between the STM32F4xx device product */
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parents:
diff changeset
8772 /* lines, the aliases defined below are put in place to overcome the */
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parents:
diff changeset
8773 /* differences in the interrupt handlers and IRQn definitions. */
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parents:
diff changeset
8774 /* No need to update developed interrupt code when moving across */
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parents:
diff changeset
8775 /* product lines within the same STM32F4 Family */
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heinrichsweikamp
parents:
diff changeset
8776 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
8777
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parents:
diff changeset
8778 /* Aliases for __IRQn */
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parents:
diff changeset
8779 #define FSMC_IRQn FMC_IRQn
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parents:
diff changeset
8780
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heinrichsweikamp
parents:
diff changeset
8781 /* Aliases for __IRQHandler */
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heinrichsweikamp
parents:
diff changeset
8782 #define FSMC_IRQHandler FMC_IRQHandler
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heinrichsweikamp
parents:
diff changeset
8783
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heinrichsweikamp
parents:
diff changeset
8784 /**
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heinrichsweikamp
parents:
diff changeset
8785 * @}
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heinrichsweikamp
parents:
diff changeset
8786 */
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heinrichsweikamp
parents:
diff changeset
8787
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heinrichsweikamp
parents:
diff changeset
8788 /**
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heinrichsweikamp
parents:
diff changeset
8789 * @}
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heinrichsweikamp
parents:
diff changeset
8790 */
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heinrichsweikamp
parents:
diff changeset
8791
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heinrichsweikamp
parents:
diff changeset
8792 /**
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heinrichsweikamp
parents:
diff changeset
8793 * @}
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heinrichsweikamp
parents:
diff changeset
8794 */
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heinrichsweikamp
parents:
diff changeset
8795
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heinrichsweikamp
parents:
diff changeset
8796 #ifdef __cplusplus
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heinrichsweikamp
parents:
diff changeset
8797 }
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heinrichsweikamp
parents:
diff changeset
8798 #endif /* __cplusplus */
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parents:
diff changeset
8799
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parents:
diff changeset
8800 #endif /* __stm32f427xx_H */
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parents:
diff changeset
8801
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heinrichsweikamp
parents:
diff changeset
8802
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heinrichsweikamp
parents:
diff changeset
8803
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heinrichsweikamp
parents:
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8804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/