annotate Discovery/Inc/ostc_discovery.h @ 471:73da921869d9 fix-bat-2

bugfix: implement battery charge percentage in dive header This commit is (much) less trivial than the related 919e5cb51c92. First, rename the CCRmode attribute (corresponding to byte Ox59) of the SLogbookHeaderOSTC3. This byte (according to the hwOS interface document) does not contain any CCR related value, but it contains "battery information". Already since 2017, this byte is used from libdivecomputer to interface the charge percentage. So, its renamed from CCRmode to batteryCharge, to reflect its true purpose. Now, simply add a batteryCharge attribute to the SLogbookHeader (and see below why that is possible, without breaking things). The remaining changes are trivial to implement battery charge percentage in dive header. Caveat: do not get confused by the exact role of the individual logbook header types. SLogbookHeaderOSTC3 is the formal type of the logbook format that the OSTC4 produces. This format is supposed to identical to the format, as is used in hwOS for the series of small OSTCs. Only some values of attributes are different. For example, the OSTC4 supports VPM, so byte 0x79 (deco model used for this dive) also has a value for VPM. But the SLogbookHeader type, despite its name and structure, is *not* a true logbook header, as it includes attributes that are not available in the SLogbookHeaderOSTC3 formal header type. Signed-off-by: Jan Mulder <jan@jlmulder.nl>
author Jan Mulder <jlmulder@xs4all.nl>
date Wed, 22 Apr 2020 13:08:57 +0200
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1 ///////////////////////////////////////////////////////////////////////////////
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2 /// -*- coding: UTF-8 -*-
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3 ///
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4 /// \file Discovery/Inc/ostc_discovery.h
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5 /// \brief Hardware specific configuration
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6 /// \author heinrichs weikamp gmbh
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7 /// \date 05-Dec-2014
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8 ///
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9 /// $Id$
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10 ///////////////////////////////////////////////////////////////////////////////
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11 /// \par Copyright (c) 2014-2018 Heinrichs Weikamp gmbh
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12 ///
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13 /// This program is free software: you can redistribute it and/or modify
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14 /// it under the terms of the GNU General Public License as published by
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15 /// the Free Software Foundation, either version 3 of the License, or
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16 /// (at your option) any later version.
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17 ///
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18 /// This program is distributed in the hope that it will be useful,
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19 /// but WITHOUT ANY WARRANTY; without even the implied warranty of
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20 /// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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21 /// GNU General Public License for more details.
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22 ///
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23 /// You should have received a copy of the GNU General Public License
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24 /// along with this program. If not, see <http://www.gnu.org/licenses/>.
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25 //////////////////////////////////////////////////////////////////////////////
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26
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27 #ifndef OSTC_DISCOVERY_H
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28 #define OSTC_DISCOVERY_H
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29
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30 #define DISPLAY_RESETB_PIN GPIO_PIN_6
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31 #define DISPLAY_RESETB_GPIO_PORT GPIOF
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32 #define DISPLAY_RESETB_GPIO_ENABLE()__GPIOF_CLK_ENABLE()
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33
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34 #define DISPLAY_CSB_PIN GPIO_PIN_8
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35 #define DISPLAY_CSB_GPIO_PORT GPIOC
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36 #define DISPLAY_CSB_GPIO_ENABLE() __GPIOC_CLK_ENABLE()
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37
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38 #define VSYNC_IRQ_PIN GPIO_PIN_4
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39 #define VSYNC_IRQ_GPIO_PORT GPIOD
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40 #define VSYNC_IRQ_GPIO_ENABLE() __GPIOD_CLK_ENABLE()
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41 #define VSYNC_IRQ_EXTI_IRQn EXTI4_IRQn
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42
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43 #define BUTTON_ENTER_PIN GPIO_PIN_0
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44 #define BUTTON_ENTER_GPIO_PORT GPIOA
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45 #define BUTTON_ENTER_GPIO_ENABLE() __GPIOA_CLK_ENABLE()
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46 #define BUTTON_ENTER_EXTI_IRQn EXTI0_IRQn
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47
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48 #define BUTTON_DOWN_PIN GPIO_PIN_1
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49 #define BUTTON_DOWN_GPIO_PORT GPIOA
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50 #define BUTTON_DOWN_GPIO_ENABLE() __GPIOA_CLK_ENABLE()
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51 #define BUTTON_DOWN_EXTI_IRQn EXTI1_IRQn
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52
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53 #define BUTTON_NEXT_PIN GPIO_PIN_2
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54 #define BUTTON_NEXT_GPIO_PORT GPIOA
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55 #define BUTTON_NEXT_GPIO_ENABLE() __GPIOA_CLK_ENABLE()
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56 #define BUTTON_NEXT_EXTI_IRQn EXTI2_IRQn
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57
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58 #define BUTTON_BACK_PIN GPIO_PIN_3
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59 #define BUTTON_BACK_GPIO_PORT GPIOC
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60 #define BUTTON_BACK_GPIO_ENABLE() __GPIOC_CLK_ENABLE()
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61 #define BUTTON_BACK_EXTI_IRQn EXTI3_IRQn
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62
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63 #define EXTFLASH_CSB_PIN GPIO_PIN_1
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64 #define EXTFLASH_CSB_GPIO_PORT GPIOC
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65 #define EXTFLASH_CSB_GPIO_ENABLE() __GPIOC_CLK_ENABLE()
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66
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67 #define OSCILLOSCOPE_PIN GPIO_PIN_14
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68 #define OSCILLOSCOPE_GPIO_PORT GPIOG
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69 #define OSCILLOSCOPE_GPIO_ENABLE() __GPIOG_CLK_ENABLE()
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70
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71 #define OSCILLOSCOPE2_PIN GPIO_PIN_13
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72 #define OSCILLOSCOPE2_GPIO_PORT GPIOG
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73 #define OSCILLOSCOPE2_GPIO_ENABLE() __GPIOG_CLK_ENABLE()
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74
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75 #define USARTx USART1
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76 #define USARTx_CLK_ENABLE() __USART1_CLK_ENABLE();
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77 #define USARTx_FORCE_RESET() __USART1_FORCE_RESET()
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78 #define USARTx_RELEASE_RESET() __USART1_RELEASE_RESET()
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79
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80 #define USARTx_RX_AF GPIO_AF7_USART1
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81 #define USARTx_RX_PIN GPIO_PIN_10
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82 #define USARTx_RX_GPIO_PORT GPIOA
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83 #define USARTx_RX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
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84
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85 #define USARTx_TX_AF GPIO_AF7_USART1
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86 #define USARTx_TX_PIN GPIO_PIN_9
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87 #define USARTx_TX_GPIO_PORT GPIOA
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88 #define USARTx_TX_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
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89 #define USARTx_IRQn USART1_IRQn
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90 #define USARTx_IRQHandler USART1_IRQHandler
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91
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92 #define TIMx TIM3
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93 #define TIMx_CLK_ENABLE __TIM3_CLK_ENABLE
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94 #define TIMx_IRQn TIM3_IRQn
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95 #define TIMx_IRQHandler TIM3_IRQHandler
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96
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97 #define SMALLCPU_CSB_PIN GPIO_PIN_15
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98 #define SMALLCPU_CSB_GPIO_PORT GPIOA
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99 #define SMALLCPU_CSB_GPIO_ENABLE() __GPIOA_CLK_ENABLE()
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100
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101 #endif // OSTC_DISCOVERY_H