Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fsmc.h @ 471:73da921869d9 fix-bat-2
bugfix: implement battery charge percentage in dive header
This commit is (much) less trivial than the related 919e5cb51c92.
First, rename the CCRmode attribute (corresponding to byte Ox59) of
the SLogbookHeaderOSTC3. This byte (according to the hwOS interface
document) does not contain any CCR related value, but it contains
"battery information". Already since 2017, this byte is used from
libdivecomputer to interface the charge percentage. So, its
renamed from CCRmode to batteryCharge, to reflect its true purpose.
Now, simply add a batteryCharge attribute to the SLogbookHeader
(and see below why that is possible, without breaking things).
The remaining changes are trivial to implement battery charge
percentage in dive header.
Caveat: do not get confused by the exact role of the individual
logbook header types. SLogbookHeaderOSTC3 is the formal type of
the logbook format that the OSTC4 produces. This format is
supposed to identical to the format, as is used in hwOS for the
series of small OSTCs. Only some values of attributes are different.
For example, the OSTC4 supports VPM, so byte 0x79 (deco model used
for this dive) also has a value for VPM. But the SLogbookHeader
type, despite its name and structure, is *not* a true logbook
header, as it includes attributes that are not available in the
SLogbookHeaderOSTC3 formal header type.
Signed-off-by: Jan Mulder <jan@jlmulder.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
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date | Wed, 22 Apr 2020 13:08:57 +0200 (2020-04-22) |
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rev | line source |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_ll_fsmc.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of FSMC HAL module. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 |
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36 /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 #ifndef __STM32F4xx_LL_FSMC_H |
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38 #define __STM32F4xx_LL_FSMC_H |
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39 |
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40 #ifdef __cplusplus |
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41 extern "C" { |
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42 #endif |
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43 |
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44 /* Includes ------------------------------------------------------------------*/ |
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45 #include "stm32f4xx_hal_def.h" |
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46 |
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47 /** @addtogroup STM32F4xx_HAL_Driver |
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48 * @{ |
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49 */ |
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50 |
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51 /** @addtogroup FSMC_LL |
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52 * @{ |
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53 */ |
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54 |
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55 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ |
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56 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
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57 /* Private types -------------------------------------------------------------*/ |
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58 /** @defgroup FSMC_LL_Private_Types FSMC Private Types |
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59 * @{ |
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60 */ |
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61 |
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62 /** |
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63 * @brief FSMC NORSRAM Configuration Structure definition |
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64 */ |
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65 typedef struct |
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66 { |
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67 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
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68 This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
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69 |
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70 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
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71 multiplexed on the data bus or not. |
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72 This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
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73 |
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74 uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
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75 the corresponding memory device. |
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76 This parameter can be a value of @ref FSMC_Memory_Type */ |
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77 |
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78 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
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79 This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
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80 |
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81 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
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82 valid only with synchronous burst Flash memories. |
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83 This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
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84 |
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85 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
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86 the Flash memory in burst mode. |
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87 This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
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88 |
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89 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
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90 memory, valid only when accessing Flash memories in burst mode. |
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91 This parameter can be a value of @ref FSMC_Wrap_Mode |
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92 This mode is available only for the STM32F405/407/4015/417xx devices */ |
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93 |
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94 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
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95 clock cycle before the wait state or during the wait state, |
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96 valid only when accessing memories in burst mode. |
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97 This parameter can be a value of @ref FSMC_Wait_Timing */ |
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98 |
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99 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
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100 This parameter can be a value of @ref FSMC_Write_Operation */ |
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101 |
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102 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
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103 signal, valid for Flash memory access in burst mode. |
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104 This parameter can be a value of @ref FSMC_Wait_Signal */ |
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105 |
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106 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
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107 This parameter can be a value of @ref FSMC_Extended_Mode */ |
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108 |
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109 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
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110 valid only with asynchronous Flash memories. |
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111 This parameter can be a value of @ref FSMC_AsynchronousWait */ |
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112 |
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113 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
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114 This parameter can be a value of @ref FSMC_Write_Burst */ |
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115 |
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116 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. |
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117 This parameter is only enabled through the FMC_BCR1 register, and don't care |
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118 through FMC_BCR2..4 registers. |
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119 This parameter can be a value of @ref FMC_Continous_Clock |
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120 This mode is available only for the STM32F412Vx/Zx/Rx devices */ |
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121 |
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122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. |
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123 This parameter is only enabled through the FMC_BCR1 register, and don't care |
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124 through FMC_BCR2..4 registers. |
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125 This parameter can be a value of @ref FMC_Write_FIFO |
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126 This mode is available only for the STM32F412Vx/Vx devices */ |
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127 |
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128 uint32_t PageSize; /*!< Specifies the memory page size. |
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129 This parameter can be a value of @ref FMC_Page_Size */ |
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130 }FSMC_NORSRAM_InitTypeDef; |
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131 |
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132 /** |
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133 * @brief FSMC NORSRAM Timing parameters structure definition |
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134 */ |
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135 typedef struct |
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136 { |
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137 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
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138 the duration of the address setup time. |
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139 This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
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140 @note This parameter is not used with synchronous NOR Flash memories. */ |
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141 |
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142 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
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143 the duration of the address hold time. |
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144 This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
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145 @note This parameter is not used with synchronous NOR Flash memories. */ |
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146 |
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147 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
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148 the duration of the data setup time. |
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149 This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
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150 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
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151 NOR Flash memories. */ |
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152 |
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153 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
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154 the duration of the bus turnaround. |
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155 This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
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156 @note This parameter is only used for multiplexed NOR Flash memories. */ |
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157 |
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158 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
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159 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
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160 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
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161 accesses. */ |
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162 |
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163 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
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164 to the memory before getting the first data. |
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165 The parameter value depends on the memory type as shown below: |
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166 - It must be set to 0 in case of a CRAM |
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167 - It is don't care in asynchronous NOR, SRAM or ROM accesses |
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168 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
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169 with synchronous burst mode enable */ |
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170 |
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171 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
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172 This parameter can be a value of @ref FSMC_Access_Mode */ |
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173 |
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174 }FSMC_NORSRAM_TimingTypeDef; |
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175 |
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176 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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177 /** |
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178 * @brief FSMC NAND Configuration Structure definition |
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179 */ |
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180 typedef struct |
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181 { |
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182 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
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183 This parameter can be a value of @ref FSMC_NAND_Bank */ |
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184 |
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185 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
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186 This parameter can be any value of @ref FSMC_Wait_feature */ |
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187 |
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188 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
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189 This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
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190 |
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191 uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
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192 This parameter can be any value of @ref FSMC_ECC */ |
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193 |
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194 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
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195 This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
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196 |
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197 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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198 delay between CLE low and RE low. |
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199 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
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200 |
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201 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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202 delay between ALE low and RE low. |
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203 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
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204 |
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205 }FSMC_NAND_InitTypeDef; |
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206 |
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207 /** |
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208 * @brief FSMC NAND/PCCARD Timing parameters structure definition |
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209 */ |
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210 typedef struct |
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211 { |
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212 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
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213 the command assertion for NAND-Flash read or write access |
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214 to common/Attribute or I/O memory space (depending on |
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215 the memory space timing to be configured). |
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216 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
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217 |
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218 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
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219 command for NAND-Flash read or write access to |
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220 common/Attribute or I/O memory space (depending on the |
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221 memory space timing to be configured). |
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222 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
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223 |
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224 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
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225 (and data for write access) after the command de-assertion |
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226 for NAND-Flash read or write access to common/Attribute |
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227 or I/O memory space (depending on the memory space timing |
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228 to be configured). |
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229 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
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230 |
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231 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
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232 data bus is kept in HiZ after the start of a NAND-Flash |
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233 write access to common/Attribute or I/O memory space (depending |
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234 on the memory space timing to be configured). |
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235 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
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236 |
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237 }FSMC_NAND_PCC_TimingTypeDef; |
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238 |
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239 /** |
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240 * @brief FSMC NAND Configuration Structure definition |
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241 */ |
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242 typedef struct |
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243 { |
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244 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
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245 This parameter can be any value of @ref FSMC_Wait_feature */ |
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246 |
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247 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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248 delay between CLE low and RE low. |
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249 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
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250 |
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251 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
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252 delay between ALE low and RE low. |
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253 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
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254 |
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255 }FSMC_PCCARD_InitTypeDef; |
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256 /** |
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257 * @} |
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258 */ |
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259 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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260 |
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261 /* Private constants ---------------------------------------------------------*/ |
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262 /** @defgroup FSMC_LL_Private_Constants FSMC Private Constants |
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263 * @{ |
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264 */ |
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265 |
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266 /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
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267 * @{ |
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268 */ |
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269 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
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270 * @{ |
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271 */ |
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272 #define FSMC_NORSRAM_BANK1 0x00000000U |
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273 #define FSMC_NORSRAM_BANK2 0x00000002U |
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274 #define FSMC_NORSRAM_BANK3 0x00000004U |
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275 #define FSMC_NORSRAM_BANK4 0x00000006U |
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276 /** |
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277 * @} |
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278 */ |
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279 |
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280 /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
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281 * @{ |
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282 */ |
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283 #define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U |
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284 #define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U |
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285 /** |
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286 * @} |
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287 */ |
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288 |
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289 /** @defgroup FSMC_Memory_Type FSMC Memory Type |
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290 * @{ |
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291 */ |
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292 #define FSMC_MEMORY_TYPE_SRAM 0x00000000U |
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293 #define FSMC_MEMORY_TYPE_PSRAM 0x00000004U |
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294 #define FSMC_MEMORY_TYPE_NOR 0x00000008U |
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295 /** |
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296 * @} |
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297 */ |
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298 |
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299 /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
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300 * @{ |
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301 */ |
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302 #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U |
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303 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U |
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304 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U |
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305 /** |
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306 * @} |
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307 */ |
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308 |
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309 /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
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310 * @{ |
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311 */ |
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312 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U |
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313 #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U |
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314 /** |
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315 * @} |
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316 */ |
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317 |
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318 /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
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319 * @{ |
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320 */ |
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321 #define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U |
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322 #define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U |
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323 /** |
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324 * @} |
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325 */ |
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326 |
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327 /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
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328 * @{ |
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329 */ |
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330 #define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U |
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331 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U |
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332 /** |
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333 * @} |
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334 */ |
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335 |
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336 /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
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337 * @note These values are available only for the STM32F405/415/407/417xx devices. |
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338 * @{ |
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339 */ |
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340 #define FSMC_WRAP_MODE_DISABLE 0x00000000U |
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341 #define FSMC_WRAP_MODE_ENABLE 0x00000400U |
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342 /** |
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343 * @} |
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344 */ |
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345 |
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346 /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
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347 * @{ |
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348 */ |
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349 #define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U |
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350 #define FSMC_WAIT_TIMING_DURING_WS 0x00000800U |
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351 /** |
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352 * @} |
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353 */ |
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354 |
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355 /** @defgroup FSMC_Write_Operation FSMC Write Operation |
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356 * @{ |
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357 */ |
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358 #define FSMC_WRITE_OPERATION_DISABLE 0x00000000U |
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359 #define FSMC_WRITE_OPERATION_ENABLE 0x00001000U |
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360 /** |
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361 * @} |
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362 */ |
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363 |
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364 /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
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365 * @{ |
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366 */ |
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367 #define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U |
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368 #define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U |
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369 /** |
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370 * @} |
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371 */ |
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372 |
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373 /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
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374 * @{ |
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375 */ |
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376 #define FSMC_EXTENDED_MODE_DISABLE 0x00000000U |
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377 #define FSMC_EXTENDED_MODE_ENABLE 0x00004000U |
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378 /** |
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379 * @} |
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380 */ |
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381 |
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382 /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
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383 * @{ |
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384 */ |
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385 #define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U |
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386 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U |
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387 /** |
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388 * @} |
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389 */ |
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390 |
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391 /** @defgroup FSMC_Page_Size FSMC Page Size |
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392 * @{ |
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393 */ |
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394 #define FSMC_PAGE_SIZE_NONE 0x00000000U |
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395 #define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) |
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396 #define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) |
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397 #define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) |
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398 #define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) |
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399 /** |
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400 * @} |
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401 */ |
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402 |
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403 /** @defgroup FSMC_Write_FIFO FSMC Write FIFO |
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404 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. |
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405 * @{ |
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406 */ |
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407 #define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) |
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408 #define FSMC_WRITE_FIFO_ENABLE 0x00000000U |
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409 /** |
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410 * @} |
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411 */ |
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412 |
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413 /** @defgroup FSMC_Write_Burst FSMC Write Burst |
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414 * @{ |
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415 */ |
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416 #define FSMC_WRITE_BURST_DISABLE 0x00000000U |
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417 #define FSMC_WRITE_BURST_ENABLE 0x00080000U |
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418 /** |
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419 * @} |
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420 */ |
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421 |
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422 /** @defgroup FSMC_Continous_Clock FSMC Continous Clock |
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423 * @note These values are available only for the STM32F412Vx/Zx/Rx devices. |
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424 * @{ |
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425 */ |
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426 #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U |
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427 #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U |
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428 /** |
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429 * @} |
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430 */ |
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431 |
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432 /** @defgroup FSMC_Access_Mode FSMC Access Mode |
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433 * @{ |
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434 */ |
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435 #define FSMC_ACCESS_MODE_A 0x00000000U |
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436 #define FSMC_ACCESS_MODE_B 0x10000000U |
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437 #define FSMC_ACCESS_MODE_C 0x20000000U |
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438 #define FSMC_ACCESS_MODE_D 0x30000000U |
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439 /** |
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440 * @} |
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441 */ |
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442 /** |
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443 * @} |
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444 */ |
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445 |
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446 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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447 /** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller |
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448 * @{ |
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449 */ |
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450 /** @defgroup FSMC_NAND_Bank FSMC NAND Bank |
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451 * @{ |
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452 */ |
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453 #define FSMC_NAND_BANK2 0x00000010U |
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454 #define FSMC_NAND_BANK3 0x00000100U |
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455 /** |
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456 * @} |
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457 */ |
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458 |
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459 /** @defgroup FSMC_Wait_feature FSMC Wait feature |
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460 * @{ |
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461 */ |
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462 #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U |
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463 #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U |
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464 /** |
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465 * @} |
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466 */ |
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467 |
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468 /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type |
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469 * @{ |
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470 */ |
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471 #define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U |
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472 #define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U |
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473 /** |
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474 * @} |
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475 */ |
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476 |
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477 /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width |
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478 * @{ |
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479 */ |
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480 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U |
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481 #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U |
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482 /** |
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483 * @} |
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484 */ |
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485 |
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486 /** @defgroup FSMC_ECC FSMC ECC |
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487 * @{ |
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488 */ |
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489 #define FSMC_NAND_ECC_DISABLE 0x00000000U |
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490 #define FSMC_NAND_ECC_ENABLE 0x00000040U |
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491 /** |
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492 * @} |
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493 */ |
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494 |
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495 /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size |
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496 * @{ |
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497 */ |
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498 #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U |
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499 #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U |
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500 #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U |
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501 #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U |
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502 #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U |
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503 #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U |
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504 /** |
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505 * @} |
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506 */ |
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507 /** |
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508 * @} |
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509 */ |
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510 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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511 |
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512 /** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition |
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513 * @{ |
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514 */ |
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515 #define FSMC_IT_RISING_EDGE 0x00000008U |
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516 #define FSMC_IT_LEVEL 0x00000010U |
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517 #define FSMC_IT_FALLING_EDGE 0x00000020U |
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518 #define FSMC_IT_REFRESH_ERROR 0x00004000U |
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519 /** |
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520 * @} |
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521 */ |
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522 |
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523 /** @defgroup FSMC_LL_Flag_definition FSMC Flag definition |
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524 * @{ |
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525 */ |
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526 #define FSMC_FLAG_RISING_EDGE 0x00000001U |
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527 #define FSMC_FLAG_LEVEL 0x00000002U |
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528 #define FSMC_FLAG_FALLING_EDGE 0x00000004U |
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529 #define FSMC_FLAG_FEMPT 0x00000040U |
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530 /** |
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531 * @} |
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532 */ |
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533 |
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534 /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition |
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535 * @{ |
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536 */ |
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537 #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
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538 #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
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539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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540 #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
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541 #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
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542 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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543 |
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544 #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
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545 #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
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546 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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547 #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
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548 #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
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549 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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550 |
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551 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 |
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552 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 |
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553 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32 |
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554 |
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555 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
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556 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
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557 #define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef |
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558 #define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef |
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559 |
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560 #define FMC_NORSRAM_Init FSMC_NORSRAM_Init |
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561 #define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init |
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562 #define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init |
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563 #define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit |
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564 #define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable |
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565 #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable |
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566 |
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567 #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE |
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568 #define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE |
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569 |
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570 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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571 #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef |
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572 #define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef |
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573 #define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef |
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574 |
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575 #define FMC_NAND_Init FSMC_NAND_Init |
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576 #define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init |
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577 #define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init |
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578 #define FMC_NAND_DeInit FSMC_NAND_DeInit |
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579 #define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable |
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580 #define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable |
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581 #define FMC_NAND_GetECC FSMC_NAND_GetECC |
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582 #define FMC_PCCARD_Init FSMC_PCCARD_Init |
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583 #define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init |
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584 #define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init |
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585 #define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init |
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586 #define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit |
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587 |
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588 #define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE |
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589 #define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE |
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590 #define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE |
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591 #define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE |
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592 #define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT |
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593 #define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT |
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594 #define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG |
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595 #define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG |
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596 #define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT |
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597 #define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT |
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598 #define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG |
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599 #define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG |
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600 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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601 |
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602 #define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef |
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603 #define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef |
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604 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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605 #define FMC_NAND_TypeDef FSMC_NAND_TypeDef |
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606 #define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef |
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607 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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608 |
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609 #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE |
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610 #define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE |
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611 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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612 #define FMC_NAND_DEVICE FSMC_NAND_DEVICE |
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613 #define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE |
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614 |
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615 #define FMC_NAND_BANK2 FSMC_NAND_BANK2 |
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616 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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617 |
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618 #define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 |
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619 #define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 |
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620 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 |
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621 |
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622 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE |
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623 #define FMC_IT_LEVEL FSMC_IT_LEVEL |
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624 #define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE |
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625 #define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR |
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626 |
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627 #define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE |
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628 #define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL |
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629 #define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE |
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630 #define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT |
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631 /** |
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632 * @} |
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633 */ |
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634 |
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635 /** |
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636 * @} |
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637 */ |
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638 |
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639 /* Private macro -------------------------------------------------------------*/ |
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640 /** @defgroup FSMC_LL_Private_Macros FSMC Private Macros |
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641 * @{ |
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642 */ |
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643 |
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644 /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros |
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645 * @brief macros to handle NOR device enable/disable and read/write operations |
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646 * @{ |
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647 */ |
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648 /** |
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649 * @brief Enable the NORSRAM device access. |
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650 * @param __INSTANCE__ FSMC_NORSRAM Instance |
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651 * @param __BANK__ FSMC_NORSRAM Bank |
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652 * @retval none |
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653 */ |
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654 #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) |
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655 |
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656 /** |
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657 * @brief Disable the NORSRAM device access. |
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658 * @param __INSTANCE__ FSMC_NORSRAM Instance |
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659 * @param __BANK__ FSMC_NORSRAM Bank |
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660 * @retval none |
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661 */ |
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662 #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) |
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663 /** |
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664 * @} |
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665 */ |
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666 |
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667 /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros |
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668 * @brief macros to handle NAND device enable/disable |
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669 * @{ |
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670 */ |
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671 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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672 /** |
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673 * @brief Enable the NAND device access. |
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674 * @param __INSTANCE__ FSMC_NAND Instance |
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675 * @param __BANK__ FSMC_NAND Bank |
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676 * @retval none |
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677 */ |
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678 #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ |
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679 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) |
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680 |
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681 /** |
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682 * @brief Disable the NAND device access. |
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|
683 * @param __INSTANCE__ FSMC_NAND Instance |
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684 * @param __BANK__ FSMC_NAND Bank |
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685 * @retval none |
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686 */ |
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687 #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ |
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688 ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) |
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|
689 /** |
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690 * @} |
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|
691 */ |
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|
692 |
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|
693 /** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros |
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Ideenmodellierer
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|
694 * @brief macros to handle SRAM read/write operations |
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Added current STM32 standandard libraries in version independend folder structure
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|
695 * @{ |
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696 */ |
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|
697 /** |
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|
698 * @brief Enable the PCCARD device access. |
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|
699 * @param __INSTANCE__ FSMC_PCCARD Instance |
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700 * @retval none |
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Added current STM32 standandard libraries in version independend folder structure
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|
701 */ |
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|
702 #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) |
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|
703 |
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|
704 /** |
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Added current STM32 standandard libraries in version independend folder structure
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|
705 * @brief Disable the PCCARD device access. |
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|
706 * @param __INSTANCE__ FSMC_PCCARD Instance |
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|
707 * @retval none |
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Added current STM32 standandard libraries in version independend folder structure
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|
708 */ |
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|
709 #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) |
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|
710 /** |
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|
711 * @} |
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Added current STM32 standandard libraries in version independend folder structure
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|
712 */ |
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|
713 |
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Ideenmodellierer
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|
714 /** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
715 * @brief macros to handle FSMC flags and interrupts |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
716 * @{ |
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Added current STM32 standandard libraries in version independend folder structure
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|
717 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
718 /** |
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Added current STM32 standandard libraries in version independend folder structure
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|
719 * @brief Enable the NAND device interrupt. |
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Added current STM32 standandard libraries in version independend folder structure
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|
720 * @param __INSTANCE__ FSMC_NAND Instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
721 * @param __BANK__ FSMC_NAND Bank |
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Added current STM32 standandard libraries in version independend folder structure
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|
722 * @param __INTERRUPT__ FSMC_NAND interrupt |
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Added current STM32 standandard libraries in version independend folder structure
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|
723 * This parameter can be any combination of the following values: |
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Added current STM32 standandard libraries in version independend folder structure
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|
724 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
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|
725 * @arg FSMC_IT_LEVEL: Interrupt level. |
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Added current STM32 standandard libraries in version independend folder structure
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|
726 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
c78bcbd5deda
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|
727 * @retval None |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
728 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
729 #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
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Added current STM32 standandard libraries in version independend folder structure
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730 ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
731 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
732 /** |
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Added current STM32 standandard libraries in version independend folder structure
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|
733 * @brief Disable the NAND device interrupt. |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
734 * @param __INSTANCE__ FSMC_NAND Instance |
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Added current STM32 standandard libraries in version independend folder structure
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735 * @param __BANK__ FSMC_NAND Bank |
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Added current STM32 standandard libraries in version independend folder structure
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736 * @param __INTERRUPT__ FSMC_NAND interrupt |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
737 * This parameter can be any combination of the following values: |
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Added current STM32 standandard libraries in version independend folder structure
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|
738 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
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|
739 * @arg FSMC_IT_LEVEL: Interrupt level. |
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|
740 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
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|
741 * @retval None |
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|
742 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
743 #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
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Added current STM32 standandard libraries in version independend folder structure
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744 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
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Added current STM32 standandard libraries in version independend folder structure
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|
745 |
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Added current STM32 standandard libraries in version independend folder structure
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|
746 /** |
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|
747 * @brief Get flag status of the NAND device. |
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748 * @param __INSTANCE__ FSMC_NAND Instance |
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|
749 * @param __BANK__ FSMC_NAND Bank |
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Added current STM32 standandard libraries in version independend folder structure
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750 * @param __FLAG__ FSMC_NAND flag |
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Added current STM32 standandard libraries in version independend folder structure
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|
751 * This parameter can be any combination of the following values: |
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Added current STM32 standandard libraries in version independend folder structure
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|
752 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
753 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
754 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
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Added current STM32 standandard libraries in version independend folder structure
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|
755 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
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Added current STM32 standandard libraries in version independend folder structure
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|
756 * @retval The state of FLAG (SET or RESET). |
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Added current STM32 standandard libraries in version independend folder structure
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|
757 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
758 #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
759 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
760 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
761 /** |
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|
762 * @brief Clear flag status of the NAND device. |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
763 * @param __INSTANCE__ FSMC_NAND Instance |
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Added current STM32 standandard libraries in version independend folder structure
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|
764 * @param __BANK__ FSMC_NAND Bank |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
765 * @param __FLAG__ FSMC_NAND flag |
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Added current STM32 standandard libraries in version independend folder structure
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|
766 * This parameter can be any combination of the following values: |
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767 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
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768 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
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769 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
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770 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
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771 * @retval None |
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|
772 */ |
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|
773 #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
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|
774 ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
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|
775 |
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|
776 /** |
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|
777 * @brief Enable the PCCARD device interrupt. |
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|
778 * @param __INSTANCE__ FSMC_PCCARD Instance |
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|
779 * @param __INTERRUPT__ FSMC_PCCARD interrupt |
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|
780 * This parameter can be any combination of the following values: |
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781 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
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782 * @arg FSMC_IT_LEVEL: Interrupt level. |
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783 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
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|
784 * @retval None |
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|
785 */ |
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|
786 #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
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|
787 |
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|
788 /** |
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|
789 * @brief Disable the PCCARD device interrupt. |
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|
790 * @param __INSTANCE__ FSMC_PCCARD Instance |
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Added current STM32 standandard libraries in version independend folder structure
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791 * @param __INTERRUPT__ FSMC_PCCARD interrupt |
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|
792 * This parameter can be any combination of the following values: |
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|
793 * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
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|
794 * @arg FSMC_IT_LEVEL: Interrupt level. |
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|
795 * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
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|
796 * @retval None |
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|
797 */ |
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|
798 #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
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|
799 |
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|
800 /** |
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|
801 * @brief Get flag status of the PCCARD device. |
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|
802 * @param __INSTANCE__ FSMC_PCCARD Instance |
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803 * @param __FLAG__ FSMC_PCCARD flag |
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|
804 * This parameter can be any combination of the following values: |
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Added current STM32 standandard libraries in version independend folder structure
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|
805 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
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|
806 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
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|
807 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
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|
808 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
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809 * @retval The state of FLAG (SET or RESET). |
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|
810 */ |
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|
811 #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
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|
812 |
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|
813 /** |
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|
814 * @brief Clear flag status of the PCCARD device. |
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Added current STM32 standandard libraries in version independend folder structure
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|
815 * @param __INSTANCE__ FSMC_PCCARD Instance |
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|
816 * @param __FLAG__ FSMC_PCCARD flag |
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|
817 * This parameter can be any combination of the following values: |
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|
818 * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
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Added current STM32 standandard libraries in version independend folder structure
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|
819 * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
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|
820 * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
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Added current STM32 standandard libraries in version independend folder structure
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|
821 * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
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|
822 * @retval None |
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|
823 */ |
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|
824 #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
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|
825 /** |
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|
826 * @} |
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|
827 */ |
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828 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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|
829 |
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830 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros |
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|
831 * @{ |
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|
832 */ |
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|
833 #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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834 ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
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|
835 ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
836 ((__BANK__) == FSMC_NORSRAM_BANK4)) |
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|
837 |
c78bcbd5deda
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|
838 #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
839 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
840 |
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|
841 #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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842 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
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843 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
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|
844 |
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|
845 #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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846 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
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847 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
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|
848 |
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|
849 #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
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850 ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
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851 ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
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852 ((__MODE__) == FSMC_ACCESS_MODE_D)) |
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|
853 |
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|
854 #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ |
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855 ((BANK) == FSMC_NAND_BANK3)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
856 |
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|
857 #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
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858 ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
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|
859 |
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|
860 #define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
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861 ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
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|
862 |
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|
863 #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ |
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864 ((STATE) == FSMC_NAND_ECC_ENABLE)) |
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|
865 |
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866 #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
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867 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
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868 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
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869 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
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870 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
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871 ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
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|
872 |
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|
873 #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) |
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|
874 |
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|
875 #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) |
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|
876 |
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877 #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) |
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|
878 |
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|
879 #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) |
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|
880 |
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|
881 #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) |
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|
882 |
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|
883 #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) |
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|
884 |
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885 #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
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|
886 |
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|
887 #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
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888 |
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889 #define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) |
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890 |
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891 #define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) |
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892 |
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893 #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
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894 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
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895 |
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896 #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
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897 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
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898 |
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899 #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
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900 ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
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901 |
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902 #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
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903 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
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904 |
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905 #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
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906 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
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907 |
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908 #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
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909 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
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910 |
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911 #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
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912 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
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913 |
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914 #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
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915 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
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916 |
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917 #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
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918 |
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919 #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
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920 ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
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921 |
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922 #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
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923 |
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924 #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
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925 |
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926 #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
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927 |
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928 #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
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929 |
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930 #define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
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931 ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
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|
932 |
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933 #define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) |
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|
934 |
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935 #define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ |
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936 ((SIZE) == FSMC_PAGE_SIZE_128) || \ |
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937 ((SIZE) == FSMC_PAGE_SIZE_256) || \ |
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938 ((SIZE) == FSMC_PAGE_SIZE_512) || \ |
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939 ((SIZE) == FSMC_PAGE_SIZE_1024)) |
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940 |
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941 #define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ |
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942 ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) |
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943 |
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944 /** |
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945 * @} |
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946 */ |
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947 /** |
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948 * @} |
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949 */ |
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950 |
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951 /* Private functions ---------------------------------------------------------*/ |
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952 /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
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953 * @{ |
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954 */ |
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|
955 |
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956 /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
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957 * @{ |
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|
958 */ |
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|
959 |
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960 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
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961 * @{ |
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|
962 */ |
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963 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); |
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964 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
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965 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
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966 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
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967 /** |
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968 * @} |
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969 */ |
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970 |
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971 /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
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972 * @{ |
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973 */ |
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974 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
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975 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
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976 /** |
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977 * @} |
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978 */ |
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979 /** |
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980 * @} |
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981 */ |
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982 |
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983 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) |
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984 /** @defgroup FSMC_LL_NAND NAND |
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985 * @{ |
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986 */ |
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987 /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
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988 * @{ |
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989 */ |
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990 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
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991 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
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992 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
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993 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
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994 /** |
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995 * @} |
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996 */ |
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997 |
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998 /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
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999 * @{ |
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1000 */ |
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1001 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
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1002 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
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1003 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); |
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1004 /** |
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1005 * @} |
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1006 */ |
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1007 /** |
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1008 * @} |
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1009 */ |
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1010 |
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1011 /** @defgroup FSMC_LL_PCCARD PCCARD |
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1012 * @{ |
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1013 */ |
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1014 /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions |
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1015 * @{ |
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1016 */ |
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1017 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
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1018 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
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1019 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
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1020 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); |
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1021 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
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1022 /** |
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1023 * @} |
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1024 */ |
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1025 /** |
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1026 * @} |
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1027 */ |
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1028 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
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1029 |
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1030 /** |
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1031 * @} |
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1032 */ |
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1033 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ |
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1034 |
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1035 /** |
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1036 * @} |
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1037 */ |
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1038 |
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1039 /** |
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1040 * @} |
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1041 */ |
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1042 |
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1043 #ifdef __cplusplus |
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1044 } |
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1045 #endif |
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1046 |
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1047 #endif /* __STM32F4xx_LL_FSMC_H */ |
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1048 |
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1049 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |