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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usart.c @ 750:6bd21ebe1a93

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author Ideenmodellierer
date Sun, 05 Mar 2023 22:17:32 +0100
parents c78bcbd5deda
children
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_usart.c
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4 * @author MCD Application Team
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5 * @brief USART LL module driver.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35 #if defined(USE_FULL_LL_DRIVER)
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36
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37 /* Includes ------------------------------------------------------------------*/
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38 #include "stm32f4xx_ll_usart.h"
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39 #include "stm32f4xx_ll_rcc.h"
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40 #include "stm32f4xx_ll_bus.h"
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41 #ifdef USE_FULL_ASSERT
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42 #include "stm32_assert.h"
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43 #else
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44 #define assert_param(expr) ((void)0U)
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45 #endif
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46
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47 /** @addtogroup STM32F4xx_LL_Driver
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48 * @{
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49 */
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50
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51 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
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52
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53 /** @addtogroup USART_LL
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54 * @{
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55 */
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56
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57 /* Private types -------------------------------------------------------------*/
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58 /* Private variables ---------------------------------------------------------*/
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59 /* Private constants ---------------------------------------------------------*/
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60 /** @addtogroup USART_LL_Private_Constants
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61 * @{
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62 */
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63
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64 /**
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65 * @}
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66 */
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67
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68
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69 /* Private macros ------------------------------------------------------------*/
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70 /** @addtogroup USART_LL_Private_Macros
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71 * @{
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72 */
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73
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74 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
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75 * divided by the smallest oversampling used on the USART (i.e. 8) */
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76 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
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77
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78 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
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79 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
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80
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81 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
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82 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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83
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84 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
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85 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
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86 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
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87 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
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88
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89 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
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90 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
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91 || ((__VALUE__) == LL_USART_PARITY_ODD))
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92
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93 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
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94 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
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95
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96 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
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97 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
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98
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99 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
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100 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
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101
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102 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
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103 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
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104
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105 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
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106 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
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107
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108 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
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109 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
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110
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111 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
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112 || ((__VALUE__) == LL_USART_STOPBITS_1) \
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113 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
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114 || ((__VALUE__) == LL_USART_STOPBITS_2))
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115
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116 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
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117 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
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118 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
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119 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
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120
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121 /**
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122 * @}
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123 */
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124
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125 /* Private function prototypes -----------------------------------------------*/
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126
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127 /* Exported functions --------------------------------------------------------*/
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128 /** @addtogroup USART_LL_Exported_Functions
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129 * @{
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130 */
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131
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132 /** @addtogroup USART_LL_EF_Init
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133 * @{
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134 */
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135
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136 /**
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137 * @brief De-initialize USART registers (Registers restored to their default values).
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138 * @param USARTx USART Instance
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139 * @retval An ErrorStatus enumeration value:
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140 * - SUCCESS: USART registers are de-initialized
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141 * - ERROR: USART registers are not de-initialized
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142 */
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143 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
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144 {
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145 ErrorStatus status = SUCCESS;
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146
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147 /* Check the parameters */
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148 assert_param(IS_UART_INSTANCE(USARTx));
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149
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150 if (USARTx == USART1)
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151 {
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152 /* Force reset of USART clock */
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153 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
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154
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155 /* Release reset of USART clock */
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156 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
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157 }
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158 else if (USARTx == USART2)
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159 {
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160 /* Force reset of USART clock */
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161 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
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162
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163 /* Release reset of USART clock */
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164 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
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165 }
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166 #if defined(USART3)
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167 else if (USARTx == USART3)
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168 {
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169 /* Force reset of USART clock */
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170 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
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171
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172 /* Release reset of USART clock */
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173 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
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174 }
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175 #endif /* USART3 */
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176 #if defined(USART6)
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177 else if (USARTx == USART6)
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178 {
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179 /* Force reset of USART clock */
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180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
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181
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182 /* Release reset of USART clock */
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183 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
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184 }
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185 #endif /* USART6 */
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186 #if defined(UART4)
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187 else if (USARTx == UART4)
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188 {
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189 /* Force reset of UART clock */
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190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
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191
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192 /* Release reset of UART clock */
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193 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
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194 }
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195 #endif /* UART4 */
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196 #if defined(UART5)
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197 else if (USARTx == UART5)
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198 {
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199 /* Force reset of UART clock */
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200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
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201
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202 /* Release reset of UART clock */
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203 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
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204 }
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205 #endif /* UART5 */
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206 #if defined(UART7)
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207 else if (USARTx == UART7)
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208 {
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209 /* Force reset of UART clock */
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210 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
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211
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212 /* Release reset of UART clock */
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213 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
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214 }
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215 #endif /* UART7 */
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216 #if defined(UART8)
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217 else if (USARTx == UART8)
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218 {
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219 /* Force reset of UART clock */
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220 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
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221
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222 /* Release reset of UART clock */
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223 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
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224 }
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225 #endif /* UART8 */
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226 #if defined(UART9)
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227 else if (USARTx == UART9)
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228 {
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229 /* Force reset of UART clock */
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230 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
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231
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232 /* Release reset of UART clock */
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233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
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234 }
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235 #endif /* UART9 */
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236 #if defined(UART10)
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237 else if (USARTx == UART10)
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238 {
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239 /* Force reset of UART clock */
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240 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
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241
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242 /* Release reset of UART clock */
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243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
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244 }
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245 #endif /* UART10 */
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246 else
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247 {
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248 status = ERROR;
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249 }
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250
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251 return (status);
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252 }
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253
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254 /**
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255 * @brief Initialize USART registers according to the specified
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256 * parameters in USART_InitStruct.
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257 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
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258 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
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259 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
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260 * @param USARTx USART Instance
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261 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
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262 * that contains the configuration information for the specified USART peripheral.
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263 * @retval An ErrorStatus enumeration value:
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264 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
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265 * - ERROR: Problem occurred during USART Registers initialization
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266 */
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267 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
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268 {
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269 ErrorStatus status = ERROR;
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270 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
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271 LL_RCC_ClocksTypeDef rcc_clocks;
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272
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273 /* Check the parameters */
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274 assert_param(IS_UART_INSTANCE(USARTx));
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275 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
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276 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
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277 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
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278 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
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279 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
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280 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
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281 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
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282
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283 /* USART needs to be in disabled state, in order to be able to configure some bits in
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284 CRx registers */
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285 if (LL_USART_IsEnabled(USARTx) == 0U)
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286 {
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287 /*---------------------------- USART CR1 Configuration -----------------------
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288 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
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289 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
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290 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
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291 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
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292 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
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293 */
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294 MODIFY_REG(USARTx->CR1,
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295 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
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296 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
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297 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
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298 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
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299
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300 /*---------------------------- USART CR2 Configuration -----------------------
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301 * Configure USARTx CR2 (Stop bits) with parameters:
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302 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
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303 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
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304 */
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305 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
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306
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307 /*---------------------------- USART CR3 Configuration -----------------------
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308 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
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309 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
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310 */
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311 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
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312
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313 /*---------------------------- USART BRR Configuration -----------------------
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314 * Retrieve Clock frequency used for USART Peripheral
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315 */
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316 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
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317 if (USARTx == USART1)
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318 {
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319 periphclk = rcc_clocks.PCLK2_Frequency;
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320 }
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321 else if (USARTx == USART2)
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322 {
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323 periphclk = rcc_clocks.PCLK1_Frequency;
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324 }
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325 #if defined(USART3)
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326 else if (USARTx == USART3)
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327 {
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328 periphclk = rcc_clocks.PCLK1_Frequency;
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329 }
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330 #endif /* USART3 */
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331 #if defined(USART6)
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332 else if (USARTx == USART6)
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333 {
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334 periphclk = rcc_clocks.PCLK2_Frequency;
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335 }
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336 #endif /* USART6 */
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337 #if defined(UART4)
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338 else if (USARTx == UART4)
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339 {
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340 periphclk = rcc_clocks.PCLK1_Frequency;
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341 }
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342 #endif /* UART4 */
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343 #if defined(UART5)
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344 else if (USARTx == UART5)
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345 {
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346 periphclk = rcc_clocks.PCLK1_Frequency;
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347 }
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348 #endif /* UART5 */
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349 #if defined(UART7)
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350 else if (USARTx == UART7)
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351 {
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352 periphclk = rcc_clocks.PCLK1_Frequency;
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353 }
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354 #endif /* UART7 */
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355 #if defined(UART8)
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356 else if (USARTx == UART8)
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357 {
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358 periphclk = rcc_clocks.PCLK1_Frequency;
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359 }
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360 #endif /* UART8 */
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361 #if defined(UART9)
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362 else if (USARTx == UART9)
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363 {
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364 periphclk = rcc_clocks.PCLK1_Frequency;
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365 }
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366 #endif /* UART9 */
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367 #if defined(UART10)
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368 else if (USARTx == UART10)
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369 {
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370 periphclk = rcc_clocks.PCLK1_Frequency;
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371 }
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372 #endif /* UART10 */
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373 else
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374 {
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375 /* Nothing to do, as error code is already assigned to ERROR value */
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376 }
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377
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378 /* Configure the USART Baud Rate :
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379 - valid baud rate value (different from 0) is required
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380 - Peripheral clock as returned by RCC service, should be valid (different from 0).
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381 */
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382 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
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383 && (USART_InitStruct->BaudRate != 0U))
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384 {
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385 status = SUCCESS;
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386 LL_USART_SetBaudRate(USARTx,
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387 periphclk,
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388 USART_InitStruct->OverSampling,
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389 USART_InitStruct->BaudRate);
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390
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391 /* Check BRR is greater than or equal to 16d */
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392 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
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393
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394 /* Check BRR is greater than or equal to 16d */
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395 assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
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396 }
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397 }
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398 /* Endif (=> USART not in Disabled state => return ERROR) */
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399
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400 return (status);
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401 }
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402
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403 /**
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404 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
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405 * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
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406 * whose fields will be set to default values.
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407 * @retval None
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408 */
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409
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410 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
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411 {
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412 /* Set USART_InitStruct fields to default values */
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413 USART_InitStruct->BaudRate = 9600U;
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414 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
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415 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
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416 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
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417 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
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418 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
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419 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
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420 }
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421
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422 /**
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423 * @brief Initialize USART Clock related settings according to the
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424 * specified parameters in the USART_ClockInitStruct.
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425 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
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426 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
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427 * @param USARTx USART Instance
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428 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
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429 * that contains the Clock configuration information for the specified USART peripheral.
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430 * @retval An ErrorStatus enumeration value:
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431 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
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432 * - ERROR: Problem occurred during USART Registers initialization
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433 */
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434 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
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435 {
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436 ErrorStatus status = SUCCESS;
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437
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438 /* Check USART Instance and Clock signal output parameters */
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439 assert_param(IS_UART_INSTANCE(USARTx));
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440 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
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441
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442 /* USART needs to be in disabled state, in order to be able to configure some bits in
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443 CRx registers */
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444 if (LL_USART_IsEnabled(USARTx) == 0U)
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445 {
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446 /*---------------------------- USART CR2 Configuration -----------------------*/
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447 /* If Clock signal has to be output */
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448 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
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449 {
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450 /* Deactivate Clock signal delivery :
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451 * - Disable Clock Output: USART_CR2_CLKEN cleared
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452 */
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453 LL_USART_DisableSCLKOutput(USARTx);
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454 }
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455 else
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456 {
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457 /* Ensure USART instance is USART capable */
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458 assert_param(IS_USART_INSTANCE(USARTx));
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459
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460 /* Check clock related parameters */
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461 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
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462 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
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463 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
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464
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465 /*---------------------------- USART CR2 Configuration -----------------------
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466 * Configure USARTx CR2 (Clock signal related bits) with parameters:
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467 * - Enable Clock Output: USART_CR2_CLKEN set
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468 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
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469 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
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470 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
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471 */
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472 MODIFY_REG(USARTx->CR2,
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473 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
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474 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
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475 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
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476 }
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477 }
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478 /* Else (USART not in Disabled state => return ERROR */
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479 else
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480 {
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481 status = ERROR;
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482 }
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483
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484 return (status);
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485 }
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486
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487 /**
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488 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
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489 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
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490 * whose fields will be set to default values.
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491 * @retval None
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492 */
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493 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
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494 {
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495 /* Set LL_USART_ClockInitStruct fields with default values */
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496 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
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497 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
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498 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
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499 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
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500 }
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501
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502 /**
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503 * @}
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504 */
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505
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506 /**
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507 * @}
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508 */
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509
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510 /**
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511 * @}
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512 */
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513
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514 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
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515
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516 /**
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517 * @}
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518 */
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519
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520 #endif /* USE_FULL_LL_DRIVER */
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521
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522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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523