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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f407xx.h
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral’s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32f407xx
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49 * @{
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50 */
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51
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52 #ifndef __STM32F407xx_H
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53 #define __STM32F407xx_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59
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60 /** @addtogroup Configuration_section_for_CMSIS
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61 * @{
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62 */
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63
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64 /**
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65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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66 */
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67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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71 #define __FPU_PRESENT 1 /*!< FPU present */
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72
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73 /**
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74 * @}
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75 */
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76
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77 /** @addtogroup Peripheral_interrupt_number_definition
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78 * @{
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79 */
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80
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81 /**
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82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
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83 * in @ref Library_configuration_section
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84 */
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85 typedef enum
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86 {
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87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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96 /****** STM32 specific Interrupt Numbers **********************************************************************/
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97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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102 RCC_IRQn = 5, /*!< RCC global Interrupt */
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103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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116 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
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117 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
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118 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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119 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
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120 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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121 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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122 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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123 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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124 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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125 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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126 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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127 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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128 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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129 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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130 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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131 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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132 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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133 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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134 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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135 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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136 USART3_IRQn = 39, /*!< USART3 global Interrupt */
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137 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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138 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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139 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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140 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
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141 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
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142 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
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143 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
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144 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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145 FSMC_IRQn = 48, /*!< FSMC global Interrupt */
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146 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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147 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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148 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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149 UART4_IRQn = 52, /*!< UART4 global Interrupt */
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150 UART5_IRQn = 53, /*!< UART5 global Interrupt */
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151 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
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152 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
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153 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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154 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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155 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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156 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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157 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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158 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
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159 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
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160 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
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161 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
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162 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
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163 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
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164 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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165 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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166 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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167 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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168 USART6_IRQn = 71, /*!< USART6 global interrupt */
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169 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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170 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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171 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
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172 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
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173 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
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174 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
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175 DCMI_IRQn = 78, /*!< DCMI global interrupt */
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176 HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */
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177 FPU_IRQn = 81 /*!< FPU global interrupt */
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178 } IRQn_Type;
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179
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180 /**
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181 * @}
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182 */
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183
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184 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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185 #include "system_stm32f4xx.h"
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186 #include <stdint.h>
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187
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188 /** @addtogroup Peripheral_registers_structures
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189 * @{
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190 */
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191
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192 /**
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193 * @brief Analog to Digital Converter
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194 */
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195
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196 typedef struct
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197 {
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198 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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199 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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200 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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201 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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202 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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203 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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204 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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205 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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206 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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207 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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208 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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209 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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210 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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211 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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212 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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213 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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214 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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215 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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216 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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217 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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218 } ADC_TypeDef;
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219
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220 typedef struct
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221 {
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222 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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223 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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224 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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225 AND triple modes, Address offset: ADC1 base address + 0x308 */
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226 } ADC_Common_TypeDef;
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227
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228
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229 /**
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230 * @brief Controller Area Network TxMailBox
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231 */
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232
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233 typedef struct
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234 {
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235 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
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236 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
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237 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
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238 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
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239 } CAN_TxMailBox_TypeDef;
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240
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241 /**
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242 * @brief Controller Area Network FIFOMailBox
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243 */
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244
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245 typedef struct
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246 {
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247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
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248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
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249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
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250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
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251 } CAN_FIFOMailBox_TypeDef;
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252
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253 /**
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254 * @brief Controller Area Network FilterRegister
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255 */
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256
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257 typedef struct
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258 {
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259 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
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260 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
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261 } CAN_FilterRegister_TypeDef;
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262
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263 /**
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264 * @brief Controller Area Network
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265 */
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266
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267 typedef struct
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268 {
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269 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
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270 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
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271 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
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272 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
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273 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
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274 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
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275 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
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276 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
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277 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
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278 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
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279 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
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280 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
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281 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
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282 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
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283 uint32_t RESERVED2; /*!< Reserved, 0x208 */
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284 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
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285 uint32_t RESERVED3; /*!< Reserved, 0x210 */
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286 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
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287 uint32_t RESERVED4; /*!< Reserved, 0x218 */
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288 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
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289 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
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290 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
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291 } CAN_TypeDef;
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292
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293 /**
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294 * @brief CRC calculation unit
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295 */
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296
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297 typedef struct
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298 {
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299 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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300 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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301 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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302 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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303 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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304 } CRC_TypeDef;
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305
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306 /**
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307 * @brief Digital to Analog Converter
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308 */
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309
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310 typedef struct
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311 {
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312 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
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313 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
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314 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
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315 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
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316 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
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317 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
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318 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
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319 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
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320 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
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321 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
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322 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
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323 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
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324 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
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325 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
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326 } DAC_TypeDef;
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327
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328 /**
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329 * @brief Debug MCU
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330 */
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331
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332 typedef struct
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333 {
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334 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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335 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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336 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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337 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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338 }DBGMCU_TypeDef;
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339
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340 /**
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341 * @brief DCMI
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342 */
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343
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344 typedef struct
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345 {
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346 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
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347 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
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348 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
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349 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
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350 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
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351 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
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352 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
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353 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
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354 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
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355 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
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356 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
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357 } DCMI_TypeDef;
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358
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359 /**
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360 * @brief DMA Controller
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361 */
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362
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363 typedef struct
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364 {
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365 __IO uint32_t CR; /*!< DMA stream x configuration register */
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366 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
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367 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
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368 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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369 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
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370 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
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371 } DMA_Stream_TypeDef;
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372
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373 typedef struct
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374 {
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375 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
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376 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
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377 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
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378 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
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379 } DMA_TypeDef;
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380
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381
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382 /**
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|
|
383 * @brief Ethernet MAC
|
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384 */
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385
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386 typedef struct
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387 {
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388 __IO uint32_t MACCR;
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|
389 __IO uint32_t MACFFR;
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390 __IO uint32_t MACHTHR;
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|
391 __IO uint32_t MACHTLR;
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|
392 __IO uint32_t MACMIIAR;
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|
393 __IO uint32_t MACMIIDR;
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|
394 __IO uint32_t MACFCR;
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|
|
395 __IO uint32_t MACVLANTR; /* 8 */
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|
|
396 uint32_t RESERVED0[2];
|
|
|
397 __IO uint32_t MACRWUFFR; /* 11 */
|
|
|
398 __IO uint32_t MACPMTCSR;
|
|
|
399 uint32_t RESERVED1[2];
|
|
|
400 __IO uint32_t MACSR; /* 15 */
|
|
|
401 __IO uint32_t MACIMR;
|
|
|
402 __IO uint32_t MACA0HR;
|
|
|
403 __IO uint32_t MACA0LR;
|
|
|
404 __IO uint32_t MACA1HR;
|
|
|
405 __IO uint32_t MACA1LR;
|
|
|
406 __IO uint32_t MACA2HR;
|
|
|
407 __IO uint32_t MACA2LR;
|
|
|
408 __IO uint32_t MACA3HR;
|
|
|
409 __IO uint32_t MACA3LR; /* 24 */
|
|
|
410 uint32_t RESERVED2[40];
|
|
|
411 __IO uint32_t MMCCR; /* 65 */
|
|
|
412 __IO uint32_t MMCRIR;
|
|
|
413 __IO uint32_t MMCTIR;
|
|
|
414 __IO uint32_t MMCRIMR;
|
|
|
415 __IO uint32_t MMCTIMR; /* 69 */
|
|
|
416 uint32_t RESERVED3[14];
|
|
|
417 __IO uint32_t MMCTGFSCCR; /* 84 */
|
|
|
418 __IO uint32_t MMCTGFMSCCR;
|
|
|
419 uint32_t RESERVED4[5];
|
|
|
420 __IO uint32_t MMCTGFCR;
|
|
|
421 uint32_t RESERVED5[10];
|
|
|
422 __IO uint32_t MMCRFCECR;
|
|
|
423 __IO uint32_t MMCRFAECR;
|
|
|
424 uint32_t RESERVED6[10];
|
|
|
425 __IO uint32_t MMCRGUFCR;
|
|
|
426 uint32_t RESERVED7[334];
|
|
|
427 __IO uint32_t PTPTSCR;
|
|
|
428 __IO uint32_t PTPSSIR;
|
|
|
429 __IO uint32_t PTPTSHR;
|
|
|
430 __IO uint32_t PTPTSLR;
|
|
|
431 __IO uint32_t PTPTSHUR;
|
|
|
432 __IO uint32_t PTPTSLUR;
|
|
|
433 __IO uint32_t PTPTSAR;
|
|
|
434 __IO uint32_t PTPTTHR;
|
|
|
435 __IO uint32_t PTPTTLR;
|
|
|
436 __IO uint32_t RESERVED8;
|
|
|
437 __IO uint32_t PTPTSSR;
|
|
|
438 uint32_t RESERVED9[565];
|
|
|
439 __IO uint32_t DMABMR;
|
|
|
440 __IO uint32_t DMATPDR;
|
|
|
441 __IO uint32_t DMARPDR;
|
|
|
442 __IO uint32_t DMARDLAR;
|
|
|
443 __IO uint32_t DMATDLAR;
|
|
|
444 __IO uint32_t DMASR;
|
|
|
445 __IO uint32_t DMAOMR;
|
|
|
446 __IO uint32_t DMAIER;
|
|
|
447 __IO uint32_t DMAMFBOCR;
|
|
|
448 __IO uint32_t DMARSWTR;
|
|
|
449 uint32_t RESERVED10[8];
|
|
|
450 __IO uint32_t DMACHTDR;
|
|
|
451 __IO uint32_t DMACHRDR;
|
|
|
452 __IO uint32_t DMACHTBAR;
|
|
|
453 __IO uint32_t DMACHRBAR;
|
|
|
454 } ETH_TypeDef;
|
|
|
455
|
|
|
456 /**
|
|
|
457 * @brief External Interrupt/Event Controller
|
|
|
458 */
|
|
|
459
|
|
|
460 typedef struct
|
|
|
461 {
|
|
|
462 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
|
|
|
463 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
|
|
|
464 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
|
|
|
465 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
|
|
|
466 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
|
|
|
467 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
|
|
|
468 } EXTI_TypeDef;
|
|
|
469
|
|
|
470 /**
|
|
|
471 * @brief FLASH Registers
|
|
|
472 */
|
|
|
473
|
|
|
474 typedef struct
|
|
|
475 {
|
|
|
476 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
|
|
|
477 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
|
|
|
478 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
|
|
|
479 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
|
|
|
480 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
|
|
|
481 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
|
|
|
482 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
|
|
|
483 } FLASH_TypeDef;
|
|
|
484
|
|
|
485
|
|
|
486 /**
|
|
|
487 * @brief Flexible Static Memory Controller
|
|
|
488 */
|
|
|
489
|
|
|
490 typedef struct
|
|
|
491 {
|
|
|
492 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
|
|
|
493 } FSMC_Bank1_TypeDef;
|
|
|
494
|
|
|
495 /**
|
|
|
496 * @brief Flexible Static Memory Controller Bank1E
|
|
|
497 */
|
|
|
498
|
|
|
499 typedef struct
|
|
|
500 {
|
|
|
501 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
|
|
|
502 } FSMC_Bank1E_TypeDef;
|
|
|
503
|
|
|
504 /**
|
|
|
505 * @brief Flexible Static Memory Controller Bank2
|
|
|
506 */
|
|
|
507
|
|
|
508 typedef struct
|
|
|
509 {
|
|
|
510 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
|
|
|
511 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
|
|
|
512 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
|
|
|
513 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
|
|
|
514 uint32_t RESERVED0; /*!< Reserved, 0x70 */
|
|
|
515 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
|
|
|
516 uint32_t RESERVED1; /*!< Reserved, 0x78 */
|
|
|
517 uint32_t RESERVED2; /*!< Reserved, 0x7C */
|
|
|
518 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
|
|
|
519 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
|
|
|
520 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
|
|
|
521 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
|
|
|
522 uint32_t RESERVED3; /*!< Reserved, 0x90 */
|
|
|
523 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
|
|
|
524 } FSMC_Bank2_3_TypeDef;
|
|
|
525
|
|
|
526 /**
|
|
|
527 * @brief Flexible Static Memory Controller Bank4
|
|
|
528 */
|
|
|
529
|
|
|
530 typedef struct
|
|
|
531 {
|
|
|
532 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
|
|
|
533 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
|
|
|
534 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
|
|
|
535 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
|
|
|
536 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
|
|
|
537 } FSMC_Bank4_TypeDef;
|
|
|
538
|
|
|
539
|
|
|
540 /**
|
|
|
541 * @brief General Purpose I/O
|
|
|
542 */
|
|
|
543
|
|
|
544 typedef struct
|
|
|
545 {
|
|
|
546 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
|
|
|
547 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
|
|
|
548 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
|
|
|
549 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
|
|
|
550 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
|
|
|
551 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
|
|
|
552 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
|
|
|
553 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
|
|
|
554 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
|
|
|
555 } GPIO_TypeDef;
|
|
|
556
|
|
|
557 /**
|
|
|
558 * @brief System configuration controller
|
|
|
559 */
|
|
|
560
|
|
|
561 typedef struct
|
|
|
562 {
|
|
|
563 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
|
|
|
564 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
|
|
|
565 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
|
|
|
566 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
|
|
|
567 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
|
|
|
568 } SYSCFG_TypeDef;
|
|
|
569
|
|
|
570 /**
|
|
|
571 * @brief Inter-integrated Circuit Interface
|
|
|
572 */
|
|
|
573
|
|
|
574 typedef struct
|
|
|
575 {
|
|
|
576 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
|
|
|
577 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
|
|
|
578 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
|
|
|
579 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
|
|
|
580 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
|
|
|
581 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
|
|
|
582 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
|
|
|
583 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
|
|
|
584 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
|
|
|
585 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
|
|
|
586 } I2C_TypeDef;
|
|
|
587
|
|
|
588 /**
|
|
|
589 * @brief Independent WATCHDOG
|
|
|
590 */
|
|
|
591
|
|
|
592 typedef struct
|
|
|
593 {
|
|
|
594 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
|
|
|
595 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
|
|
|
596 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
|
|
|
597 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
|
|
|
598 } IWDG_TypeDef;
|
|
|
599
|
|
|
600 /**
|
|
|
601 * @brief Power Control
|
|
|
602 */
|
|
|
603
|
|
|
604 typedef struct
|
|
|
605 {
|
|
|
606 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
|
|
|
607 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
|
|
|
608 } PWR_TypeDef;
|
|
|
609
|
|
|
610 /**
|
|
|
611 * @brief Reset and Clock Control
|
|
|
612 */
|
|
|
613
|
|
|
614 typedef struct
|
|
|
615 {
|
|
|
616 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
|
|
|
617 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
|
|
|
618 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
|
|
|
619 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
|
|
|
620 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
|
|
|
621 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
|
|
|
622 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
|
|
|
623 uint32_t RESERVED0; /*!< Reserved, 0x1C */
|
|
|
624 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
|
|
|
625 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
|
|
|
626 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
|
|
|
627 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
|
|
|
628 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
|
|
|
629 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
|
|
|
630 uint32_t RESERVED2; /*!< Reserved, 0x3C */
|
|
|
631 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
|
|
|
632 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
|
|
|
633 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
|
|
|
634 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
|
|
|
635 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
|
|
|
636 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
|
|
|
637 uint32_t RESERVED4; /*!< Reserved, 0x5C */
|
|
|
638 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
|
|
|
639 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
|
|
|
640 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
|
|
|
641 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
|
|
|
642 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
|
|
|
643 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
|
|
|
644 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
|
|
|
645 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
|
|
|
646
|
|
|
647 } RCC_TypeDef;
|
|
|
648
|
|
|
649 /**
|
|
|
650 * @brief Real-Time Clock
|
|
|
651 */
|
|
|
652
|
|
|
653 typedef struct
|
|
|
654 {
|
|
|
655 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
|
|
|
656 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
|
|
|
657 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
|
|
|
658 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
|
|
|
659 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
|
|
|
660 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
|
|
|
661 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
|
|
|
662 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
|
|
|
663 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
|
|
|
664 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
|
|
|
665 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
|
|
|
666 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
|
|
|
667 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
|
|
|
668 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
|
|
|
669 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
|
|
|
670 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
|
|
|
671 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
|
|
|
672 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
|
|
|
673 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
|
|
|
674 uint32_t RESERVED7; /*!< Reserved, 0x4C */
|
|
|
675 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
|
|
|
676 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
|
|
|
677 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
|
|
|
678 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
|
|
|
679 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
|
|
|
680 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
|
|
|
681 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
|
|
|
682 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
|
|
|
683 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
|
|
|
684 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
|
|
|
685 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
|
|
|
686 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
|
|
|
687 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
|
|
|
688 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
|
|
|
689 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
|
|
|
690 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
|
|
|
691 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
|
|
|
692 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
|
|
|
693 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
|
|
|
694 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
|
|
|
695 } RTC_TypeDef;
|
|
|
696
|
|
|
697
|
|
|
698 /**
|
|
|
699 * @brief SD host Interface
|
|
|
700 */
|
|
|
701
|
|
|
702 typedef struct
|
|
|
703 {
|
|
|
704 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
|
|
|
705 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
|
|
|
706 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
|
|
|
707 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
|
|
|
708 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
|
|
|
709 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
|
|
|
710 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
|
|
|
711 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
|
|
|
712 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
|
|
|
713 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
|
|
|
714 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
|
|
|
715 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
|
|
|
716 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
|
|
|
717 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
|
|
|
718 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
|
|
|
719 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
|
|
|
720 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
|
|
|
721 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
|
|
|
722 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
|
|
|
723 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
|
|
|
724 } SDIO_TypeDef;
|
|
|
725
|
|
|
726 /**
|
|
|
727 * @brief Serial Peripheral Interface
|
|
|
728 */
|
|
|
729
|
|
|
730 typedef struct
|
|
|
731 {
|
|
|
732 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
|
|
|
733 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
|
|
|
734 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
|
|
|
735 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
|
|
|
736 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
|
|
|
737 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
|
|
|
738 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
|
|
|
739 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
|
|
|
740 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
|
|
|
741 } SPI_TypeDef;
|
|
|
742
|
|
|
743 /**
|
|
|
744 * @brief TIM
|
|
|
745 */
|
|
|
746
|
|
|
747 typedef struct
|
|
|
748 {
|
|
|
749 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
|
|
|
750 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
|
|
|
751 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
|
|
|
752 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
|
|
|
753 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
|
|
|
754 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
|
|
|
755 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
|
|
|
756 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
|
|
|
757 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
|
|
|
758 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
|
|
|
759 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
|
|
|
760 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
|
|
|
761 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
|
|
|
762 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
|
|
|
763 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
|
|
|
764 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
|
|
|
765 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
|
|
|
766 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
|
|
|
767 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
|
|
|
768 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
|
|
|
769 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
|
|
|
770 } TIM_TypeDef;
|
|
|
771
|
|
|
772 /**
|
|
|
773 * @brief Universal Synchronous Asynchronous Receiver Transmitter
|
|
|
774 */
|
|
|
775
|
|
|
776 typedef struct
|
|
|
777 {
|
|
|
778 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
|
|
|
779 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
|
|
|
780 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
|
|
|
781 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
|
|
|
782 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
|
|
|
783 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
|
|
|
784 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
|
|
|
785 } USART_TypeDef;
|
|
|
786
|
|
|
787 /**
|
|
|
788 * @brief Window WATCHDOG
|
|
|
789 */
|
|
|
790
|
|
|
791 typedef struct
|
|
|
792 {
|
|
|
793 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
|
|
|
794 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
|
|
|
795 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
|
|
|
796 } WWDG_TypeDef;
|
|
|
797
|
|
|
798 /**
|
|
|
799 * @brief RNG
|
|
|
800 */
|
|
|
801
|
|
|
802 typedef struct
|
|
|
803 {
|
|
|
804 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
|
|
|
805 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
|
|
|
806 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
|
|
|
807 } RNG_TypeDef;
|
|
|
808
|
|
|
809
|
|
|
810
|
|
|
811 /**
|
|
|
812 * @brief __USB_OTG_Core_register
|
|
|
813 */
|
|
|
814 typedef struct
|
|
|
815 {
|
|
|
816 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/
|
|
|
817 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/
|
|
|
818 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/
|
|
|
819 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/
|
|
|
820 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/
|
|
|
821 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/
|
|
|
822 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/
|
|
|
823 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/
|
|
|
824 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/
|
|
|
825 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
|
|
|
826 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
|
|
|
827 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
|
|
|
828 uint32_t Reserved30[2]; /* Reserved 030h*/
|
|
|
829 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
|
|
|
830 __IO uint32_t CID; /* User ID Register 03Ch*/
|
|
|
831 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
|
|
|
832 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
|
|
|
833 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
|
|
|
834 }
|
|
|
835 USB_OTG_GlobalTypeDef;
|
|
|
836
|
|
|
837
|
|
|
838
|
|
|
839 /**
|
|
|
840 * @brief __device_Registers
|
|
|
841 */
|
|
|
842 typedef struct
|
|
|
843 {
|
|
|
844 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
|
|
|
845 __IO uint32_t DCTL; /* dev Control Register 804h*/
|
|
|
846 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
|
|
|
847 uint32_t Reserved0C; /* Reserved 80Ch*/
|
|
|
848 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
|
|
|
849 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
|
|
|
850 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
|
|
|
851 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
|
|
|
852 uint32_t Reserved20; /* Reserved 820h*/
|
|
|
853 uint32_t Reserved9; /* Reserved 824h*/
|
|
|
854 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
|
|
|
855 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
|
|
|
856 __IO uint32_t DTHRCTL; /* dev thr 830h*/
|
|
|
857 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
|
|
|
858 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
|
|
|
859 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
|
|
|
860 uint32_t Reserved40; /* dedicated EP mask 840h*/
|
|
|
861 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
|
|
|
862 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
|
|
|
863 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
|
|
|
864 }
|
|
|
865 USB_OTG_DeviceTypeDef;
|
|
|
866
|
|
|
867
|
|
|
868 /**
|
|
|
869 * @brief __IN_Endpoint-Specific_Register
|
|
|
870 */
|
|
|
871 typedef struct
|
|
|
872 {
|
|
|
873 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
|
|
|
874 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
|
|
|
875 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
|
|
|
876 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
|
|
|
877 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
|
|
|
878 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
|
|
|
879 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
|
|
|
880 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
|
|
|
881 }
|
|
|
882 USB_OTG_INEndpointTypeDef;
|
|
|
883
|
|
|
884
|
|
|
885 /**
|
|
|
886 * @brief __OUT_Endpoint-Specific_Registers
|
|
|
887 */
|
|
|
888 typedef struct
|
|
|
889 {
|
|
|
890 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
|
|
|
891 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
|
|
|
892 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
|
|
|
893 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
|
|
|
894 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
|
|
|
895 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
|
|
|
896 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
|
|
|
897 }
|
|
|
898 USB_OTG_OUTEndpointTypeDef;
|
|
|
899
|
|
|
900
|
|
|
901 /**
|
|
|
902 * @brief __Host_Mode_Register_Structures
|
|
|
903 */
|
|
|
904 typedef struct
|
|
|
905 {
|
|
|
906 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
|
|
|
907 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
|
|
|
908 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
|
|
|
909 uint32_t Reserved40C; /* Reserved 40Ch*/
|
|
|
910 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
|
|
|
911 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
|
|
|
912 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
|
|
|
913 }
|
|
|
914 USB_OTG_HostTypeDef;
|
|
|
915
|
|
|
916
|
|
|
917 /**
|
|
|
918 * @brief __Host_Channel_Specific_Registers
|
|
|
919 */
|
|
|
920 typedef struct
|
|
|
921 {
|
|
|
922 __IO uint32_t HCCHAR;
|
|
|
923 __IO uint32_t HCSPLT;
|
|
|
924 __IO uint32_t HCINT;
|
|
|
925 __IO uint32_t HCINTMSK;
|
|
|
926 __IO uint32_t HCTSIZ;
|
|
|
927 __IO uint32_t HCDMA;
|
|
|
928 uint32_t Reserved[2];
|
|
|
929 }
|
|
|
930 USB_OTG_HostChannelTypeDef;
|
|
|
931
|
|
|
932
|
|
|
933 /**
|
|
|
934 * @brief Peripheral_memory_map
|
|
|
935 */
|
|
|
936 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
|
|
|
937 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
|
|
|
938 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
|
|
|
939 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
|
|
|
940 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
|
|
|
941 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
|
|
|
942 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
|
|
|
943 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
|
|
944 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
|
|
|
945 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
|
|
|
946 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
|
|
|
947 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
|
|
|
948 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
|
|
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949 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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950 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
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951 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
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952
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|
953 /* Legacy defines */
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954 #define SRAM_BASE SRAM1_BASE
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955 #define SRAM_BB_BASE SRAM1_BB_BASE
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956
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957
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958 /*!< Peripheral memory map */
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959 #define APB1PERIPH_BASE PERIPH_BASE
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960 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
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961 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
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962 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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963
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964 /*!< APB1 peripherals */
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965 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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966 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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967 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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968 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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969 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
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970 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
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971 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
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972 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
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973 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
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974 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
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975 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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976 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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977 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
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978 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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979 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
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980 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
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981 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
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982 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
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983 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
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984 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
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985 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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986 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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987 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
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988 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
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989 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
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990 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
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991 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
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|
992
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993 /*!< APB2 peripherals */
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994 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
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995 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
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996 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
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997 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
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998 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
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999 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
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1000 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
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1001 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
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1002 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
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1003 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
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1004 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
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1005 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
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|
1006 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
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1007 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
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|
1008 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
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|
|
1009
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|
1010 /*!< AHB1 peripherals */
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|
1011 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
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|
1012 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
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|
1013 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
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1014 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
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|
1015 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
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1016 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
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|
|
1017 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
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|
|
1018 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
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|
|
1019 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
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1020 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
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1021 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
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1022 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
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1023 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
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1024 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
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|
1025 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
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|
1026 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
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|
1027 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
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|
|
1028 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
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|
|
1029 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
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|
|
1030 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
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|
|
1031 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
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|
|
1032 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
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|
|
1033 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
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|
|
1034 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
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|
|
1035 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
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|
1036 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
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|
|
1037 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
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|
|
1038 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
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|
|
1039 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
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|
|
1040 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
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|
|
1041 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
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|
|
1042 #define ETH_MAC_BASE (ETH_BASE)
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|
|
1043 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
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|
|
1044 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
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|
|
1045 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
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|
|
1046
|
|
|
1047 /*!< AHB2 peripherals */
|
|
|
1048 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
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|
|
1049 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
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|
|
1050
|
|
|
1051 /*!< FSMC Bankx registers base address */
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|
|
1052 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
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|
|
1053 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
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|
|
1054 #define FSMC_Bank2_3_R_BASE (FSMC_R_BASE + 0x0060)
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|
|
1055 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
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|
|
1056
|
|
|
1057 /* Debug MCU registers base address */
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|
|
1058 #define DBGMCU_BASE ((uint32_t )0xE0042000)
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|
|
1059
|
|
|
1060 /*!< USB registers base address */
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|
|
1061 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
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|
|
1062 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
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|
|
1063
|
|
|
1064 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
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|
|
1065 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
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|
1066 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
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|
|
1067 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
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|
|
1068 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
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|
|
1069 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
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|
1070 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
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|
1071 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
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1072 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
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1073 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
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1074 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
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|
1075 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
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|
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1076
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|
|
1077 /**
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|
1078 * @}
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|
|
1079 */
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|
|
1080
|
|
|
1081 /** @addtogroup Peripheral_declaration
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1082 * @{
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|
1083 */
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1084 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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1085 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
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1086 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
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1087 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
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1088 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
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1089 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
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1090 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
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1091 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
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1092 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
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1093 #define RTC ((RTC_TypeDef *) RTC_BASE)
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1094 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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1095 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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1096 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
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1097 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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|
1098 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
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1099 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
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1100 #define USART2 ((USART_TypeDef *) USART2_BASE)
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1101 #define USART3 ((USART_TypeDef *) USART3_BASE)
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1102 #define UART4 ((USART_TypeDef *) UART4_BASE)
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1103 #define UART5 ((USART_TypeDef *) UART5_BASE)
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1104 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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1105 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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1106 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
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1107 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
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1108 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
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|
1109 #define PWR ((PWR_TypeDef *) PWR_BASE)
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1110 #define DAC ((DAC_TypeDef *) DAC_BASE)
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1111 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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1112 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
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1113 #define USART1 ((USART_TypeDef *) USART1_BASE)
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|
1114 #define USART6 ((USART_TypeDef *) USART6_BASE)
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|
1115 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
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1116 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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1117 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
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1118 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
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|
1119 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
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|
1120 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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|
1121 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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|
1122 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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|
1123 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
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|
1124 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
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|
1125 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
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|
1126 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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|
1127 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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|
1128 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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|
1129 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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|
1130 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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|
1131 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
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|
1132 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
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|
1133 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
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|
|
1134 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
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|
1135 #define CRC ((CRC_TypeDef *) CRC_BASE)
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|
1136 #define RCC ((RCC_TypeDef *) RCC_BASE)
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|
1137 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
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|
1138 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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|
1139 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
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|
1140 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
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|
1141 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
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|
1142 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
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|
1143 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
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|
1144 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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|
1145 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
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|
1146 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
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|
1147 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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|
1148 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
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|
1149 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
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|
1150 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
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|
1151 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
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|
1152 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
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|
1153 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
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|
1154 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
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|
1155 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
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|
1156 #define ETH ((ETH_TypeDef *) ETH_BASE)
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|
1157 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
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|
1158 #define RNG ((RNG_TypeDef *) RNG_BASE)
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|
1159 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
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|
1160 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
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|
1161 #define FSMC_Bank2_3 ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
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|
1162 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
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|
1163
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|
1164 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
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1165
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|
1166 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
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|
1167 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
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|
|
1168
|
|
|
1169 /**
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|
|
1170 * @}
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|
|
1171 */
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|
|
1172
|
|
|
1173 /** @addtogroup Exported_constants
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|
|
1174 * @{
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|
1175 */
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1176
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|
|
1177 /** @addtogroup Peripheral_Registers_Bits_Definition
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|
1178 * @{
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|
|
1179 */
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|
|
1180
|
|
|
1181 /******************************************************************************/
|
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|
1182 /* Peripheral Registers_Bits_Definition */
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|
|
1183 /******************************************************************************/
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|
|
1184
|
|
|
1185 /******************************************************************************/
|
|
|
1186 /* */
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|
|
1187 /* Analog to Digital Converter */
|
|
|
1188 /* */
|
|
|
1189 /******************************************************************************/
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|
|
1190 /******************** Bit definition for ADC_SR register ********************/
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|
1191 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
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|
1192 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
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|
1193 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
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|
1194 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
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|
1195 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
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|
1196 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
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1197
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|
|
1198 /******************* Bit definition for ADC_CR1 register ********************/
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|
1199 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
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|
1200 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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|
1201 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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|
1202 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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|
1203 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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|
1204 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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|
1205 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
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|
1206 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
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|
1207 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
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|
1208 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
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|
1209 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
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|
1210 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
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|
1211 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
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|
1212 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
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|
1213 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
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|
1214 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
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|
1215 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
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|
1216 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
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|
1217 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
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|
1218 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
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|
1219 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
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|
|
1220 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1221 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1222 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
|
|
|
1223
|
|
|
1224 /******************* Bit definition for ADC_CR2 register ********************/
|
|
|
1225 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
|
|
|
1226 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
|
|
|
1227 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
|
|
|
1228 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
|
|
|
1229 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
|
|
|
1230 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
|
|
|
1231 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
|
|
|
1232 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1233 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1234 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
1235 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
1236 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
|
|
|
1237 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1238 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1239 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
|
|
|
1240 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
|
|
|
1241 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1242 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1243 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
1244 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
1245 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
|
|
|
1246 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
1247 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
1248 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
|
|
|
1249
|
|
|
1250 /****************** Bit definition for ADC_SMPR1 register *******************/
|
|
|
1251 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
|
|
|
1252 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1253 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1254 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1255 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
|
|
|
1256 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
1257 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
1258 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
1259 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
|
|
|
1260 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
1261 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
1262 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
1263 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
|
|
|
1264 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
1265 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
1266 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
1267 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
|
|
|
1268 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
1269 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
1270 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
1271 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
|
|
|
1272 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1273 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1274 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1275 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
|
|
|
1276 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
1277 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
1278 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
|
|
|
1279 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
|
|
|
1280 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
1281 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
1282 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
1283 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
|
|
|
1284 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1285 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1286 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
1287
|
|
|
1288 /****************** Bit definition for ADC_SMPR2 register *******************/
|
|
|
1289 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
|
|
|
1290 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1291 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1292 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1293 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
|
|
|
1294 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
1295 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
1296 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
1297 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
|
|
|
1298 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
1299 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
1300 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
1301 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
|
|
|
1302 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
1303 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
1304 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
1305 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
|
|
|
1306 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
|
|
|
1307 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
|
|
|
1308 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
|
|
|
1309 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
|
|
|
1310 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1311 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1312 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1313 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
|
|
|
1314 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
1315 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
1316 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
|
|
|
1317 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
|
|
|
1318 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
1319 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
1320 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
1321 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
|
|
|
1322 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1323 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1324 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
1325 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
|
|
|
1326 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
|
|
|
1327 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
|
|
|
1328 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
|
|
|
1329
|
|
|
1330 /****************** Bit definition for ADC_JOFR1 register *******************/
|
|
|
1331 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
|
|
|
1332
|
|
|
1333 /****************** Bit definition for ADC_JOFR2 register *******************/
|
|
|
1334 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
|
|
|
1335
|
|
|
1336 /****************** Bit definition for ADC_JOFR3 register *******************/
|
|
|
1337 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
|
|
|
1338
|
|
|
1339 /****************** Bit definition for ADC_JOFR4 register *******************/
|
|
|
1340 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
|
|
|
1341
|
|
|
1342 /******************* Bit definition for ADC_HTR register ********************/
|
|
|
1343 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
|
|
|
1344
|
|
|
1345 /******************* Bit definition for ADC_LTR register ********************/
|
|
|
1346 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
|
|
|
1347
|
|
|
1348 /******************* Bit definition for ADC_SQR1 register *******************/
|
|
|
1349 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
|
|
|
1350 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1351 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1352 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1353 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1354 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1355 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
|
|
|
1356 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1357 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1358 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1359 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1360 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1361 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
|
|
|
1362 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1363 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1364 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1365 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1366 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1367 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
|
|
|
1368 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1369 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1370 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1371 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1372 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1373 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
|
|
|
1374 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1375 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1376 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1377 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1378
|
|
|
1379 /******************* Bit definition for ADC_SQR2 register *******************/
|
|
|
1380 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
|
|
|
1381 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1382 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1383 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1384 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1385 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1386 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
|
|
|
1387 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1388 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1389 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1390 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1391 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1392 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
|
|
|
1393 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1394 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1395 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1396 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1397 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1398 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
|
|
|
1399 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1400 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1401 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1402 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1403 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1404 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
|
|
|
1405 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1406 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1407 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1408 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1409 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
|
|
1410 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
|
|
|
1411 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1412 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1413 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1414 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1415 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
|
1416
|
|
|
1417 /******************* Bit definition for ADC_SQR3 register *******************/
|
|
|
1418 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
|
|
|
1419 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1420 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1421 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1422 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1423 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1424 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
|
|
|
1425 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1426 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1427 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1428 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1429 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1430 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
|
|
|
1431 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1432 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1433 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1434 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1435 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1436 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
|
|
|
1437 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1438 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1439 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1440 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1441 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1442 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
|
|
|
1443 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1444 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1445 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1446 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
1447 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
|
|
|
1448 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
|
|
|
1449 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
|
|
|
1450 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
|
|
|
1451 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
|
|
|
1452 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
|
|
|
1453 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
|
|
|
1454
|
|
|
1455 /******************* Bit definition for ADC_JSQR register *******************/
|
|
|
1456 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
|
|
|
1457 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1458 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1459 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1460 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1461 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1462 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
|
|
|
1463 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
|
|
|
1464 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
|
|
|
1465 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
|
|
|
1466 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
|
|
|
1467 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
|
|
|
1468 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
|
|
|
1469 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
1470 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
1471 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
1472 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
1473 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
|
|
|
1474 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
|
|
|
1475 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
1476 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
1477 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
|
|
|
1478 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
|
|
|
1479 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
|
|
|
1480 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
|
|
|
1481 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1482 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1483
|
|
|
1484 /******************* Bit definition for ADC_JDR1 register *******************/
|
|
|
1485 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1486
|
|
|
1487 /******************* Bit definition for ADC_JDR2 register *******************/
|
|
|
1488 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1489
|
|
|
1490 /******************* Bit definition for ADC_JDR3 register *******************/
|
|
|
1491 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1492
|
|
|
1493 /******************* Bit definition for ADC_JDR4 register *******************/
|
|
|
1494 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
|
|
|
1495
|
|
|
1496 /******************** Bit definition for ADC_DR register ********************/
|
|
|
1497 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
|
|
|
1498 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
|
|
|
1499
|
|
|
1500 /******************* Bit definition for ADC_CSR register ********************/
|
|
|
1501 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
|
|
|
1502 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
|
|
|
1503 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
|
|
|
1504 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
|
|
|
1505 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
|
|
|
1506 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
|
|
|
1507 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
|
|
|
1508 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
|
|
|
1509 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
|
|
|
1510 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
|
|
|
1511 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
|
|
|
1512 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
|
|
|
1513 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
|
|
|
1514 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
|
|
|
1515 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
|
|
|
1516 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
|
|
|
1517 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
|
|
|
1518 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
|
|
|
1519
|
|
|
1520 /******************* Bit definition for ADC_CCR register ********************/
|
|
|
1521 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
|
|
|
1522 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
1523 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
1524 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
1525 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
1526 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
1527 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
|
|
|
1528 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
1529 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
1530 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
1531 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
1532 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
|
|
|
1533 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
|
|
|
1534 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
1535 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
1536 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
|
|
|
1537 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1538 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1539 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
|
|
|
1540 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
|
|
|
1541
|
|
|
1542 /******************* Bit definition for ADC_CDR register ********************/
|
|
|
1543 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
|
|
|
1544 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
|
|
|
1545
|
|
|
1546 /******************************************************************************/
|
|
|
1547 /* */
|
|
|
1548 /* Controller Area Network */
|
|
|
1549 /* */
|
|
|
1550 /******************************************************************************/
|
|
|
1551 /*!<CAN control and status registers */
|
|
|
1552 /******************* Bit definition for CAN_MCR register ********************/
|
|
|
1553 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
|
|
|
1554 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
|
|
|
1555 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
|
|
|
1556 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
|
|
|
1557 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
|
|
|
1558 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
|
|
|
1559 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
|
|
|
1560 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
|
|
|
1561 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
|
|
|
1562 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
|
|
|
1563 /******************* Bit definition for CAN_MSR register ********************/
|
|
|
1564 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
|
|
|
1565 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
|
|
|
1566 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
|
|
|
1567 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
|
|
|
1568 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
|
|
|
1569 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
|
|
|
1570 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
|
|
|
1571 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
|
|
|
1572 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
|
|
|
1573
|
|
|
1574 /******************* Bit definition for CAN_TSR register ********************/
|
|
|
1575 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
|
|
|
1576 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
|
|
|
1577 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
|
|
|
1578 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
|
|
|
1579 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
|
|
|
1580 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
|
|
|
1581 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
|
|
|
1582 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
|
|
|
1583 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
|
|
|
1584 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
|
|
|
1585 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
|
|
|
1586 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
|
|
|
1587 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
|
|
|
1588 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
|
|
|
1589 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
|
|
|
1590 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
|
|
|
1591
|
|
|
1592 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
|
|
|
1593 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
|
|
|
1594 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
|
|
|
1595 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
|
|
|
1596
|
|
|
1597 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
|
|
|
1598 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
|
|
|
1599 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
|
|
|
1600 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
|
|
|
1601
|
|
|
1602 /******************* Bit definition for CAN_RF0R register *******************/
|
|
|
1603 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
|
|
|
1604 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
|
|
|
1605 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
|
|
|
1606 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
|
|
|
1607
|
|
|
1608 /******************* Bit definition for CAN_RF1R register *******************/
|
|
|
1609 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
|
|
|
1610 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
|
|
|
1611 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
|
|
|
1612 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
|
|
|
1613
|
|
|
1614 /******************** Bit definition for CAN_IER register *******************/
|
|
|
1615 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
|
|
|
1616 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1617 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
|
|
|
1618 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1619 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
|
|
|
1620 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
|
|
|
1621 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
|
|
|
1622 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
|
|
|
1623 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
|
|
|
1624 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
|
|
|
1625 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
|
|
|
1626 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
|
|
|
1627 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
|
|
|
1628 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
|
|
|
1629 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
|
|
|
1630 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
|
|
|
1631 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
|
|
|
1632 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
|
|
|
1633 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
|
|
|
1634
|
|
|
1635
|
|
|
1636 /******************** Bit definition for CAN_ESR register *******************/
|
|
|
1637 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
|
|
|
1638 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
|
|
|
1639 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
|
|
|
1640
|
|
|
1641 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
|
|
|
1642 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
1643 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
1644 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
1645
|
|
|
1646 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
|
|
|
1647 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
|
|
|
1648
|
|
|
1649 /******************* Bit definition for CAN_BTR register ********************/
|
|
|
1650 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
|
|
|
1651 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
|
|
|
1652 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
1653 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
1654 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
1655 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
1656 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
|
|
|
1657 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
1658 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
1659 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
1660 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
|
|
|
1661 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
1662 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
1663 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
|
|
|
1664 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
|
|
|
1665
|
|
|
1666
|
|
|
1667 /*!<Mailbox registers */
|
|
|
1668 /****************** Bit definition for CAN_TI0R register ********************/
|
|
|
1669 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
|
|
1670 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1671 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1672 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
|
|
1673 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1674
|
|
|
1675 /****************** Bit definition for CAN_TDT0R register *******************/
|
|
|
1676 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1677 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
|
|
1678 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1679
|
|
|
1680 /****************** Bit definition for CAN_TDL0R register *******************/
|
|
|
1681 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1682 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1683 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1684 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1685
|
|
|
1686 /****************** Bit definition for CAN_TDH0R register *******************/
|
|
|
1687 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1688 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
1689 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1690 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1691
|
|
|
1692 /******************* Bit definition for CAN_TI1R register *******************/
|
|
|
1693 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
|
|
1694 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1695 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1696 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
|
|
1697 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1698
|
|
|
1699 /******************* Bit definition for CAN_TDT1R register ******************/
|
|
|
1700 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1701 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
|
|
1702 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1703
|
|
|
1704 /******************* Bit definition for CAN_TDL1R register ******************/
|
|
|
1705 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1706 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1707 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1708 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1709
|
|
|
1710 /******************* Bit definition for CAN_TDH1R register ******************/
|
|
|
1711 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1712 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
1713 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1714 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1715
|
|
|
1716 /******************* Bit definition for CAN_TI2R register *******************/
|
|
|
1717 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
|
|
|
1718 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1719 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1720 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
|
|
1721 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1722
|
|
|
1723 /******************* Bit definition for CAN_TDT2R register ******************/
|
|
|
1724 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1725 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
|
|
|
1726 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1727
|
|
|
1728 /******************* Bit definition for CAN_TDL2R register ******************/
|
|
|
1729 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1730 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1731 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1732 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1733
|
|
|
1734 /******************* Bit definition for CAN_TDH2R register ******************/
|
|
|
1735 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1736 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
1737 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1738 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1739
|
|
|
1740 /******************* Bit definition for CAN_RI0R register *******************/
|
|
|
1741 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1742 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1743 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
|
|
|
1744 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1745
|
|
|
1746 /******************* Bit definition for CAN_RDT0R register ******************/
|
|
|
1747 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1748 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
|
|
1749 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1750
|
|
|
1751 /******************* Bit definition for CAN_RDL0R register ******************/
|
|
|
1752 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1753 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1754 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1755 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1756
|
|
|
1757 /******************* Bit definition for CAN_RDH0R register ******************/
|
|
|
1758 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1759 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
1760 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1761 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1762
|
|
|
1763 /******************* Bit definition for CAN_RI1R register *******************/
|
|
|
1764 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
|
|
|
1765 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
|
|
|
1766 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
|
|
|
1767 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
|
|
|
1768
|
|
|
1769 /******************* Bit definition for CAN_RDT1R register ******************/
|
|
|
1770 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
|
|
|
1771 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
|
|
|
1772 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
|
|
|
1773
|
|
|
1774 /******************* Bit definition for CAN_RDL1R register ******************/
|
|
|
1775 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
|
|
|
1776 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
|
|
|
1777 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
|
|
|
1778 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
|
|
|
1779
|
|
|
1780 /******************* Bit definition for CAN_RDH1R register ******************/
|
|
|
1781 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
|
|
|
1782 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
|
|
|
1783 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
|
|
|
1784 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
|
|
|
1785
|
|
|
1786 /*!<CAN filter registers */
|
|
|
1787 /******************* Bit definition for CAN_FMR register ********************/
|
|
|
1788 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
|
|
|
1789 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
|
|
|
1790
|
|
|
1791 /******************* Bit definition for CAN_FM1R register *******************/
|
|
|
1792 #define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
|
|
|
1793 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
|
|
|
1794 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
|
|
|
1795 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
|
|
|
1796 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
|
|
|
1797 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
|
|
|
1798 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
|
|
|
1799 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
|
|
|
1800 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
|
|
|
1801 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
|
|
|
1802 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
|
|
|
1803 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
|
|
|
1804 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
|
|
|
1805 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
|
|
|
1806 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
|
|
|
1807 #define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
|
|
|
1808 #define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
|
|
|
1809 #define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
|
|
|
1810 #define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
|
|
|
1811 #define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
|
|
|
1812 #define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
|
|
|
1813 #define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
|
|
|
1814 #define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
|
|
|
1815 #define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
|
|
|
1816 #define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
|
|
|
1817 #define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
|
|
|
1818 #define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
|
|
|
1819 #define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
|
|
|
1820 #define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
|
|
|
1821
|
|
|
1822 /******************* Bit definition for CAN_FS1R register *******************/
|
|
|
1823 #define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
|
|
|
1824 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
|
|
|
1825 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
|
|
|
1826 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
|
|
|
1827 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
|
|
|
1828 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
|
|
|
1829 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
|
|
|
1830 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
|
|
|
1831 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
|
|
|
1832 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
|
|
|
1833 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
|
|
|
1834 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
|
|
|
1835 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
|
|
|
1836 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
|
|
|
1837 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
|
|
|
1838 #define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
|
|
|
1839 #define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
|
|
|
1840 #define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
|
|
|
1841 #define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
|
|
|
1842 #define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
|
|
|
1843 #define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
|
|
|
1844 #define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
|
|
|
1845 #define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
|
|
|
1846 #define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
|
|
|
1847 #define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
|
|
|
1848 #define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
|
|
|
1849 #define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
|
|
|
1850 #define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
|
|
|
1851 #define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
|
|
|
1852
|
|
|
1853 /****************** Bit definition for CAN_FFA1R register *******************/
|
|
|
1854 #define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
|
|
|
1855 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
|
|
|
1856 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
|
|
|
1857 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
|
|
|
1858 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
|
|
|
1859 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
|
|
|
1860 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
|
|
|
1861 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
|
|
|
1862 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
|
|
|
1863 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
|
|
|
1864 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
|
|
|
1865 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
|
|
|
1866 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
|
|
|
1867 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
|
|
|
1868 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
|
|
|
1869 #define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
|
|
|
1870 #define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
|
|
|
1871 #define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
|
|
|
1872 #define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
|
|
|
1873 #define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
|
|
|
1874 #define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
|
|
|
1875 #define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
|
|
|
1876 #define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
|
|
|
1877 #define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
|
|
|
1878 #define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
|
|
|
1879 #define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
|
|
|
1880 #define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
|
|
|
1881 #define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
|
|
|
1882 #define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
|
|
|
1883
|
|
|
1884 /******************* Bit definition for CAN_FA1R register *******************/
|
|
|
1885 #define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
|
|
|
1886 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
|
|
|
1887 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
|
|
|
1888 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
|
|
|
1889 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
|
|
|
1890 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
|
|
|
1891 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
|
|
|
1892 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
|
|
|
1893 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
|
|
|
1894 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
|
|
|
1895 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
|
|
|
1896 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
|
|
|
1897 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
|
|
|
1898 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
|
|
|
1899 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
|
|
|
1900 #define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
|
|
|
1901 #define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
|
|
|
1902 #define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
|
|
|
1903 #define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
|
|
|
1904 #define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
|
|
|
1905 #define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
|
|
|
1906 #define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
|
|
|
1907 #define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
|
|
|
1908 #define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
|
|
|
1909 #define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
|
|
|
1910 #define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
|
|
|
1911 #define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
|
|
|
1912 #define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
|
|
|
1913 #define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
|
|
|
1914
|
|
|
1915 /******************* Bit definition for CAN_F0R1 register *******************/
|
|
|
1916 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
1917 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
1918 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
1919 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
1920 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
1921 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
1922 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
1923 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
1924 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
1925 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
1926 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
1927 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
1928 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
1929 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
1930 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
1931 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
1932 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
1933 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
1934 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
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|
|
1935 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
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|
|
1936 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
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|
|
1937 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
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|
|
1938 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
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|
|
1939 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
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|
|
1940 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
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|
|
1941 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
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|
|
1942 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
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|
|
1943 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
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|
|
1944 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
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|
|
1945 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
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|
|
1946 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
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|
|
1947 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
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|
|
1948
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|
|
1949 /******************* Bit definition for CAN_F1R1 register *******************/
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|
|
1950 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
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|
|
1951 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
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|
|
1952 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
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|
|
1953 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
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|
|
1954 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
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|
|
1955 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
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|
|
1956 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
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|
|
1957 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
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|
|
1958 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
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|
|
1959 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
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|
1960 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
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|
1961 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
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|
|
1962 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
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|
1963 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
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|
1964 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
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|
1965 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
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1966 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
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|
1967 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
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|
1968 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
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|
1969 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
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|
1970 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
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|
1971 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
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|
1972 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
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|
1973 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
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1974 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
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|
1975 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
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|
1976 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
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|
1977 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
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|
1978 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
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|
1979 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
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|
1980 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
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|
|
1981 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
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|
|
1982
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|
1983 /******************* Bit definition for CAN_F2R1 register *******************/
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|
|
1984 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
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|
1985 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
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|
1986 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
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|
|
1987 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
1988 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
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|
|
1989 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
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|
|
1990 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
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|
|
1991 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
1992 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
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|
|
1993 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
1994 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
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|
|
1995 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
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|
|
1996 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
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|
|
1997 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
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|
|
1998 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
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|
|
1999 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
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|
|
2000 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
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|
|
2001 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2002 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2003 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2004 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2005 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2006 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2007 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2008 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2009 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2010 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2011 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2012 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2013 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2014 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2015 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2016
|
|
|
2017 /******************* Bit definition for CAN_F3R1 register *******************/
|
|
|
2018 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2019 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2020 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2021 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2022 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2023 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2024 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2025 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2026 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2027 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2028 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2029 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2030 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2031 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2032 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2033 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2034 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2035 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2036 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2037 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2038 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2039 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2040 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2041 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2042 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2043 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2044 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2045 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2046 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2047 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2048 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2049 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2050
|
|
|
2051 /******************* Bit definition for CAN_F4R1 register *******************/
|
|
|
2052 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2053 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2054 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2055 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2056 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2057 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2058 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2059 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2060 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2061 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2062 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2063 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2064 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2065 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2066 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2067 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2068 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2069 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2070 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2071 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2072 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2073 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2074 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2075 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2076 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2077 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2078 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2079 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2080 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2081 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2082 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2083 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2084
|
|
|
2085 /******************* Bit definition for CAN_F5R1 register *******************/
|
|
|
2086 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2087 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2088 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2089 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2090 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2091 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2092 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2093 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2094 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2095 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2096 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2097 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2098 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2099 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2100 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2101 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2102 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2103 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2104 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2105 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2106 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2107 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2108 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2109 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2110 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2111 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2112 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2113 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2114 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2115 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2116 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2117 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2118
|
|
|
2119 /******************* Bit definition for CAN_F6R1 register *******************/
|
|
|
2120 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2121 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2122 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2123 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2124 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2125 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2126 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2127 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2128 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2129 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2130 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2131 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2132 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2133 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2134 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2135 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2136 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2137 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2138 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2139 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2140 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2141 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2142 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2143 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2144 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2145 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2146 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2147 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2148 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2149 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2150 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2151 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2152
|
|
|
2153 /******************* Bit definition for CAN_F7R1 register *******************/
|
|
|
2154 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2155 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2156 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2157 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2158 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2159 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2160 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2161 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2162 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2163 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2164 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2165 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2166 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2167 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2168 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2169 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2170 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2171 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2172 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2173 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2174 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2175 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2176 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2177 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2178 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2179 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2180 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2181 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2182 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2183 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2184 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2185 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2186
|
|
|
2187 /******************* Bit definition for CAN_F8R1 register *******************/
|
|
|
2188 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2189 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2190 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2191 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2192 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2193 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2194 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2195 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2196 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2197 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2198 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2199 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2200 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2201 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2202 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2203 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2204 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2205 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2206 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2207 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2208 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2209 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2210 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2211 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2212 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2213 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2214 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2215 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2216 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2217 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2218 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2219 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2220
|
|
|
2221 /******************* Bit definition for CAN_F9R1 register *******************/
|
|
|
2222 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2223 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2224 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2225 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2226 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2227 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2228 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2229 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2230 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2231 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2232 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2233 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2234 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2235 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2236 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2237 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2238 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2239 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2240 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2241 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2242 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2243 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2244 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2245 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2246 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2247 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2248 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2249 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2250 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2251 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2252 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2253 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2254
|
|
|
2255 /******************* Bit definition for CAN_F10R1 register ******************/
|
|
|
2256 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2257 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2258 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2259 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2260 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2261 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2262 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2263 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2264 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2265 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2266 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2267 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2268 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2269 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2270 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2271 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2272 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2273 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2274 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2275 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2276 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2277 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2278 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2279 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2280 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2281 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2282 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2283 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2284 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2285 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2286 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2287 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2288
|
|
|
2289 /******************* Bit definition for CAN_F11R1 register ******************/
|
|
|
2290 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2291 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2292 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2293 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2294 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2295 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2296 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2297 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2298 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2299 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2300 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2301 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2302 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2303 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2304 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2305 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2306 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2307 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2308 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2309 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2310 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2311 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2312 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2313 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2314 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2315 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2316 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2317 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2318 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2319 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2320 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2321 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2322
|
|
|
2323 /******************* Bit definition for CAN_F12R1 register ******************/
|
|
|
2324 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2325 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2326 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2327 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2328 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2329 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2330 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2331 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2332 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2333 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2334 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2335 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2336 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2337 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2338 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2339 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2340 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2341 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2342 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2343 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2344 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2345 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2346 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2347 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2348 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2349 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2350 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2351 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2352 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2353 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2354 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2355 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2356
|
|
|
2357 /******************* Bit definition for CAN_F13R1 register ******************/
|
|
|
2358 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2359 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2360 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2361 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2362 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2363 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2364 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2365 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2366 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2367 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2368 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2369 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2370 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2371 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2372 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2373 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2374 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2375 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2376 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2377 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2378 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2379 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2380 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2381 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2382 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2383 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2384 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2385 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2386 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2387 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2388 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2389 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2390
|
|
|
2391 /******************* Bit definition for CAN_F0R2 register *******************/
|
|
|
2392 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2393 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2394 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2395 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2396 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2397 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2398 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2399 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2400 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2401 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2402 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2403 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2404 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2405 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2406 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2407 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2408 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2409 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2410 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2411 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2412 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2413 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2414 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2415 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2416 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2417 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2418 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2419 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2420 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2421 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2422 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2423 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2424
|
|
|
2425 /******************* Bit definition for CAN_F1R2 register *******************/
|
|
|
2426 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2427 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2428 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2429 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2430 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2431 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2432 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2433 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2434 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2435 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2436 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2437 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2438 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2439 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2440 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2441 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2442 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2443 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2444 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2445 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2446 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2447 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2448 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2449 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2450 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2451 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2452 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2453 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2454 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2455 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2456 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2457 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2458
|
|
|
2459 /******************* Bit definition for CAN_F2R2 register *******************/
|
|
|
2460 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2461 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2462 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2463 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2464 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2465 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2466 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2467 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2468 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2469 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2470 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2471 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2472 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2473 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2474 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2475 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2476 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2477 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2478 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2479 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2480 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2481 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2482 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2483 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2484 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2485 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2486 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2487 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2488 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2489 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2490 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2491 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2492
|
|
|
2493 /******************* Bit definition for CAN_F3R2 register *******************/
|
|
|
2494 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2495 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2496 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2497 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2498 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2499 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2500 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2501 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2502 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2503 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2504 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2505 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2506 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2507 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2508 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2509 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2510 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2511 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2512 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2513 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2514 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2515 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2516 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2517 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2518 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2519 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2520 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2521 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2522 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2523 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2524 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2525 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2526
|
|
|
2527 /******************* Bit definition for CAN_F4R2 register *******************/
|
|
|
2528 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2529 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2530 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2531 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2532 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2533 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2534 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2535 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2536 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2537 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2538 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2539 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2540 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2541 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2542 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2543 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2544 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2545 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2546 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2547 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2548 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2549 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2550 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2551 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2552 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2553 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2554 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2555 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2556 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2557 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2558 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2559 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2560
|
|
|
2561 /******************* Bit definition for CAN_F5R2 register *******************/
|
|
|
2562 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2563 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2564 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2565 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2566 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2567 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2568 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2569 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2570 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2571 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2572 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2573 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2574 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2575 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2576 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2577 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2578 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2579 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2580 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2581 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2582 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2583 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2584 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2585 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2586 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2587 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2588 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2589 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2590 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2591 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2592 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2593 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2594
|
|
|
2595 /******************* Bit definition for CAN_F6R2 register *******************/
|
|
|
2596 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2597 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2598 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2599 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2600 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2601 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2602 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2603 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2604 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2605 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2606 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2607 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2608 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2609 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2610 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2611 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2612 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2613 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2614 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2615 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2616 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2617 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2618 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2619 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2620 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2621 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2622 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2623 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2624 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2625 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2626 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2627 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2628
|
|
|
2629 /******************* Bit definition for CAN_F7R2 register *******************/
|
|
|
2630 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2631 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2632 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2633 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2634 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2635 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2636 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2637 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2638 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2639 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2640 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2641 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2642 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2643 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2644 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2645 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2646 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2647 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2648 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2649 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2650 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2651 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2652 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2653 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2654 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2655 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2656 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2657 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2658 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2659 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2660 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2661 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2662
|
|
|
2663 /******************* Bit definition for CAN_F8R2 register *******************/
|
|
|
2664 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2665 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2666 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2667 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2668 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2669 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2670 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2671 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2672 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2673 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2674 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2675 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2676 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2677 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2678 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2679 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2680 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2681 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2682 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2683 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2684 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2685 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2686 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2687 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2688 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2689 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2690 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2691 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2692 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2693 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2694 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2695 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2696
|
|
|
2697 /******************* Bit definition for CAN_F9R2 register *******************/
|
|
|
2698 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2699 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2700 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2701 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2702 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2703 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2704 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2705 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2706 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2707 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2708 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2709 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2710 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2711 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2712 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2713 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2714 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2715 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2716 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2717 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2718 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2719 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2720 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2721 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2722 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2723 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2724 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2725 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2726 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2727 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2728 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2729 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2730
|
|
|
2731 /******************* Bit definition for CAN_F10R2 register ******************/
|
|
|
2732 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2733 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2734 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2735 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2736 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2737 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2738 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2739 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2740 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2741 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2742 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2743 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2744 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2745 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2746 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2747 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2748 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2749 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2750 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2751 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2752 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2753 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2754 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2755 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2756 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2757 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2758 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2759 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2760 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2761 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2762 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2763 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2764
|
|
|
2765 /******************* Bit definition for CAN_F11R2 register ******************/
|
|
|
2766 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2767 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2768 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2769 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2770 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2771 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2772 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2773 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2774 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2775 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2776 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2777 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2778 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2779 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2780 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2781 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2782 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2783 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2784 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2785 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2786 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2787 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2788 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2789 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2790 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2791 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2792 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2793 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2794 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2795 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2796 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2797 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2798
|
|
|
2799 /******************* Bit definition for CAN_F12R2 register ******************/
|
|
|
2800 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2801 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2802 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2803 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2804 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2805 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2806 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2807 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2808 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2809 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2810 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2811 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2812 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2813 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2814 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2815 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2816 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2817 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2818 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2819 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2820 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2821 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2822 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2823 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2824 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2825 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2826 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2827 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2828 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2829 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2830 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2831 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2832
|
|
|
2833 /******************* Bit definition for CAN_F13R2 register ******************/
|
|
|
2834 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
|
|
|
2835 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
|
|
|
2836 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
|
|
|
2837 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
|
|
|
2838 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
|
|
|
2839 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
|
|
|
2840 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
|
|
|
2841 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
|
|
|
2842 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
|
|
|
2843 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
|
|
|
2844 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
|
|
|
2845 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
|
|
|
2846 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
|
|
|
2847 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
|
|
|
2848 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
|
|
|
2849 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
|
|
|
2850 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
|
|
|
2851 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
|
|
|
2852 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
|
|
|
2853 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
|
|
|
2854 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
|
|
|
2855 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
|
|
|
2856 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
|
|
|
2857 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
|
|
|
2858 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
|
|
|
2859 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
|
|
|
2860 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
|
|
|
2861 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
|
|
|
2862 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
|
|
|
2863 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
|
|
|
2864 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
|
|
|
2865 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
|
|
|
2866
|
|
|
2867 /******************************************************************************/
|
|
|
2868 /* */
|
|
|
2869 /* CRC calculation unit */
|
|
|
2870 /* */
|
|
|
2871 /******************************************************************************/
|
|
|
2872 /******************* Bit definition for CRC_DR register *********************/
|
|
|
2873 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
|
|
|
2874
|
|
|
2875
|
|
|
2876 /******************* Bit definition for CRC_IDR register ********************/
|
|
|
2877 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
|
|
|
2878
|
|
|
2879
|
|
|
2880 /******************** Bit definition for CRC_CR register ********************/
|
|
|
2881 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
|
|
|
2882
|
|
|
2883
|
|
|
2884 /******************************************************************************/
|
|
|
2885 /* */
|
|
|
2886 /* Digital to Analog Converter */
|
|
|
2887 /* */
|
|
|
2888 /******************************************************************************/
|
|
|
2889 /******************** Bit definition for DAC_CR register ********************/
|
|
|
2890 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
|
|
|
2891 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
|
|
|
2892 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
|
|
|
2893
|
|
|
2894 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
|
|
|
2895 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
2896 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
2897 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
2898
|
|
|
2899 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
|
|
|
2900 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
2901 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
2902
|
|
|
2903 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
|
|
|
2904 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
2905 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
2906 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
2907 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
2908
|
|
|
2909 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
|
|
|
2910 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
|
|
|
2911 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
|
|
|
2912 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
|
|
|
2913
|
|
|
2914 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
|
|
|
2915 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
|
|
|
2916 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
|
|
|
2917 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
|
|
|
2918
|
|
|
2919 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
|
|
|
2920 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
2921 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
2922
|
|
|
2923 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
|
|
|
2924 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
2925 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
2926 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
2927 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
2928
|
|
|
2929 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
|
|
|
2930
|
|
|
2931 /***************** Bit definition for DAC_SWTRIGR register ******************/
|
|
|
2932 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
|
|
|
2933 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
|
|
|
2934
|
|
|
2935 /***************** Bit definition for DAC_DHR12R1 register ******************/
|
|
|
2936 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
2937
|
|
|
2938 /***************** Bit definition for DAC_DHR12L1 register ******************/
|
|
|
2939 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
2940
|
|
|
2941 /****************** Bit definition for DAC_DHR8R1 register ******************/
|
|
|
2942 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
2943
|
|
|
2944 /***************** Bit definition for DAC_DHR12R2 register ******************/
|
|
|
2945 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
2946
|
|
|
2947 /***************** Bit definition for DAC_DHR12L2 register ******************/
|
|
|
2948 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
2949
|
|
|
2950 /****************** Bit definition for DAC_DHR8R2 register ******************/
|
|
|
2951 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
2952
|
|
|
2953 /***************** Bit definition for DAC_DHR12RD register ******************/
|
|
|
2954 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
|
|
|
2955 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
|
|
|
2956
|
|
|
2957 /***************** Bit definition for DAC_DHR12LD register ******************/
|
|
|
2958 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
|
|
|
2959 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
|
|
|
2960
|
|
|
2961 /****************** Bit definition for DAC_DHR8RD register ******************/
|
|
|
2962 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
|
|
|
2963 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
|
|
|
2964
|
|
|
2965 /******************* Bit definition for DAC_DOR1 register *******************/
|
|
|
2966 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
|
|
|
2967
|
|
|
2968 /******************* Bit definition for DAC_DOR2 register *******************/
|
|
|
2969 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
|
|
|
2970
|
|
|
2971 /******************** Bit definition for DAC_SR register ********************/
|
|
|
2972 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
|
|
|
2973 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
|
|
|
2974
|
|
|
2975 /******************************************************************************/
|
|
|
2976 /* */
|
|
|
2977 /* Debug MCU */
|
|
|
2978 /* */
|
|
|
2979 /******************************************************************************/
|
|
|
2980
|
|
|
2981 /******************************************************************************/
|
|
|
2982 /* */
|
|
|
2983 /* DCMI */
|
|
|
2984 /* */
|
|
|
2985 /******************************************************************************/
|
|
|
2986 /******************** Bits definition for DCMI_CR register ******************/
|
|
|
2987 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
|
|
|
2988 #define DCMI_CR_CM ((uint32_t)0x00000002)
|
|
|
2989 #define DCMI_CR_CROP ((uint32_t)0x00000004)
|
|
|
2990 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
|
|
|
2991 #define DCMI_CR_ESS ((uint32_t)0x00000010)
|
|
|
2992 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
|
|
|
2993 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
|
|
|
2994 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
|
|
|
2995 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
|
|
|
2996 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
|
|
|
2997 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
|
|
|
2998 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
|
|
|
2999 #define DCMI_CR_CRE ((uint32_t)0x00001000)
|
|
|
3000 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
|
|
|
3001
|
|
|
3002 /******************** Bits definition for DCMI_SR register ******************/
|
|
|
3003 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
|
|
|
3004 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
|
|
|
3005 #define DCMI_SR_FNE ((uint32_t)0x00000004)
|
|
|
3006
|
|
|
3007 /******************** Bits definition for DCMI_RISR register ****************/
|
|
|
3008 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
|
|
|
3009 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
|
|
|
3010 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
|
|
|
3011 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
|
|
|
3012 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
|
|
|
3013
|
|
|
3014 /******************** Bits definition for DCMI_IER register *****************/
|
|
|
3015 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
|
|
|
3016 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
|
|
|
3017 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
|
|
|
3018 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
|
|
|
3019 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
|
|
|
3020
|
|
|
3021 /******************** Bits definition for DCMI_MISR register ****************/
|
|
|
3022 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
|
|
|
3023 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
|
|
|
3024 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
|
|
|
3025 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
|
|
|
3026 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
|
|
|
3027
|
|
|
3028 /******************** Bits definition for DCMI_ICR register *****************/
|
|
|
3029 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
|
|
|
3030 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
|
|
|
3031 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
|
|
|
3032 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
|
|
|
3033 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
|
|
|
3034
|
|
|
3035 /******************************************************************************/
|
|
|
3036 /* */
|
|
|
3037 /* DMA Controller */
|
|
|
3038 /* */
|
|
|
3039 /******************************************************************************/
|
|
|
3040 /******************** Bits definition for DMA_SxCR register *****************/
|
|
|
3041 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
|
|
|
3042 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
|
|
|
3043 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
|
|
|
3044 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
|
|
|
3045 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
|
|
|
3046 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
|
|
|
3047 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
|
|
|
3048 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
|
|
|
3049 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
|
|
|
3050 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
|
|
|
3051 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
|
|
|
3052 #define DMA_SxCR_CT ((uint32_t)0x00080000)
|
|
|
3053 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
|
|
|
3054 #define DMA_SxCR_PL ((uint32_t)0x00030000)
|
|
|
3055 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
|
|
|
3056 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
|
|
|
3057 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
|
|
|
3058 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
|
|
|
3059 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
|
|
|
3060 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
|
|
|
3061 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
|
|
|
3062 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
|
|
|
3063 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
|
|
|
3064 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
|
|
|
3065 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
|
|
|
3066 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
|
|
|
3067 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
|
|
|
3068 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
|
|
|
3069 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
|
|
|
3070 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
|
|
|
3071 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
|
|
|
3072 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
|
|
|
3073 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
|
|
|
3074 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
|
|
|
3075 #define DMA_SxCR_EN ((uint32_t)0x00000001)
|
|
|
3076
|
|
|
3077 /******************** Bits definition for DMA_SxCNDTR register **************/
|
|
|
3078 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
|
|
|
3079 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
|
|
|
3080 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
|
|
|
3081 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
|
|
|
3082 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
|
|
|
3083 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
|
|
|
3084 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
|
|
|
3085 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
|
|
|
3086 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
|
|
|
3087 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
|
|
|
3088 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
|
|
|
3089 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
|
|
|
3090 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
|
|
|
3091 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
|
|
|
3092 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
|
|
|
3093 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
|
|
|
3094 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
|
|
|
3095
|
|
|
3096 /******************** Bits definition for DMA_SxFCR register ****************/
|
|
|
3097 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
|
|
|
3098 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
|
|
|
3099 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
|
|
|
3100 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
|
|
|
3101 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
|
|
|
3102 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
|
|
|
3103 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
|
|
|
3104 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
|
|
|
3105 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
|
|
|
3106
|
|
|
3107 /******************** Bits definition for DMA_LISR register *****************/
|
|
|
3108 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
|
|
|
3109 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
|
|
|
3110 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
|
|
|
3111 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
|
|
|
3112 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
|
|
|
3113 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
|
|
|
3114 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
|
|
|
3115 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
|
|
|
3116 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
|
|
|
3117 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
|
|
|
3118 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
|
|
|
3119 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
|
|
|
3120 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
|
|
|
3121 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
|
|
|
3122 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
|
|
|
3123 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
|
|
|
3124 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
|
|
|
3125 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
|
|
|
3126 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
|
|
|
3127 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
|
|
|
3128
|
|
|
3129 /******************** Bits definition for DMA_HISR register *****************/
|
|
|
3130 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
|
|
|
3131 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
|
|
|
3132 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
|
|
|
3133 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
|
|
|
3134 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
|
|
|
3135 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
|
|
|
3136 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
|
|
|
3137 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
|
|
|
3138 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
|
|
|
3139 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
|
|
|
3140 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
|
|
|
3141 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
|
|
|
3142 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
|
|
|
3143 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
|
|
|
3144 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
|
|
|
3145 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
|
|
|
3146 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
|
|
|
3147 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
|
|
|
3148 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
|
|
|
3149 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
|
|
|
3150
|
|
|
3151 /******************** Bits definition for DMA_LIFCR register ****************/
|
|
|
3152 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
|
|
|
3153 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
|
|
|
3154 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
|
|
|
3155 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
|
|
|
3156 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
|
|
|
3157 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
|
|
|
3158 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
|
|
|
3159 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
|
|
|
3160 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
|
|
|
3161 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
|
|
|
3162 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
|
|
|
3163 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
|
|
|
3164 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
|
|
|
3165 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
|
|
|
3166 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
|
|
|
3167 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
|
|
|
3168 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
|
|
|
3169 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
|
|
|
3170 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
|
|
|
3171 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
|
|
|
3172
|
|
|
3173 /******************** Bits definition for DMA_HIFCR register ****************/
|
|
|
3174 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
|
|
|
3175 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
|
|
|
3176 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
|
|
|
3177 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
|
|
|
3178 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
|
|
|
3179 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
|
|
|
3180 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
|
|
|
3181 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
|
|
|
3182 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
|
|
|
3183 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
|
|
|
3184 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
|
|
|
3185 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
|
|
|
3186 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
|
|
|
3187 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
|
|
|
3188 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
|
|
|
3189 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
|
|
|
3190 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
|
|
|
3191 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
|
|
|
3192 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
|
|
|
3193 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
|
|
|
3194
|
|
|
3195
|
|
|
3196 /******************************************************************************/
|
|
|
3197 /* */
|
|
|
3198 /* External Interrupt/Event Controller */
|
|
|
3199 /* */
|
|
|
3200 /******************************************************************************/
|
|
|
3201 /******************* Bit definition for EXTI_IMR register *******************/
|
|
|
3202 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
|
|
|
3203 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
|
|
|
3204 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
|
|
|
3205 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
|
|
|
3206 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
|
|
|
3207 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
|
|
|
3208 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
|
|
|
3209 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
|
|
|
3210 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
|
|
|
3211 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
|
|
|
3212 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
|
|
|
3213 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
|
|
|
3214 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
|
|
|
3215 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
|
|
|
3216 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
|
|
|
3217 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
|
|
|
3218 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
|
|
|
3219 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
|
|
|
3220 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
|
|
|
3221 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
|
|
|
3222
|
|
|
3223 /******************* Bit definition for EXTI_EMR register *******************/
|
|
|
3224 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
|
|
|
3225 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
|
|
|
3226 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
|
|
|
3227 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
|
|
|
3228 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
|
|
|
3229 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
|
|
|
3230 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
|
|
|
3231 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
|
|
|
3232 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
|
|
|
3233 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
|
|
|
3234 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
|
|
|
3235 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
|
|
|
3236 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
|
|
|
3237 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
|
|
|
3238 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
|
|
|
3239 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
|
|
|
3240 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
|
|
|
3241 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
|
|
|
3242 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
|
|
|
3243 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
|
|
|
3244
|
|
|
3245 /****************** Bit definition for EXTI_RTSR register *******************/
|
|
|
3246 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
|
|
|
3247 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
|
|
|
3248 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
|
|
|
3249 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
|
|
|
3250 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
|
|
|
3251 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
|
|
|
3252 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
|
|
|
3253 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
|
|
|
3254 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
|
|
|
3255 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
|
|
|
3256 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
|
|
|
3257 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
|
|
|
3258 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
|
|
|
3259 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
|
|
|
3260 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
|
|
|
3261 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
|
|
|
3262 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
|
|
|
3263 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
|
|
|
3264 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
|
|
|
3265 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
|
|
|
3266
|
|
|
3267 /****************** Bit definition for EXTI_FTSR register *******************/
|
|
|
3268 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
|
|
|
3269 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
|
|
|
3270 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
|
|
|
3271 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
|
|
|
3272 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
|
|
|
3273 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
|
|
|
3274 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
|
|
|
3275 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
|
|
|
3276 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
|
|
|
3277 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
|
|
|
3278 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
|
|
|
3279 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
|
|
|
3280 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
|
|
|
3281 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
|
|
|
3282 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
|
|
|
3283 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
|
|
|
3284 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
|
|
|
3285 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
|
|
|
3286 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
|
|
|
3287 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
|
|
|
3288
|
|
|
3289 /****************** Bit definition for EXTI_SWIER register ******************/
|
|
|
3290 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
|
|
|
3291 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
|
|
|
3292 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
|
|
|
3293 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
|
|
|
3294 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
|
|
|
3295 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
|
|
|
3296 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
|
|
|
3297 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
|
|
|
3298 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
|
|
|
3299 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
|
|
|
3300 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
|
|
|
3301 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
|
|
|
3302 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
|
|
|
3303 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
|
|
|
3304 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
|
|
|
3305 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
|
|
|
3306 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
|
|
|
3307 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
|
|
|
3308 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
|
|
|
3309 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
|
|
|
3310
|
|
|
3311 /******************* Bit definition for EXTI_PR register ********************/
|
|
|
3312 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
|
|
|
3313 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
|
|
|
3314 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
|
|
|
3315 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
|
|
|
3316 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
|
|
|
3317 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
|
|
|
3318 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
|
|
|
3319 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
|
|
|
3320 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
|
|
|
3321 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
|
|
|
3322 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
|
|
|
3323 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
|
|
|
3324 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
|
|
|
3325 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
|
|
|
3326 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
|
|
|
3327 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
|
|
|
3328 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
|
|
|
3329 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
|
|
|
3330 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
|
|
|
3331 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
|
|
|
3332
|
|
|
3333 /******************************************************************************/
|
|
|
3334 /* */
|
|
|
3335 /* FLASH */
|
|
|
3336 /* */
|
|
|
3337 /******************************************************************************/
|
|
|
3338 /******************* Bits definition for FLASH_ACR register *****************/
|
|
|
3339 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
|
|
|
3340 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
|
|
|
3341 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
|
|
|
3342 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
|
|
|
3343 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
|
|
|
3344 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
|
|
|
3345 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
|
|
|
3346 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
|
|
|
3347 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
|
|
|
3348
|
|
|
3349 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
|
|
|
3350 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
|
|
|
3351 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
|
|
|
3352 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
|
|
|
3353 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
|
|
|
3354 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
|
|
|
3355 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
|
|
|
3356
|
|
|
3357 /******************* Bits definition for FLASH_SR register ******************/
|
|
|
3358 #define FLASH_SR_EOP ((uint32_t)0x00000001)
|
|
|
3359 #define FLASH_SR_SOP ((uint32_t)0x00000002)
|
|
|
3360 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
|
|
|
3361 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
|
|
|
3362 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
|
|
|
3363 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
|
|
|
3364 #define FLASH_SR_BSY ((uint32_t)0x00010000)
|
|
|
3365
|
|
|
3366 /******************* Bits definition for FLASH_CR register ******************/
|
|
|
3367 #define FLASH_CR_PG ((uint32_t)0x00000001)
|
|
|
3368 #define FLASH_CR_SER ((uint32_t)0x00000002)
|
|
|
3369 #define FLASH_CR_MER ((uint32_t)0x00000004)
|
|
|
3370 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
|
|
|
3371 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
|
|
|
3372 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
|
|
|
3373 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
|
|
|
3374 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
|
|
|
3375 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
|
|
|
3376 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
|
|
|
3377 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
|
|
|
3378 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
|
|
|
3379 #define FLASH_CR_STRT ((uint32_t)0x00010000)
|
|
|
3380 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
|
|
|
3381 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
|
|
|
3382
|
|
|
3383 /******************* Bits definition for FLASH_OPTCR register ***************/
|
|
|
3384 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
|
|
|
3385 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
|
|
|
3386 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
|
|
|
3387 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
|
|
|
3388 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
|
|
|
3389
|
|
|
3390 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
|
|
|
3391 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
|
|
|
3392 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
|
|
|
3393 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
|
|
|
3394 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
|
|
|
3395 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
|
|
|
3396 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
|
|
|
3397 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
|
|
|
3398 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
|
|
|
3399 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
|
|
|
3400 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
|
|
|
3401 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
|
|
|
3402 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
|
|
|
3403 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
|
|
|
3404 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
|
|
|
3405 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
|
|
|
3406 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
|
|
|
3407 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
|
|
|
3408 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
|
|
|
3409 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
|
|
|
3410 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
|
|
|
3411 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
|
|
|
3412 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
|
|
|
3413 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
|
|
|
3414 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
|
|
|
3415
|
|
|
3416 /****************** Bits definition for FLASH_OPTCR1 register ***************/
|
|
|
3417 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
|
|
|
3418 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
|
|
|
3419 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
|
|
|
3420 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
|
|
|
3421 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
|
|
|
3422 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
|
|
|
3423 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
|
|
|
3424 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
|
|
|
3425 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
|
|
|
3426 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
|
|
|
3427 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
|
|
|
3428 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
|
|
|
3429 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
|
|
|
3430
|
|
|
3431 /******************************************************************************/
|
|
|
3432 /* */
|
|
|
3433 /* Flexible Static Memory Controller */
|
|
|
3434 /* */
|
|
|
3435 /******************************************************************************/
|
|
|
3436 /****************** Bit definition for FSMC_BCR1 register *******************/
|
|
|
3437 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3438 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3439
|
|
|
3440 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3441 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3442 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3443
|
|
|
3444 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3445 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3446 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3447
|
|
|
3448 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3449 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3450 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3451 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3452 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3453 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3454 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3455 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3456 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3457 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3458
|
|
|
3459 /****************** Bit definition for FSMC_BCR2 register *******************/
|
|
|
3460 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3461 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3462
|
|
|
3463 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3464 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3465 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3466
|
|
|
3467 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3468 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3469 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3470
|
|
|
3471 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3472 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3473 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3474 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3475 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3476 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3477 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3478 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3479 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3480 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3481
|
|
|
3482 /****************** Bit definition for FSMC_BCR3 register *******************/
|
|
|
3483 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3484 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3485
|
|
|
3486 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3487 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3488 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3489
|
|
|
3490 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3491 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3492 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3493
|
|
|
3494 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3495 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3496 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3497 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3498 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3499 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3500 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3501 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3502 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3503 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3504
|
|
|
3505 /****************** Bit definition for FSMC_BCR4 register *******************/
|
|
|
3506 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
|
|
|
3507 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
|
|
|
3508
|
|
|
3509 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
|
|
|
3510 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
3511 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
3512
|
|
|
3513 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
|
|
|
3514 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3515 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3516
|
|
|
3517 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
|
|
|
3518 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
|
|
|
3519 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
|
|
|
3520 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
|
|
|
3521 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
|
|
|
3522 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
|
|
|
3523 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
|
|
|
3524 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
|
|
|
3525 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
|
|
|
3526 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
|
|
|
3527
|
|
|
3528 /****************** Bit definition for FSMC_BTR1 register ******************/
|
|
|
3529 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3530 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3531 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3532 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3533 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3534
|
|
|
3535 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3536 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3537 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3538 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3539 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3540
|
|
|
3541 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3542 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3543 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3544 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3545 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3546
|
|
|
3547 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
3548 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3549 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3550 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3551 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3552
|
|
|
3553 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3554 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3555 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3556 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3557 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3558
|
|
|
3559 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3560 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3561 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3562 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3563 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3564
|
|
|
3565 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3566 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3567 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3568
|
|
|
3569 /****************** Bit definition for FSMC_BTR2 register *******************/
|
|
|
3570 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3571 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3572 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3573 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3574 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3575
|
|
|
3576 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3577 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3578 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3579 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3580 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3581
|
|
|
3582 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3583 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3584 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3585 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3586 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3587
|
|
|
3588 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
3589 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3590 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3591 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3592 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3593
|
|
|
3594 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3595 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3596 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3597 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3598 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3599
|
|
|
3600 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3601 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3602 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3603 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3604 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3605
|
|
|
3606 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3607 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3608 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3609
|
|
|
3610 /******************* Bit definition for FSMC_BTR3 register *******************/
|
|
|
3611 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3612 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3613 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3614 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3615 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3616
|
|
|
3617 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3618 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3619 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3620 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3621 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3622
|
|
|
3623 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3624 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3625 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3626 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3627 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3628
|
|
|
3629 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
3630 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3631 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3632 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3633 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3634
|
|
|
3635 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3636 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3637 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3638 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3639 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3640
|
|
|
3641 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3642 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3643 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3644 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3645 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3646
|
|
|
3647 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3648 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3649 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3650
|
|
|
3651 /****************** Bit definition for FSMC_BTR4 register *******************/
|
|
|
3652 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3653 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3654 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3655 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3656 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3657
|
|
|
3658 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3659 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3660 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3661 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3662 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3663
|
|
|
3664 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3665 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3666 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3667 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3668 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3669
|
|
|
3670 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
|
|
|
3671 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3672 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3673 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3674 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3675
|
|
|
3676 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3677 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3678 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3679 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3680 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3681
|
|
|
3682 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3683 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3684 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3685 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3686 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3687
|
|
|
3688 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3689 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3690 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3691
|
|
|
3692 /****************** Bit definition for FSMC_BWTR1 register ******************/
|
|
|
3693 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3694 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3695 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3696 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3697 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3698
|
|
|
3699 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3700 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3701 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3702 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3703 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3704
|
|
|
3705 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3706 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3707 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3708 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3709 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3710
|
|
|
3711 #define FSMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
3712 #define FSMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3713 #define FSMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3714 #define FSMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3715 #define FSMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3716
|
|
|
3717 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3718 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3719 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3720 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3721 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3722
|
|
|
3723 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3724 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3725 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3726 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3727 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3728
|
|
|
3729 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3730 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3731 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3732
|
|
|
3733 /****************** Bit definition for FSMC_BWTR2 register ******************/
|
|
|
3734 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3735 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3736 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3737 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3738 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3739
|
|
|
3740 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3741 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3742 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3743 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3744 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3745
|
|
|
3746 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3747 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3748 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3749 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3750 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3751
|
|
|
3752 #define FSMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
3753 #define FSMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3754 #define FSMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3755 #define FSMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3756 #define FSMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3757
|
|
|
3758 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3759 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3760 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
|
|
|
3761 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3762 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3763
|
|
|
3764 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3765 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3766 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3767 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3768 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3769
|
|
|
3770 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3771 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3772 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3773
|
|
|
3774 /****************** Bit definition for FSMC_BWTR3 register ******************/
|
|
|
3775 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3776 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3777 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3778 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3779 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3780
|
|
|
3781 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3782 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3783 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3784 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3785 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3786
|
|
|
3787 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3788 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3789 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3790 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3791 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3792
|
|
|
3793 #define FSMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
3794 #define FSMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3795 #define FSMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3796 #define FSMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3797 #define FSMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3798
|
|
|
3799 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3800 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3801 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3802 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3803 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3804
|
|
|
3805 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3806 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3807 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3808 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3809 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3810
|
|
|
3811 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3812 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3813 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3814
|
|
|
3815 /****************** Bit definition for FSMC_BWTR4 register ******************/
|
|
|
3816 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
|
|
|
3817 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3818 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3819 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3820 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3821
|
|
|
3822 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
|
|
|
3823 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3824 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3825 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
3826 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
3827
|
|
|
3828 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
|
|
|
3829 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3830 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3831 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3832 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3833
|
|
|
3834 #define FSMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
|
|
|
3835 #define FSMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3836 #define FSMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3837 #define FSMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3838 #define FSMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3839
|
|
|
3840 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
|
|
|
3841 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
3842 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
3843 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
|
|
|
3844 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
|
|
|
3845
|
|
|
3846 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
|
|
|
3847 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
3848 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
3849 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
3850 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
3851
|
|
|
3852 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
|
|
|
3853 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
|
|
|
3854 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
|
|
|
3855
|
|
|
3856 /****************** Bit definition for FSMC_PCR2 register *******************/
|
|
|
3857 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
|
|
3858 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
|
|
3859 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
|
|
3860
|
|
|
3861 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
3862 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3863 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3864
|
|
|
3865 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
|
|
3866
|
|
|
3867 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
3868 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
3869 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
3870 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
3871 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
|
|
3872
|
|
|
3873 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
3874 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
3875 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
3876 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
3877 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
3878
|
|
|
3879 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
|
|
|
3880 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
3881 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
3882 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
3883
|
|
|
3884 /****************** Bit definition for FSMC_PCR3 register *******************/
|
|
|
3885 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
|
|
3886 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
|
|
3887 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
|
|
3888
|
|
|
3889 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
3890 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3891 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3892
|
|
|
3893 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
|
|
3894
|
|
|
3895 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
3896 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
3897 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
3898 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
3899 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
|
|
3900
|
|
|
3901 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
3902 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
3903 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
3904 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
3905 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
3906
|
|
|
3907 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
|
|
3908 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
3909 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
3910 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
3911
|
|
|
3912 /****************** Bit definition for FSMC_PCR4 register *******************/
|
|
|
3913 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
|
|
|
3914 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
|
|
|
3915 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
|
|
|
3916
|
|
|
3917 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
|
|
|
3918 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
3919 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
3920
|
|
|
3921 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
|
|
|
3922
|
|
|
3923 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
|
|
|
3924 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
|
|
|
3925 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
|
|
|
3926 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
|
|
|
3927 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
|
|
|
3928
|
|
|
3929 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
|
|
|
3930 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
3931 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
3932 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
3933 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
3934
|
|
|
3935 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
|
|
|
3936 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
3937 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
3938 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
3939
|
|
|
3940 /******************* Bit definition for FSMC_SR2 register *******************/
|
|
|
3941 #define FSMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
3942 #define FSMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
3943 #define FSMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
3944 #define FSMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
3945 #define FSMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
3946 #define FSMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
3947 #define FSMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
3948
|
|
|
3949 /******************* Bit definition for FSMC_SR3 register *******************/
|
|
|
3950 #define FSMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
3951 #define FSMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
3952 #define FSMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
3953 #define FSMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
3954 #define FSMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
3955 #define FSMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
3956 #define FSMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
3957
|
|
|
3958 /******************* Bit definition for FSMC_SR4 register *******************/
|
|
|
3959 #define FSMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
|
|
|
3960 #define FSMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
|
|
|
3961 #define FSMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
|
|
|
3962 #define FSMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
|
|
|
3963 #define FSMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
|
|
|
3964 #define FSMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
|
|
|
3965 #define FSMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
|
|
|
3966
|
|
|
3967 /****************** Bit definition for FSMC_PMEM2 register ******************/
|
|
|
3968 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
|
|
|
3969 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
3970 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
3971 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
3972 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
3973 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
3974 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
3975 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
3976 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
3977
|
|
|
3978 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
|
|
|
3979 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
3980 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
3981 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
3982 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
3983 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
3984 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
3985 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
3986 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
3987
|
|
|
3988 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
|
|
|
3989 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
3990 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
3991 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
3992 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
3993 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
3994 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
3995 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
3996 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
3997
|
|
|
3998 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
|
|
|
3999 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4000 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4001 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4002 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4003 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4004 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4005 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4006 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4007
|
|
|
4008 /****************** Bit definition for FSMC_PMEM3 register ******************/
|
|
|
4009 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
|
|
|
4010 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4011 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4012 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4013 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4014 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4015 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4016 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4017 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4018
|
|
|
4019 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
|
|
|
4020 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4021 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4022 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4023 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4024 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4025 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4026 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4027 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4028
|
|
|
4029 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
|
|
|
4030 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4031 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4032 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4033 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4034 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4035 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4036 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4037 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4038
|
|
|
4039 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
|
|
|
4040 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4041 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4042 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4043 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4044 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4045 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4046 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4047 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4048
|
|
|
4049 /****************** Bit definition for FSMC_PMEM4 register ******************/
|
|
|
4050 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
|
|
|
4051 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4052 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4053 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4054 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4055 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4056 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4057 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4058 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4059
|
|
|
4060 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
|
|
|
4061 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4062 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4063 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4064 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4065 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4066 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4067 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4068 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4069
|
|
|
4070 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
|
|
|
4071 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4072 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4073 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4074 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4075 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4076 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4077 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4078 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4079
|
|
|
4080 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
|
|
|
4081 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4082 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4083 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4084 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4085 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4086 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4087 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4088 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4089
|
|
|
4090 /****************** Bit definition for FSMC_PATT2 register ******************/
|
|
|
4091 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
|
|
|
4092 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4093 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4094 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4095 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4096 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4097 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4098 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4099 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4100
|
|
|
4101 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
|
|
|
4102 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4103 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4104 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4105 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4106 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4107 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4108 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4109 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4110
|
|
|
4111 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
|
|
|
4112 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4113 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4114 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4115 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4116 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4117 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4118 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4119 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4120
|
|
|
4121 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
|
|
|
4122 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4123 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4124 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4125 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4126 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4127 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4128 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4129 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4130
|
|
|
4131 /****************** Bit definition for FSMC_PATT3 register ******************/
|
|
|
4132 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
|
|
|
4133 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4134 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4135 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4136 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4137 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4138 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4139 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4140 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4141
|
|
|
4142 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
|
|
|
4143 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4144 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4145 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4146 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4147 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4148 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4149 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4150 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4151
|
|
|
4152 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
|
|
|
4153 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4154 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4155 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4156 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4157 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4158 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4159 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4160 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4161
|
|
|
4162 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
|
|
|
4163 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4164 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4165 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4166 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4167 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4168 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4169 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4170 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4171
|
|
|
4172 /****************** Bit definition for FSMC_PATT4 register ******************/
|
|
|
4173 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
|
|
|
4174 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4175 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4176 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4177 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4178 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4179 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4180 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4181 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4182
|
|
|
4183 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
|
|
|
4184 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4185 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4186 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4187 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4188 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4189 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4190 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4191 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4192
|
|
|
4193 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
|
|
|
4194 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4195 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4196 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4197 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4198 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4199 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4200 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4201 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4202
|
|
|
4203 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
|
|
|
4204 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4205 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4206 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4207 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4208 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4209 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4210 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4211 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4212
|
|
|
4213 /****************** Bit definition for FSMC_PIO4 register *******************/
|
|
|
4214 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
|
|
|
4215 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
4216 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
4217 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
4218 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
4219 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
4220 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
4221 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
4222 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
|
|
|
4223
|
|
|
4224 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
|
|
|
4225 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
4226 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
4227 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
|
|
|
4228 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
|
|
|
4229 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
|
|
|
4230 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
|
|
|
4231 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
|
|
|
4232 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
|
|
|
4233
|
|
|
4234 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
|
|
|
4235 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
4236 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
4237 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
4238 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
4239 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
4240 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
4241 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
4242 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
4243
|
|
|
4244 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
|
|
|
4245 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
4246 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
4247 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
4248 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
4249 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
4250 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
4251 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
4252 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
4253
|
|
|
4254 /****************** Bit definition for FSMC_ECCR2 register ******************/
|
|
|
4255 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
|
|
4256
|
|
|
4257 /****************** Bit definition for FSMC_ECCR3 register ******************/
|
|
|
4258 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
|
|
|
4259
|
|
|
4260 /******************************************************************************/
|
|
|
4261 /* */
|
|
|
4262 /* General Purpose I/O */
|
|
|
4263 /* */
|
|
|
4264 /******************************************************************************/
|
|
|
4265 /****************** Bits definition for GPIO_MODER register *****************/
|
|
|
4266 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
|
|
|
4267 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
|
|
|
4268 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
|
|
|
4269
|
|
|
4270 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
|
|
|
4271 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
|
|
|
4272 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
|
|
|
4273
|
|
|
4274 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
|
|
|
4275 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
|
|
|
4276 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
|
|
|
4277
|
|
|
4278 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
|
|
|
4279 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
|
|
|
4280 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
|
|
|
4281
|
|
|
4282 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
|
|
|
4283 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
|
|
|
4284 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
|
|
|
4285
|
|
|
4286 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
|
|
|
4287 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
|
|
|
4288 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
|
|
|
4289
|
|
|
4290 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
|
|
|
4291 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
|
|
|
4292 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
|
|
|
4293
|
|
|
4294 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
|
|
|
4295 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
|
|
|
4296 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
|
|
|
4297
|
|
|
4298 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
|
|
|
4299 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
|
|
|
4300 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
|
|
|
4301
|
|
|
4302 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
|
|
|
4303 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
|
|
|
4304 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
|
|
|
4305
|
|
|
4306 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
|
|
|
4307 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
|
|
|
4308 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
|
|
|
4309
|
|
|
4310 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
|
|
|
4311 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
|
|
|
4312 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
|
|
|
4313
|
|
|
4314 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
|
|
|
4315 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
|
|
|
4316 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
|
|
|
4317
|
|
|
4318 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
|
|
|
4319 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
|
|
|
4320 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
|
|
|
4321
|
|
|
4322 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
|
|
|
4323 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
|
|
|
4324 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
|
|
|
4325
|
|
|
4326 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
|
|
|
4327 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
|
|
|
4328 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
|
|
|
4329
|
|
|
4330 /****************** Bits definition for GPIO_OTYPER register ****************/
|
|
|
4331 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
|
|
|
4332 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
|
|
|
4333 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
|
|
|
4334 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
|
|
|
4335 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
|
|
|
4336 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
|
|
|
4337 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
|
|
|
4338 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
|
|
|
4339 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
|
|
|
4340 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
|
|
|
4341 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
|
|
|
4342 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
|
|
|
4343 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
|
|
|
4344 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
|
|
|
4345 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
|
|
|
4346 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
|
|
|
4347
|
|
|
4348 /****************** Bits definition for GPIO_OSPEEDR register ***************/
|
|
|
4349 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
|
|
|
4350 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
|
|
|
4351 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
|
|
|
4352
|
|
|
4353 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
|
|
|
4354 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
|
|
|
4355 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
|
|
|
4356
|
|
|
4357 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
|
|
|
4358 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
|
|
|
4359 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
|
|
|
4360
|
|
|
4361 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
|
|
|
4362 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
|
|
|
4363 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
|
|
|
4364
|
|
|
4365 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
|
|
|
4366 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
|
|
|
4367 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
|
|
|
4368
|
|
|
4369 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
|
|
|
4370 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
|
|
|
4371 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
|
|
|
4372
|
|
|
4373 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
|
|
|
4374 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
|
|
|
4375 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
|
|
|
4376
|
|
|
4377 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
|
|
|
4378 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
|
|
|
4379 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
|
|
|
4380
|
|
|
4381 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
|
|
|
4382 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
|
|
|
4383 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
|
|
|
4384
|
|
|
4385 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
|
|
|
4386 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
|
|
|
4387 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
|
|
|
4388
|
|
|
4389 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
|
|
|
4390 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
|
|
|
4391 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
|
|
|
4392
|
|
|
4393 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
|
|
|
4394 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
|
|
|
4395 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
|
|
|
4396
|
|
|
4397 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
|
|
|
4398 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
|
|
|
4399 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
|
|
|
4400
|
|
|
4401 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
|
|
|
4402 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
|
|
|
4403 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
|
|
|
4404
|
|
|
4405 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
|
|
|
4406 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
|
|
|
4407 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
|
|
|
4408
|
|
|
4409 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
|
|
|
4410 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
|
|
|
4411 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
|
|
|
4412
|
|
|
4413 /****************** Bits definition for GPIO_PUPDR register *****************/
|
|
|
4414 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
|
|
|
4415 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
|
|
|
4416 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
|
|
|
4417
|
|
|
4418 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
|
|
|
4419 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
|
|
|
4420 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
|
|
|
4421
|
|
|
4422 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
|
|
|
4423 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
|
|
|
4424 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
|
|
|
4425
|
|
|
4426 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
|
|
|
4427 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
|
|
|
4428 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
|
|
|
4429
|
|
|
4430 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
|
|
|
4431 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
|
|
|
4432 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
|
|
|
4433
|
|
|
4434 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
|
|
|
4435 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
|
|
|
4436 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
|
|
|
4437
|
|
|
4438 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
|
|
|
4439 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
|
|
|
4440 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
|
|
|
4441
|
|
|
4442 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
|
|
|
4443 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
|
|
|
4444 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
|
|
|
4445
|
|
|
4446 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
|
|
|
4447 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
|
|
|
4448 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
|
|
|
4449
|
|
|
4450 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
|
|
|
4451 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
|
|
|
4452 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
|
|
|
4453
|
|
|
4454 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
|
|
|
4455 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
|
|
|
4456 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
|
|
|
4457
|
|
|
4458 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
|
|
|
4459 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
|
|
|
4460 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
|
|
|
4461
|
|
|
4462 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
|
|
|
4463 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
|
|
|
4464 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
|
|
|
4465
|
|
|
4466 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
|
|
|
4467 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
|
|
|
4468 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
|
|
|
4469
|
|
|
4470 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
|
|
|
4471 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
|
|
|
4472 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
|
|
|
4473
|
|
|
4474 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
|
|
|
4475 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
|
|
|
4476 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
|
|
|
4477
|
|
|
4478 /****************** Bits definition for GPIO_IDR register *******************/
|
|
|
4479 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
|
|
|
4480 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
|
|
|
4481 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
|
|
|
4482 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
|
|
|
4483 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
|
|
|
4484 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
|
|
|
4485 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
|
|
|
4486 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
|
|
|
4487 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
|
|
|
4488 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
|
|
|
4489 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
|
|
|
4490 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
|
|
|
4491 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
|
|
|
4492 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
|
|
|
4493 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
|
|
|
4494 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
|
|
|
4495 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
|
|
|
4496 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
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|
|
4497 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
|
|
|
4498 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
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|
|
4499 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
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|
4500 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
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4501 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
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4502 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
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4503 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
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4504 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
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4505 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
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4506 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
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4507 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
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4508 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
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4509 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
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4510 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
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4511 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
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4512
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|
|
4513 /****************** Bits definition for GPIO_ODR register *******************/
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4514 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
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4515 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
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4516 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
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4517 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
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4518 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
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4519 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
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4520 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
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4521 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
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4522 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
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4523 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
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4524 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
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4525 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
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4526 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
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4527 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
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4528 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
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4529 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
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|
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4530 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
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4531 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
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4532 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
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4533 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
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4534 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
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4535 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
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4536 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
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4537 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
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4538 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
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4539 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
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4540 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
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4541 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
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4542 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
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4543 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
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4544 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
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4545 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
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4546 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
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4547
|
|
|
4548 /****************** Bits definition for GPIO_BSRR register ******************/
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4549 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
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4550 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
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4551 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
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4552 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
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4553 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
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4554 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
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4555 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
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4556 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
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4557 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
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4558 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
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|
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4559 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
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4560 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
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|
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4561 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
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4562 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
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|
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4563 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
|
|
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4564 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
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4565 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
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4566 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
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4567 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
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4568 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
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|
|
4569 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
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|
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4570 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
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|
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4571 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
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4572 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
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4573 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
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|
4574 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
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4575 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
|
|
|
4576 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
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|
|
4577 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
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|
|
4578 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
|
|
|
4579 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
|
|
|
4580 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
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|
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4581
|
|
|
4582 /****************** Bit definition for GPIO_LCKR register *********************/
|
|
|
4583 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
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|
|
4584 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
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|
|
4585 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
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|
|
4586 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
|
|
|
4587 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
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|
|
4588 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
|
|
|
4589 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
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|
|
4590 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
|
|
|
4591 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
|
|
|
4592 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
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|
4593 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
|
|
|
4594 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
|
|
|
4595 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
|
|
|
4596 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
|
|
|
4597 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
|
|
|
4598 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
|
|
|
4599 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
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4600
|
|
|
4601 /******************************************************************************/
|
|
|
4602 /* */
|
|
|
4603 /* Inter-integrated Circuit Interface */
|
|
|
4604 /* */
|
|
|
4605 /******************************************************************************/
|
|
|
4606 /******************* Bit definition for I2C_CR1 register ********************/
|
|
|
4607 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
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|
4608 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
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4609 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
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4610 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
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4611 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
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4612 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
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4613 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
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4614 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
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4615 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
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4616 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
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4617 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
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4618 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
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4619 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
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4620 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
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4621
|
|
|
4622 /******************* Bit definition for I2C_CR2 register ********************/
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|
|
4623 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
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4624 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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4625 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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4626 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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4627 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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4628 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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4629 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
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4630
|
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4631 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
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4632 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
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4633 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
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4634 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
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4635 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
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4636
|
|
|
4637 /******************* Bit definition for I2C_OAR1 register *******************/
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|
4638 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
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4639 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
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4640
|
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|
4641 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
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4642 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
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4643 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
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4644 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
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|
4645 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
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|
4646 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
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|
4647 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
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|
4648 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
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|
4649 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
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|
4650 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
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|
4651
|
|
|
4652 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
|
|
|
4653
|
|
|
4654 /******************* Bit definition for I2C_OAR2 register *******************/
|
|
|
4655 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
|
|
|
4656 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
|
|
|
4657
|
|
|
4658 /******************** Bit definition for I2C_DR register ********************/
|
|
|
4659 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
|
|
|
4660
|
|
|
4661 /******************* Bit definition for I2C_SR1 register ********************/
|
|
|
4662 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
|
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|
4663 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
|
|
|
4664 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
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|
|
4665 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
|
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|
4666 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
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|
|
4667 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
|
|
|
4668 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
|
|
|
4669 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
|
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|
4670 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
|
|
|
4671 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
|
|
|
4672 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
|
|
|
4673 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
|
|
|
4674 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
|
|
|
4675 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
|
|
|
4676
|
|
|
4677 /******************* Bit definition for I2C_SR2 register ********************/
|
|
|
4678 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
|
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|
4679 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
|
|
|
4680 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
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|
4681 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
|
|
|
4682 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
|
|
|
4683 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
|
|
|
4684 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
|
|
|
4685 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
|
|
|
4686
|
|
|
4687 /******************* Bit definition for I2C_CCR register ********************/
|
|
|
4688 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
|
|
|
4689 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
|
|
|
4690 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
|
|
|
4691
|
|
|
4692 /****************** Bit definition for I2C_TRISE register *******************/
|
|
|
4693 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
|
|
|
4694
|
|
|
4695 /****************** Bit definition for I2C_FLTR register *******************/
|
|
|
4696 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
|
|
|
4697 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
|
|
|
4698
|
|
|
4699 /******************************************************************************/
|
|
|
4700 /* */
|
|
|
4701 /* Independent WATCHDOG */
|
|
|
4702 /* */
|
|
|
4703 /******************************************************************************/
|
|
|
4704 /******************* Bit definition for IWDG_KR register ********************/
|
|
|
4705 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
|
|
|
4706
|
|
|
4707 /******************* Bit definition for IWDG_PR register ********************/
|
|
|
4708 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
|
|
|
4709 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
4710 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
4711 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
4712
|
|
|
4713 /******************* Bit definition for IWDG_RLR register *******************/
|
|
|
4714 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
|
|
|
4715
|
|
|
4716 /******************* Bit definition for IWDG_SR register ********************/
|
|
|
4717 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
|
|
|
4718 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
|
|
|
4719
|
|
|
4720
|
|
|
4721 /******************************************************************************/
|
|
|
4722 /* */
|
|
|
4723 /* Power Control */
|
|
|
4724 /* */
|
|
|
4725 /******************************************************************************/
|
|
|
4726 /******************** Bit definition for PWR_CR register ********************/
|
|
|
4727 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
|
|
|
4728 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
|
|
|
4729 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
|
|
|
4730 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
|
|
|
4731 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
|
|
|
4732
|
|
|
4733 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
|
|
|
4734 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
|
|
|
4735 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
|
|
|
4736 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
|
|
|
4737
|
|
|
4738 /*!< PVD level configuration */
|
|
|
4739 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
|
|
|
4740 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
|
|
|
4741 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
|
|
|
4742 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
|
|
|
4743 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
|
|
|
4744 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
|
|
|
4745 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
|
|
|
4746 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
|
|
|
4747
|
|
|
4748 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
|
|
|
4749 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
|
|
|
4750 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
|
|
|
4751 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
|
|
|
4752 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
|
|
|
4753
|
|
|
4754 /* Legacy define */
|
|
|
4755 #define PWR_CR_PMODE PWR_CR_VOS
|
|
|
4756
|
|
|
4757 /******************* Bit definition for PWR_CSR register ********************/
|
|
|
4758 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
|
|
|
4759 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
|
|
|
4760 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
|
|
|
4761 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
|
|
|
4762 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
|
|
|
4763 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
|
|
|
4764 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
|
|
|
4765
|
|
|
4766 /* Legacy define */
|
|
|
4767 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
|
|
|
4768
|
|
|
4769 /******************************************************************************/
|
|
|
4770 /* */
|
|
|
4771 /* Reset and Clock Control */
|
|
|
4772 /* */
|
|
|
4773 /******************************************************************************/
|
|
|
4774 /******************** Bit definition for RCC_CR register ********************/
|
|
|
4775 #define RCC_CR_HSION ((uint32_t)0x00000001)
|
|
|
4776 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
|
|
|
4777
|
|
|
4778 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
|
|
|
4779 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
|
|
|
4780 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
|
|
|
4781 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
|
|
|
4782 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
|
|
|
4783 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
|
|
|
4784
|
|
|
4785 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
|
|
|
4786 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
|
|
|
4787 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
|
|
|
4788 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
|
|
|
4789 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
|
|
|
4790 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
|
|
|
4791 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
|
|
|
4792 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
|
|
|
4793 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
|
|
|
4794
|
|
|
4795 #define RCC_CR_HSEON ((uint32_t)0x00010000)
|
|
|
4796 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
|
|
|
4797 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
|
|
|
4798 #define RCC_CR_CSSON ((uint32_t)0x00080000)
|
|
|
4799 #define RCC_CR_PLLON ((uint32_t)0x01000000)
|
|
|
4800 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
|
|
|
4801 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
|
|
|
4802 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
|
|
|
4803
|
|
|
4804 /******************** Bit definition for RCC_PLLCFGR register ***************/
|
|
|
4805 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
|
|
|
4806 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
|
|
|
4807 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
|
|
|
4808 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
|
|
|
4809 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
|
|
|
4810 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
|
|
|
4811 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
|
|
|
4812
|
|
|
4813 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
|
|
|
4814 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
|
|
|
4815 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
|
|
|
4816 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
|
|
|
4817 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
|
|
|
4818 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
|
|
|
4819 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
|
|
|
4820 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
|
|
|
4821 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
|
|
|
4822 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
|
|
|
4823
|
|
|
4824 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
|
|
|
4825 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
|
|
|
4826 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
|
|
|
4827
|
|
|
4828 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
|
|
|
4829 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
|
|
|
4830 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
|
|
|
4831
|
|
|
4832 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
|
|
|
4833 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
|
|
|
4834 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
|
|
|
4835 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
|
|
|
4836 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
|
|
|
4837
|
|
|
4838 /******************** Bit definition for RCC_CFGR register ******************/
|
|
|
4839 /*!< SW configuration */
|
|
|
4840 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
|
|
|
4841 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
|
|
4842 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
|
|
4843
|
|
|
4844 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
|
|
|
4845 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
|
|
|
4846 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
|
|
|
4847
|
|
|
4848 /*!< SWS configuration */
|
|
|
4849 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
|
|
|
4850 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
|
|
|
4851 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
|
|
|
4852
|
|
|
4853 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
|
|
|
4854 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
|
|
|
4855 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
|
|
|
4856
|
|
|
4857 /*!< HPRE configuration */
|
|
|
4858 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
|
|
|
4859 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
|
|
|
4860 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
|
|
|
4861 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
|
|
|
4862 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
|
|
|
4863
|
|
|
4864 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
|
|
|
4865 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
|
|
|
4866 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
|
|
|
4867 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
|
|
|
4868 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
|
|
|
4869 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
|
|
|
4870 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
|
|
|
4871 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
|
|
|
4872 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
|
|
|
4873
|
|
|
4874 /*!< PPRE1 configuration */
|
|
|
4875 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
|
|
|
4876 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
|
|
|
4877 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
|
|
|
4878 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
|
|
|
4879
|
|
|
4880 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
4881 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
|
|
|
4882 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
|
|
|
4883 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
|
|
|
4884 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
|
|
|
4885
|
|
|
4886 /*!< PPRE2 configuration */
|
|
|
4887 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
|
|
|
4888 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
|
|
|
4889 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
|
|
|
4890 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
|
|
|
4891
|
|
|
4892 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
|
|
|
4893 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
|
|
|
4894 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
|
|
|
4895 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
|
|
|
4896 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
|
|
|
4897
|
|
|
4898 /*!< RTCPRE configuration */
|
|
|
4899 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
|
|
|
4900 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
|
|
|
4901 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
|
|
|
4902 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
|
|
|
4903 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
|
|
|
4904 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
|
|
|
4905
|
|
|
4906 /*!< MCO1 configuration */
|
|
|
4907 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
|
|
|
4908 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
|
|
|
4909 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
|
|
|
4910
|
|
|
4911 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
|
|
|
4912
|
|
|
4913 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
|
|
|
4914 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
|
|
|
4915 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
|
|
|
4916 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
|
|
|
4917
|
|
|
4918 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
|
|
|
4919 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
|
|
|
4920 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
|
|
|
4921 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
|
|
|
4922
|
|
|
4923 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
|
|
|
4924 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
|
|
|
4925 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
|
|
|
4926
|
|
|
4927 /******************** Bit definition for RCC_CIR register *******************/
|
|
|
4928 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
|
|
|
4929 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
|
|
|
4930 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
|
|
|
4931 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
|
|
|
4932 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
|
|
|
4933 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
|
|
|
4934
|
|
|
4935 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
|
|
|
4936 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
|
|
|
4937 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
|
|
|
4938 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
|
|
|
4939 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
|
|
|
4940 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
|
|
|
4941 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
|
|
|
4942
|
|
|
4943 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
|
|
|
4944 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
|
|
|
4945 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
|
|
|
4946 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
|
|
|
4947 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
|
|
|
4948 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
|
|
|
4949
|
|
|
4950 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
|
|
|
4951
|
|
|
4952 /******************** Bit definition for RCC_AHB1RSTR register **************/
|
|
|
4953 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
|
|
|
4954 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
|
|
|
4955 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
|
|
|
4956 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
|
|
|
4957 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
|
|
|
4958 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
|
|
|
4959 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
|
|
|
4960 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
|
|
|
4961 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
|
|
|
4962 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
|
|
|
4963 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
|
|
|
4964 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
|
|
|
4965 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
|
|
|
4966 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
|
|
|
4967
|
|
|
4968 /******************** Bit definition for RCC_AHB2RSTR register **************/
|
|
|
4969 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
|
|
|
4970 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
|
|
|
4971 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
|
|
|
4972
|
|
|
4973 /******************** Bit definition for RCC_AHB3RSTR register **************/
|
|
|
4974
|
|
|
4975 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)
|
|
|
4976
|
|
|
4977 /******************** Bit definition for RCC_APB1RSTR register **************/
|
|
|
4978 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
|
|
|
4979 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
|
|
|
4980 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
|
|
|
4981 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
|
|
|
4982 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
|
|
|
4983 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
|
|
|
4984 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
|
|
|
4985 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
|
|
|
4986 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
|
|
|
4987 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
|
|
|
4988 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
|
|
|
4989 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
|
|
|
4990 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
|
|
|
4991 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
|
|
|
4992 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
|
|
|
4993 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
|
|
|
4994 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
|
|
|
4995 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
|
|
|
4996 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
|
|
|
4997 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
|
|
|
4998 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
|
|
|
4999 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
|
|
|
5000 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
|
|
|
5001
|
|
|
5002 /******************** Bit definition for RCC_APB2RSTR register **************/
|
|
|
5003 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
|
|
|
5004 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
|
|
|
5005 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
|
|
|
5006 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
|
|
|
5007 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
|
|
|
5008 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
|
|
|
5009 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
|
|
|
5010 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
|
|
|
5011 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
|
|
|
5012 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
|
|
|
5013 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
|
|
|
5014
|
|
|
5015 /* Old SPI1RST bit definition, maintained for legacy purpose */
|
|
|
5016 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
|
|
|
5017
|
|
|
5018 /******************** Bit definition for RCC_AHB1ENR register ***************/
|
|
|
5019 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
|
|
|
5020 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
|
|
|
5021 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
|
|
|
5022 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
|
|
|
5023 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
|
|
|
5024 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
|
|
|
5025 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
|
|
|
5026 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
|
|
|
5027 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
|
|
|
5028 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
|
|
|
5029 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
|
|
|
5030 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
|
|
|
5031 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
|
|
|
5032 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
|
|
|
5033
|
|
|
5034 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
|
|
|
5035 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
|
|
|
5036 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
|
|
|
5037 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
|
|
|
5038 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
|
|
|
5039 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
|
|
|
5040
|
|
|
5041 /******************** Bit definition for RCC_AHB2ENR register ***************/
|
|
|
5042 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
|
|
|
5043 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
|
|
|
5044 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
|
|
|
5045
|
|
|
5046 /******************** Bit definition for RCC_AHB3ENR register ***************/
|
|
|
5047
|
|
|
5048 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)
|
|
|
5049
|
|
|
5050 /******************** Bit definition for RCC_APB1ENR register ***************/
|
|
|
5051 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
|
|
|
5052 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
|
|
|
5053 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
|
|
|
5054 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
|
|
|
5055 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
|
|
|
5056 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
|
|
|
5057 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
|
|
|
5058 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
|
|
|
5059 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
|
|
|
5060 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
|
|
|
5061 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
|
|
|
5062 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
|
|
|
5063 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
|
|
|
5064 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
|
|
|
5065 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
|
|
|
5066 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
|
|
|
5067 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
|
|
|
5068 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
|
|
|
5069 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
|
|
|
5070 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
|
|
|
5071 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
|
|
|
5072 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
|
|
|
5073 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
|
|
|
5074
|
|
|
5075 /******************** Bit definition for RCC_APB2ENR register ***************/
|
|
|
5076 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
|
|
|
5077 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
|
|
|
5078 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
|
|
|
5079 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
|
|
|
5080 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
|
|
|
5081 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
|
|
|
5082 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
|
|
|
5083 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
|
|
|
5084 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
|
|
|
5085 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
|
|
|
5086 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
|
|
|
5087 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
|
|
|
5088 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
|
|
|
5089 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
|
|
|
5090 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
|
|
|
5091
|
|
|
5092 /******************** Bit definition for RCC_AHB1LPENR register *************/
|
|
|
5093 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
|
|
|
5094 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
|
|
|
5095 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
|
|
|
5096 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
|
|
|
5097 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
|
|
|
5098 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
|
|
|
5099 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
|
|
|
5100 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
|
|
|
5101 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
|
|
|
5102 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
|
|
|
5103 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
|
|
|
5104 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
|
|
|
5105 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
|
|
|
5106 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
|
|
|
5107 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
|
|
|
5108 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
|
|
|
5109 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
|
|
|
5110 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
|
|
|
5111 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
|
|
|
5112 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
|
|
|
5113 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
|
|
|
5114 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
|
|
|
5115 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
|
|
|
5116
|
|
|
5117 /******************** Bit definition for RCC_AHB2LPENR register *************/
|
|
|
5118 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
|
|
|
5119 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
|
|
|
5120 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
|
|
|
5121
|
|
|
5122 /******************** Bit definition for RCC_AHB3LPENR register *************/
|
|
|
5123
|
|
|
5124 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)
|
|
|
5125
|
|
|
5126 /******************** Bit definition for RCC_APB1LPENR register *************/
|
|
|
5127 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
|
|
|
5128 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
|
|
|
5129 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
|
|
|
5130 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
|
|
|
5131 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
|
|
|
5132 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
|
|
|
5133 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
|
|
|
5134 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
|
|
|
5135 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
|
|
|
5136 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
|
|
|
5137 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
|
|
|
5138 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
|
|
|
5139 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
|
|
|
5140 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
|
|
|
5141 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
|
|
|
5142 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
|
|
|
5143 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
|
|
|
5144 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
|
|
|
5145 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
|
|
|
5146 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
|
|
|
5147 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
|
|
|
5148 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
|
|
|
5149 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
|
|
|
5150
|
|
|
5151 /******************** Bit definition for RCC_APB2LPENR register *************/
|
|
|
5152 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
|
|
|
5153 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
|
|
|
5154 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
|
|
|
5155 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
|
|
|
5156 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
|
|
|
5157 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
|
|
|
5158 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
|
|
|
5159 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
|
|
|
5160 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
|
|
|
5161 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
|
|
|
5162 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
|
|
|
5163 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
|
|
|
5164 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
|
|
|
5165
|
|
|
5166 /******************** Bit definition for RCC_BDCR register ******************/
|
|
|
5167 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
|
|
|
5168 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
|
|
|
5169 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
|
|
|
5170
|
|
|
5171 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
|
|
|
5172 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
|
|
|
5173 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
|
|
|
5174
|
|
|
5175 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
|
|
|
5176 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
|
|
|
5177
|
|
|
5178 /******************** Bit definition for RCC_CSR register *******************/
|
|
|
5179 #define RCC_CSR_LSION ((uint32_t)0x00000001)
|
|
|
5180 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
|
|
|
5181 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
|
|
|
5182 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
|
|
|
5183 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
|
|
|
5184 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
|
|
|
5185 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
|
|
|
5186 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
|
|
|
5187 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
|
|
|
5188 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
|
|
|
5189
|
|
|
5190 /******************** Bit definition for RCC_SSCGR register *****************/
|
|
|
5191 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
|
|
|
5192 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
|
|
|
5193 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
|
|
|
5194 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
|
|
|
5195
|
|
|
5196 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
|
|
|
5197 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
|
|
|
5198 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
|
|
|
5199 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
|
|
|
5200 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
|
|
|
5201 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
|
|
|
5202 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
|
|
|
5203 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
|
|
|
5204 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
|
|
|
5205 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
|
|
|
5206 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
|
|
|
5207
|
|
|
5208 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
|
|
|
5209 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
|
|
|
5210 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
|
|
|
5211 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
|
|
|
5212
|
|
|
5213 /******************************************************************************/
|
|
|
5214 /* */
|
|
|
5215 /* RNG */
|
|
|
5216 /* */
|
|
|
5217 /******************************************************************************/
|
|
|
5218 /******************** Bits definition for RNG_CR register *******************/
|
|
|
5219 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
|
|
|
5220 #define RNG_CR_IE ((uint32_t)0x00000008)
|
|
|
5221
|
|
|
5222 /******************** Bits definition for RNG_SR register *******************/
|
|
|
5223 #define RNG_SR_DRDY ((uint32_t)0x00000001)
|
|
|
5224 #define RNG_SR_CECS ((uint32_t)0x00000002)
|
|
|
5225 #define RNG_SR_SECS ((uint32_t)0x00000004)
|
|
|
5226 #define RNG_SR_CEIS ((uint32_t)0x00000020)
|
|
|
5227 #define RNG_SR_SEIS ((uint32_t)0x00000040)
|
|
|
5228
|
|
|
5229 /******************************************************************************/
|
|
|
5230 /* */
|
|
|
5231 /* Real-Time Clock (RTC) */
|
|
|
5232 /* */
|
|
|
5233 /******************************************************************************/
|
|
|
5234 /******************** Bits definition for RTC_TR register *******************/
|
|
|
5235 #define RTC_TR_PM ((uint32_t)0x00400000)
|
|
|
5236 #define RTC_TR_HT ((uint32_t)0x00300000)
|
|
|
5237 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
|
|
|
5238 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
|
|
|
5239 #define RTC_TR_HU ((uint32_t)0x000F0000)
|
|
|
5240 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
|
|
|
5241 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
|
|
|
5242 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
|
|
|
5243 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
|
|
|
5244 #define RTC_TR_MNT ((uint32_t)0x00007000)
|
|
|
5245 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
|
|
|
5246 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
|
|
|
5247 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
|
|
|
5248 #define RTC_TR_MNU ((uint32_t)0x00000F00)
|
|
|
5249 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
|
|
|
5250 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
|
|
|
5251 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
|
|
|
5252 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
|
|
|
5253 #define RTC_TR_ST ((uint32_t)0x00000070)
|
|
|
5254 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
|
|
|
5255 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
|
|
|
5256 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
|
|
|
5257 #define RTC_TR_SU ((uint32_t)0x0000000F)
|
|
|
5258 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
|
|
|
5259 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
|
|
|
5260 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
|
|
|
5261 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
|
|
|
5262
|
|
|
5263 /******************** Bits definition for RTC_DR register *******************/
|
|
|
5264 #define RTC_DR_YT ((uint32_t)0x00F00000)
|
|
|
5265 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
|
|
|
5266 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
|
|
|
5267 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
|
|
|
5268 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
|
|
|
5269 #define RTC_DR_YU ((uint32_t)0x000F0000)
|
|
|
5270 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
|
|
|
5271 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
|
|
|
5272 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
|
|
|
5273 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
|
|
|
5274 #define RTC_DR_WDU ((uint32_t)0x0000E000)
|
|
|
5275 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
|
|
|
5276 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
|
|
|
5277 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
|
|
|
5278 #define RTC_DR_MT ((uint32_t)0x00001000)
|
|
|
5279 #define RTC_DR_MU ((uint32_t)0x00000F00)
|
|
|
5280 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
|
|
|
5281 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
|
|
|
5282 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
|
|
|
5283 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
|
|
|
5284 #define RTC_DR_DT ((uint32_t)0x00000030)
|
|
|
5285 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
|
|
|
5286 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
|
|
|
5287 #define RTC_DR_DU ((uint32_t)0x0000000F)
|
|
|
5288 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
|
|
|
5289 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
|
|
|
5290 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
|
|
|
5291 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
|
|
|
5292
|
|
|
5293 /******************** Bits definition for RTC_CR register *******************/
|
|
|
5294 #define RTC_CR_COE ((uint32_t)0x00800000)
|
|
|
5295 #define RTC_CR_OSEL ((uint32_t)0x00600000)
|
|
|
5296 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
|
|
|
5297 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
|
|
|
5298 #define RTC_CR_POL ((uint32_t)0x00100000)
|
|
|
5299 #define RTC_CR_COSEL ((uint32_t)0x00080000)
|
|
|
5300 #define RTC_CR_BCK ((uint32_t)0x00040000)
|
|
|
5301 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
|
|
|
5302 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
|
|
|
5303 #define RTC_CR_TSIE ((uint32_t)0x00008000)
|
|
|
5304 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
|
|
|
5305 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
|
|
|
5306 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
|
|
|
5307 #define RTC_CR_TSE ((uint32_t)0x00000800)
|
|
|
5308 #define RTC_CR_WUTE ((uint32_t)0x00000400)
|
|
|
5309 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
|
|
|
5310 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
|
|
|
5311 #define RTC_CR_DCE ((uint32_t)0x00000080)
|
|
|
5312 #define RTC_CR_FMT ((uint32_t)0x00000040)
|
|
|
5313 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
|
|
|
5314 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
|
|
|
5315 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
|
|
|
5316 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
|
|
|
5317 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
|
|
|
5318 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
|
|
|
5319 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
|
|
|
5320
|
|
|
5321 /******************** Bits definition for RTC_ISR register ******************/
|
|
|
5322 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
|
|
|
5323 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
|
|
|
5324 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
|
|
|
5325 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
|
|
|
5326 #define RTC_ISR_TSF ((uint32_t)0x00000800)
|
|
|
5327 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
|
|
|
5328 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
|
|
|
5329 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
|
|
|
5330 #define RTC_ISR_INIT ((uint32_t)0x00000080)
|
|
|
5331 #define RTC_ISR_INITF ((uint32_t)0x00000040)
|
|
|
5332 #define RTC_ISR_RSF ((uint32_t)0x00000020)
|
|
|
5333 #define RTC_ISR_INITS ((uint32_t)0x00000010)
|
|
|
5334 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
|
|
|
5335 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
|
|
|
5336 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
|
|
|
5337 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
|
|
|
5338
|
|
|
5339 /******************** Bits definition for RTC_PRER register *****************/
|
|
|
5340 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
|
|
|
5341 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
|
|
|
5342
|
|
|
5343 /******************** Bits definition for RTC_WUTR register *****************/
|
|
|
5344 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
|
|
|
5345
|
|
|
5346 /******************** Bits definition for RTC_CALIBR register ***************/
|
|
|
5347 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
|
|
|
5348 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
|
|
|
5349
|
|
|
5350 /******************** Bits definition for RTC_ALRMAR register ***************/
|
|
|
5351 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
|
|
|
5352 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
|
|
|
5353 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
|
|
|
5354 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
|
|
|
5355 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
|
|
|
5356 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
|
|
|
5357 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
|
|
|
5358 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
|
|
|
5359 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
|
|
|
5360 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
|
|
|
5361 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
|
|
|
5362 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
|
|
|
5363 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
|
|
|
5364 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
|
|
|
5365 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
|
|
|
5366 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
|
|
|
5367 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
|
|
|
5368 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
|
|
|
5369 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
|
|
|
5370 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
|
|
|
5371 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
|
|
|
5372 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
|
|
|
5373 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
|
|
|
5374 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
|
|
|
5375 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
|
|
|
5376 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
|
|
|
5377 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
|
|
|
5378 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
|
|
|
5379 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
|
|
|
5380 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
|
|
|
5381 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
|
|
|
5382 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
|
|
|
5383 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
|
|
|
5384 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
|
|
|
5385 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
|
|
|
5386 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
|
|
|
5387 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
|
|
|
5388 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
|
|
|
5389 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
|
|
|
5390 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
|
|
|
5391
|
|
|
5392 /******************** Bits definition for RTC_ALRMBR register ***************/
|
|
|
5393 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
|
|
|
5394 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
|
|
|
5395 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
|
|
|
5396 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
|
|
|
5397 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
|
|
|
5398 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
|
|
|
5399 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
|
|
|
5400 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
|
|
|
5401 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
|
|
|
5402 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
|
|
|
5403 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
|
|
|
5404 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
|
|
|
5405 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
|
|
|
5406 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
|
|
|
5407 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
|
|
|
5408 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
|
|
|
5409 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
|
|
|
5410 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
|
|
|
5411 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
|
|
|
5412 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
|
|
|
5413 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
|
|
|
5414 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
|
|
|
5415 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
|
|
|
5416 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
|
|
|
5417 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
|
|
|
5418 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
|
|
|
5419 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
|
|
|
5420 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
|
|
|
5421 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
|
|
|
5422 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
|
|
|
5423 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
|
|
|
5424 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
|
|
|
5425 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
|
|
|
5426 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
|
|
|
5427 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
|
|
|
5428 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
|
|
|
5429 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
|
|
|
5430 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
|
|
|
5431 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
|
|
|
5432 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
|
|
|
5433
|
|
|
5434 /******************** Bits definition for RTC_WPR register ******************/
|
|
|
5435 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
|
|
|
5436
|
|
|
5437 /******************** Bits definition for RTC_SSR register ******************/
|
|
|
5438 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
|
|
|
5439
|
|
|
5440 /******************** Bits definition for RTC_SHIFTR register ***************/
|
|
|
5441 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
|
|
|
5442 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
|
|
|
5443
|
|
|
5444 /******************** Bits definition for RTC_TSTR register *****************/
|
|
|
5445 #define RTC_TSTR_PM ((uint32_t)0x00400000)
|
|
|
5446 #define RTC_TSTR_HT ((uint32_t)0x00300000)
|
|
|
5447 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
|
|
|
5448 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
|
|
|
5449 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
|
|
|
5450 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
|
|
|
5451 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
|
|
|
5452 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
|
|
|
5453 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
|
|
|
5454 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
|
|
|
5455 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
|
|
|
5456 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
|
|
|
5457 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
|
|
|
5458 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
|
|
|
5459 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
|
|
|
5460 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
|
|
|
5461 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
|
|
|
5462 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
|
|
|
5463 #define RTC_TSTR_ST ((uint32_t)0x00000070)
|
|
|
5464 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
|
|
|
5465 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
|
|
|
5466 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
|
|
|
5467 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
|
|
|
5468 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
|
|
|
5469 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
|
|
|
5470 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
|
|
|
5471 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
|
|
|
5472
|
|
|
5473 /******************** Bits definition for RTC_TSDR register *****************/
|
|
|
5474 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
|
|
|
5475 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
|
|
|
5476 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
|
|
|
5477 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
|
|
|
5478 #define RTC_TSDR_MT ((uint32_t)0x00001000)
|
|
|
5479 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
|
|
|
5480 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
|
|
|
5481 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
|
|
|
5482 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
|
|
|
5483 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
|
|
|
5484 #define RTC_TSDR_DT ((uint32_t)0x00000030)
|
|
|
5485 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
|
|
|
5486 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
|
|
|
5487 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
|
|
|
5488 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
|
|
|
5489 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
|
|
|
5490 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
|
|
|
5491 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
|
|
|
5492
|
|
|
5493 /******************** Bits definition for RTC_TSSSR register ****************/
|
|
|
5494 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
|
|
|
5495
|
|
|
5496 /******************** Bits definition for RTC_CAL register *****************/
|
|
|
5497 #define RTC_CALR_CALP ((uint32_t)0x00008000)
|
|
|
5498 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
|
|
|
5499 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
|
|
|
5500 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
|
|
|
5501 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
|
|
|
5502 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
|
|
|
5503 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
|
|
|
5504 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
|
|
|
5505 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
|
|
|
5506 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
|
|
|
5507 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
|
|
|
5508 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
|
|
|
5509 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
|
|
|
5510
|
|
|
5511 /******************** Bits definition for RTC_TAFCR register ****************/
|
|
|
5512 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
|
|
|
5513 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
|
|
|
5514 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
|
|
|
5515 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
|
|
|
5516 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
|
|
|
5517 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
|
|
|
5518 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
|
|
|
5519 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
|
|
|
5520 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
|
|
|
5521 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
|
|
|
5522 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
|
|
|
5523 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
|
|
|
5524 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
|
|
|
5525 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
|
|
|
5526 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
|
|
|
5527 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
|
|
|
5528 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
|
|
|
5529 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
|
|
|
5530 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
|
|
|
5531 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
|
|
|
5532
|
|
|
5533 /******************** Bits definition for RTC_ALRMASSR register *************/
|
|
|
5534 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
5535 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
5536 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
5537 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
5538 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
5539 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
|
|
|
5540
|
|
|
5541 /******************** Bits definition for RTC_ALRMBSSR register *************/
|
|
|
5542 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
|
|
|
5543 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
|
|
|
5544 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
|
|
|
5545 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
|
|
|
5546 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
|
|
|
5547 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
|
|
|
5548
|
|
|
5549 /******************** Bits definition for RTC_BKP0R register ****************/
|
|
|
5550 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
|
|
|
5551
|
|
|
5552 /******************** Bits definition for RTC_BKP1R register ****************/
|
|
|
5553 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
|
|
|
5554
|
|
|
5555 /******************** Bits definition for RTC_BKP2R register ****************/
|
|
|
5556 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
|
|
|
5557
|
|
|
5558 /******************** Bits definition for RTC_BKP3R register ****************/
|
|
|
5559 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
|
|
|
5560
|
|
|
5561 /******************** Bits definition for RTC_BKP4R register ****************/
|
|
|
5562 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
|
|
|
5563
|
|
|
5564 /******************** Bits definition for RTC_BKP5R register ****************/
|
|
|
5565 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
|
|
|
5566
|
|
|
5567 /******************** Bits definition for RTC_BKP6R register ****************/
|
|
|
5568 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
|
|
|
5569
|
|
|
5570 /******************** Bits definition for RTC_BKP7R register ****************/
|
|
|
5571 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
|
|
|
5572
|
|
|
5573 /******************** Bits definition for RTC_BKP8R register ****************/
|
|
|
5574 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
|
|
|
5575
|
|
|
5576 /******************** Bits definition for RTC_BKP9R register ****************/
|
|
|
5577 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
|
|
|
5578
|
|
|
5579 /******************** Bits definition for RTC_BKP10R register ***************/
|
|
|
5580 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
|
|
|
5581
|
|
|
5582 /******************** Bits definition for RTC_BKP11R register ***************/
|
|
|
5583 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
|
|
|
5584
|
|
|
5585 /******************** Bits definition for RTC_BKP12R register ***************/
|
|
|
5586 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
|
|
|
5587
|
|
|
5588 /******************** Bits definition for RTC_BKP13R register ***************/
|
|
|
5589 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
|
|
|
5590
|
|
|
5591 /******************** Bits definition for RTC_BKP14R register ***************/
|
|
|
5592 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
|
|
|
5593
|
|
|
5594 /******************** Bits definition for RTC_BKP15R register ***************/
|
|
|
5595 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
|
|
|
5596
|
|
|
5597 /******************** Bits definition for RTC_BKP16R register ***************/
|
|
|
5598 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
|
|
|
5599
|
|
|
5600 /******************** Bits definition for RTC_BKP17R register ***************/
|
|
|
5601 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
|
|
|
5602
|
|
|
5603 /******************** Bits definition for RTC_BKP18R register ***************/
|
|
|
5604 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
|
|
|
5605
|
|
|
5606 /******************** Bits definition for RTC_BKP19R register ***************/
|
|
|
5607 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
|
|
|
5608
|
|
|
5609
|
|
|
5610
|
|
|
5611 /******************************************************************************/
|
|
|
5612 /* */
|
|
|
5613 /* SD host Interface */
|
|
|
5614 /* */
|
|
|
5615 /******************************************************************************/
|
|
|
5616 /****************** Bit definition for SDIO_POWER register ******************/
|
|
|
5617 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
|
|
|
5618 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
5619 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
5620
|
|
|
5621 /****************** Bit definition for SDIO_CLKCR register ******************/
|
|
|
5622 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
|
|
|
5623 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
|
|
|
5624 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
|
|
|
5625 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
|
|
|
5626
|
|
|
5627 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
|
|
|
5628 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
|
|
|
5629 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
|
|
|
5630
|
|
|
5631 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
|
|
|
5632 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
|
|
|
5633
|
|
|
5634 /******************* Bit definition for SDIO_ARG register *******************/
|
|
|
5635 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
|
|
|
5636
|
|
|
5637 /******************* Bit definition for SDIO_CMD register *******************/
|
|
|
5638 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
|
|
|
5639
|
|
|
5640 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
|
|
|
5641 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
|
|
|
5642 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
|
|
|
5643
|
|
|
5644 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
|
|
|
5645 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
|
|
|
5646 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
|
|
|
5647 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
|
|
|
5648 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
|
|
|
5649 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
|
|
|
5650 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
|
|
|
5651
|
|
|
5652 /***************** Bit definition for SDIO_RESPCMD register *****************/
|
|
|
5653 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
|
|
|
5654
|
|
|
5655 /****************** Bit definition for SDIO_RESP0 register ******************/
|
|
|
5656 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
5657
|
|
|
5658 /****************** Bit definition for SDIO_RESP1 register ******************/
|
|
|
5659 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
5660
|
|
|
5661 /****************** Bit definition for SDIO_RESP2 register ******************/
|
|
|
5662 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
5663
|
|
|
5664 /****************** Bit definition for SDIO_RESP3 register ******************/
|
|
|
5665 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
5666
|
|
|
5667 /****************** Bit definition for SDIO_RESP4 register ******************/
|
|
|
5668 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
|
|
|
5669
|
|
|
5670 /****************** Bit definition for SDIO_DTIMER register *****************/
|
|
|
5671 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
|
|
|
5672
|
|
|
5673 /****************** Bit definition for SDIO_DLEN register *******************/
|
|
|
5674 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
|
|
|
5675
|
|
|
5676 /****************** Bit definition for SDIO_DCTRL register ******************/
|
|
|
5677 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
|
|
|
5678 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
|
|
|
5679 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
|
|
|
5680 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
|
|
|
5681
|
|
|
5682 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
|
|
|
5683 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
5684 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
5685 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
5686 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
5687
|
|
|
5688 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
|
|
|
5689 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
|
|
|
5690 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
|
|
|
5691 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
|
|
|
5692
|
|
|
5693 /****************** Bit definition for SDIO_DCOUNT register *****************/
|
|
|
5694 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
|
|
|
5695
|
|
|
5696 /****************** Bit definition for SDIO_STA register ********************/
|
|
|
5697 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
|
|
|
5698 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
|
|
|
5699 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
|
|
|
5700 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
|
|
|
5701 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
|
|
|
5702 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
|
|
|
5703 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
|
|
|
5704 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
|
|
|
5705 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
|
|
|
5706 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
|
|
|
5707 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
|
|
|
5708 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
|
|
|
5709 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
|
|
|
5710 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
|
|
|
5711 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
|
|
|
5712 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
|
|
|
5713 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
|
|
|
5714 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
|
|
|
5715 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
|
|
|
5716 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
|
|
|
5717 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
|
|
|
5718 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
|
|
|
5719 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
|
|
|
5720 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
|
|
|
5721
|
|
|
5722 /******************* Bit definition for SDIO_ICR register *******************/
|
|
|
5723 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
|
|
|
5724 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
|
|
|
5725 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
|
|
|
5726 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
|
|
|
5727 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
|
|
|
5728 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
|
|
|
5729 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
|
|
|
5730 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
|
|
|
5731 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
|
|
|
5732 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
|
|
|
5733 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
|
|
|
5734 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
|
|
|
5735 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
|
|
|
5736
|
|
|
5737 /****************** Bit definition for SDIO_MASK register *******************/
|
|
|
5738 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
|
|
|
5739 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
|
|
|
5740 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
|
|
|
5741 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
|
|
|
5742 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
|
|
|
5743 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
|
|
|
5744 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
|
|
|
5745 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
|
|
|
5746 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
|
|
|
5747 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
|
|
|
5748 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
|
|
|
5749 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
|
|
|
5750 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
|
|
|
5751 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
|
|
|
5752 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
|
|
|
5753 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
|
|
|
5754 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
|
|
|
5755 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
|
|
|
5756 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
|
|
|
5757 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
|
|
|
5758 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
|
|
|
5759 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
|
|
|
5760 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
|
|
|
5761 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
|
|
|
5762
|
|
|
5763 /***************** Bit definition for SDIO_FIFOCNT register *****************/
|
|
|
5764 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
|
|
|
5765
|
|
|
5766 /****************** Bit definition for SDIO_FIFO register *******************/
|
|
|
5767 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
|
|
|
5768
|
|
|
5769 /******************************************************************************/
|
|
|
5770 /* */
|
|
|
5771 /* Serial Peripheral Interface */
|
|
|
5772 /* */
|
|
|
5773 /******************************************************************************/
|
|
|
5774 /******************* Bit definition for SPI_CR1 register ********************/
|
|
|
5775 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
|
|
|
5776 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
|
|
|
5777 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
|
|
|
5778
|
|
|
5779 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
|
|
|
5780 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
|
|
|
5781 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
5782 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
|
|
|
5783
|
|
|
5784 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
|
|
|
5785 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
|
|
|
5786 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
|
|
|
5787 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
|
|
|
5788 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
|
|
|
5789 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
|
|
|
5790 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
|
|
|
5791 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
|
|
|
5792 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
|
|
|
5793 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
|
|
|
5794
|
|
|
5795 /******************* Bit definition for SPI_CR2 register ********************/
|
|
|
5796 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
|
|
|
5797 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
|
|
|
5798 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
|
|
|
5799 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
|
|
|
5800 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
|
|
|
5801 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
|
|
|
5802 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
|
|
|
5803
|
|
|
5804 /******************** Bit definition for SPI_SR register ********************/
|
|
|
5805 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
|
|
|
5806 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
|
|
|
5807 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
|
|
|
5808 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
|
|
|
5809 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
|
|
|
5810 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
|
|
|
5811 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
|
|
|
5812 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
|
|
|
5813 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
|
|
|
5814
|
|
|
5815 /******************** Bit definition for SPI_DR register ********************/
|
|
|
5816 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
|
|
|
5817
|
|
|
5818 /******************* Bit definition for SPI_CRCPR register ******************/
|
|
|
5819 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
|
|
|
5820
|
|
|
5821 /****************** Bit definition for SPI_RXCRCR register ******************/
|
|
|
5822 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
|
|
|
5823
|
|
|
5824 /****************** Bit definition for SPI_TXCRCR register ******************/
|
|
|
5825 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
|
|
|
5826
|
|
|
5827 /****************** Bit definition for SPI_I2SCFGR register *****************/
|
|
|
5828 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
|
|
|
5829
|
|
|
5830 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
|
|
|
5831 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
5832 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
5833
|
|
|
5834 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
|
|
|
5835
|
|
|
5836 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
|
|
|
5837 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
5838 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
5839
|
|
|
5840 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
|
|
|
5841
|
|
|
5842 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
|
|
|
5843 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
|
|
|
5844 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
|
|
|
5845
|
|
|
5846 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
|
|
|
5847 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
|
|
|
5848
|
|
|
5849 /****************** Bit definition for SPI_I2SPR register *******************/
|
|
|
5850 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
|
|
|
5851 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
|
|
|
5852 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
|
|
|
5853
|
|
|
5854 /******************************************************************************/
|
|
|
5855 /* */
|
|
|
5856 /* SYSCFG */
|
|
|
5857 /* */
|
|
|
5858 /******************************************************************************/
|
|
|
5859 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
|
|
|
5860 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
|
|
|
5861 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
|
|
|
5862 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
|
|
|
5863 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
|
|
|
5864
|
|
|
5865 /****************** Bit definition for SYSCFG_PMC register ******************/
|
|
|
5866 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
|
|
|
5867 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
|
|
|
5868 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
|
|
|
5869
|
|
|
5870 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
|
|
|
5871 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
|
|
|
5872 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
|
|
|
5873 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
|
|
|
5874 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
|
|
|
5875 /**
|
|
|
5876 * @brief EXTI0 configuration
|
|
|
5877 */
|
|
|
5878 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
|
|
|
5879 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
|
|
|
5880 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
|
|
|
5881 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
|
|
|
5882 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
|
|
|
5883 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
|
|
|
5884 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
|
|
|
5885 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
|
|
|
5886 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
|
|
|
5887
|
|
|
5888 /**
|
|
|
5889 * @brief EXTI1 configuration
|
|
|
5890 */
|
|
|
5891 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
|
|
|
5892 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
|
|
|
5893 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
|
|
|
5894 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
|
|
|
5895 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
|
|
|
5896 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
|
|
|
5897 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
|
|
|
5898 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
|
|
|
5899 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
|
|
|
5900
|
|
|
5901 /**
|
|
|
5902 * @brief EXTI2 configuration
|
|
|
5903 */
|
|
|
5904 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
|
|
|
5905 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
|
|
|
5906 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
|
|
|
5907 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
|
|
|
5908 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
|
|
|
5909 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
|
|
|
5910 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
|
|
|
5911 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
|
|
|
5912 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
|
|
|
5913
|
|
|
5914 /**
|
|
|
5915 * @brief EXTI3 configuration
|
|
|
5916 */
|
|
|
5917 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
|
|
|
5918 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
|
|
|
5919 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
|
|
|
5920 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
|
|
|
5921 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
|
|
|
5922 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
|
|
|
5923 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
|
|
|
5924 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
|
|
|
5925 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
|
|
|
5926
|
|
|
5927 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
|
|
|
5928 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
|
|
|
5929 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
|
|
|
5930 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
|
|
|
5931 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
|
|
|
5932 /**
|
|
|
5933 * @brief EXTI4 configuration
|
|
|
5934 */
|
|
|
5935 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
|
|
|
5936 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
|
|
|
5937 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
|
|
|
5938 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
|
|
|
5939 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
|
|
|
5940 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
|
|
|
5941 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
|
|
|
5942 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
|
|
|
5943 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
|
|
|
5944
|
|
|
5945 /**
|
|
|
5946 * @brief EXTI5 configuration
|
|
|
5947 */
|
|
|
5948 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
|
|
|
5949 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
|
|
|
5950 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
|
|
|
5951 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
|
|
|
5952 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
|
|
|
5953 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
|
|
|
5954 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
|
|
|
5955 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
|
|
|
5956 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
|
|
|
5957
|
|
|
5958 /**
|
|
|
5959 * @brief EXTI6 configuration
|
|
|
5960 */
|
|
|
5961 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
|
|
|
5962 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
|
|
|
5963 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
|
|
|
5964 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
|
|
|
5965 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
|
|
|
5966 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
|
|
|
5967 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
|
|
|
5968 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
|
|
|
5969 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
|
|
|
5970
|
|
|
5971 /**
|
|
|
5972 * @brief EXTI7 configuration
|
|
|
5973 */
|
|
|
5974 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
|
|
|
5975 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
|
|
|
5976 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
|
|
|
5977 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
|
|
|
5978 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
|
|
|
5979 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
|
|
|
5980 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
|
|
|
5981 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
|
|
|
5982 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
|
|
|
5983
|
|
|
5984
|
|
|
5985 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
|
|
|
5986 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
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|
|
5987 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
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|
|
5988 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
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|
|
5989 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
|
|
|
5990
|
|
|
5991 /**
|
|
|
5992 * @brief EXTI8 configuration
|
|
|
5993 */
|
|
|
5994 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
|
|
|
5995 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
|
|
|
5996 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
|
|
|
5997 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
|
|
|
5998 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
|
|
|
5999 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
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|
|
6000 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
|
|
|
6001 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
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|
|
6002 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
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|
|
6003
|
|
|
6004 /**
|
|
|
6005 * @brief EXTI9 configuration
|
|
|
6006 */
|
|
|
6007 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
|
|
|
6008 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
|
|
|
6009 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
|
|
|
6010 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
|
|
|
6011 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
|
|
|
6012 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
|
|
|
6013 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
|
|
|
6014 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
|
|
|
6015 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
|
|
|
6016
|
|
|
6017 /**
|
|
|
6018 * @brief EXTI10 configuration
|
|
|
6019 */
|
|
|
6020 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
|
|
|
6021 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
|
|
|
6022 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
|
|
|
6023 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
|
|
|
6024 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
|
|
|
6025 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
|
|
|
6026 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
|
|
|
6027 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
|
|
|
6028 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
|
|
|
6029
|
|
|
6030 /**
|
|
|
6031 * @brief EXTI11 configuration
|
|
|
6032 */
|
|
|
6033 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
|
|
|
6034 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
|
|
|
6035 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
|
|
|
6036 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
|
|
|
6037 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
|
|
|
6038 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
|
|
|
6039 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
|
|
|
6040 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
|
|
|
6041 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
|
|
|
6042
|
|
|
6043 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
|
|
|
6044 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
|
|
|
6045 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
|
|
|
6046 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
|
|
|
6047 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
|
|
|
6048 /**
|
|
|
6049 * @brief EXTI12 configuration
|
|
|
6050 */
|
|
|
6051 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
|
|
|
6052 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
|
|
|
6053 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
|
|
|
6054 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
|
|
|
6055 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
|
|
|
6056 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
|
|
|
6057 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
|
|
|
6058 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
|
|
|
6059
|
|
|
6060 /**
|
|
|
6061 * @brief EXTI13 configuration
|
|
|
6062 */
|
|
|
6063 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
|
|
|
6064 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
|
|
|
6065 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
|
|
|
6066 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
|
|
|
6067 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
|
|
|
6068 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
|
|
|
6069 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
|
|
|
6070 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
|
|
|
6071
|
|
|
6072 /**
|
|
|
6073 * @brief EXTI14 configuration
|
|
|
6074 */
|
|
|
6075 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
|
|
|
6076 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
|
|
|
6077 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
|
|
|
6078 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
|
|
|
6079 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
|
|
|
6080 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
|
|
|
6081 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
|
|
|
6082 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
|
|
|
6083
|
|
|
6084 /**
|
|
|
6085 * @brief EXTI15 configuration
|
|
|
6086 */
|
|
|
6087 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
|
|
|
6088 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
|
|
|
6089 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
|
|
|
6090 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
|
|
|
6091 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
|
|
|
6092 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
|
|
|
6093 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
|
|
|
6094 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
|
|
|
6095
|
|
|
6096 /****************** Bit definition for SYSCFG_CMPCR register ****************/
|
|
|
6097 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
|
|
|
6098 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
|
|
|
6099
|
|
|
6100 /******************************************************************************/
|
|
|
6101 /* */
|
|
|
6102 /* TIM */
|
|
|
6103 /* */
|
|
|
6104 /******************************************************************************/
|
|
|
6105 /******************* Bit definition for TIM_CR1 register ********************/
|
|
|
6106 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
|
|
|
6107 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
|
|
|
6108 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
|
|
|
6109 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
|
|
|
6110 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
|
|
|
6111
|
|
|
6112 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
|
|
|
6113 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
|
|
|
6114 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
|
|
|
6115
|
|
|
6116 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
|
|
|
6117
|
|
|
6118 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
|
|
|
6119 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6120 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6121
|
|
|
6122 /******************* Bit definition for TIM_CR2 register ********************/
|
|
|
6123 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
|
|
|
6124 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
|
|
|
6125 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
|
|
|
6126
|
|
|
6127 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
|
|
|
6128 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6129 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6130 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6131
|
|
|
6132 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
|
|
|
6133 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
|
|
|
6134 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
|
|
|
6135 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
|
|
|
6136 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
|
|
|
6137 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
|
|
|
6138 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
|
|
|
6139 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
|
|
|
6140
|
|
|
6141 /******************* Bit definition for TIM_SMCR register *******************/
|
|
|
6142 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
|
|
|
6143 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6144 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6145 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
6146
|
|
|
6147 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
|
|
|
6148 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6149 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6150 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6151
|
|
|
6152 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
|
|
|
6153
|
|
|
6154 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
|
|
|
6155 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6156 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6157 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
6158 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
6159
|
|
|
6160 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
|
|
|
6161 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6162 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6163
|
|
|
6164 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
|
|
|
6165 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
|
|
|
6166
|
|
|
6167 /******************* Bit definition for TIM_DIER register *******************/
|
|
|
6168 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
|
|
|
6169 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
|
|
|
6170 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
|
|
|
6171 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
|
|
|
6172 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
|
|
|
6173 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
|
|
|
6174 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
|
|
|
6175 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
|
|
|
6176 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
|
|
|
6177 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
|
|
|
6178 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
|
|
|
6179 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
|
|
|
6180 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
|
|
|
6181 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
|
|
|
6182 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
|
|
|
6183
|
|
|
6184 /******************** Bit definition for TIM_SR register ********************/
|
|
|
6185 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
|
|
|
6186 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
|
|
|
6187 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
|
|
|
6188 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
|
|
|
6189 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
|
|
|
6190 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
|
|
|
6191 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
|
|
|
6192 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
|
|
|
6193 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
|
|
|
6194 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
|
|
|
6195 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
|
|
|
6196 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
|
|
|
6197
|
|
|
6198 /******************* Bit definition for TIM_EGR register ********************/
|
|
|
6199 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
|
|
|
6200 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
|
|
|
6201 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
|
|
|
6202 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
|
|
|
6203 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
|
|
|
6204 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
|
|
|
6205 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
|
|
|
6206 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
|
|
|
6207
|
|
|
6208 /****************** Bit definition for TIM_CCMR1 register *******************/
|
|
|
6209 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
|
|
|
6210 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6211 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6212
|
|
|
6213 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
|
|
|
6214 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
|
|
|
6215
|
|
|
6216 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
|
|
|
6217 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6218 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6219 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6220
|
|
|
6221 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
|
|
|
6222
|
|
|
6223 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
|
|
|
6224 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6225 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6226
|
|
|
6227 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
|
|
|
6228 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
|
|
|
6229
|
|
|
6230 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
|
|
|
6231 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6232 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6233 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
6234
|
|
|
6235 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
|
|
|
6236
|
|
|
6237 /*----------------------------------------------------------------------------*/
|
|
|
6238
|
|
|
6239 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
|
|
|
6240 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
6241 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
6242
|
|
|
6243 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
|
|
|
6244 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6245 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6246 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6247 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
6248
|
|
|
6249 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
|
|
|
6250 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
6251 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
6252
|
|
|
6253 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
|
|
|
6254 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6255 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6256 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
6257 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
6258
|
|
|
6259 /****************** Bit definition for TIM_CCMR2 register *******************/
|
|
|
6260 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
|
|
|
6261 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6262 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6263
|
|
|
6264 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
|
|
|
6265 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
|
|
|
6266
|
|
|
6267 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
|
|
|
6268 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6269 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6270 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6271
|
|
|
6272 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
|
|
|
6273
|
|
|
6274 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
|
|
|
6275 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6276 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6277
|
|
|
6278 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
|
|
|
6279 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
|
|
|
6280
|
|
|
6281 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
|
|
|
6282 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6283 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6284 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
6285
|
|
|
6286 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
|
|
|
6287
|
|
|
6288 /*----------------------------------------------------------------------------*/
|
|
|
6289
|
|
|
6290 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
|
|
|
6291 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
|
|
|
6292 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
|
|
|
6293
|
|
|
6294 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
|
|
|
6295 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
|
|
|
6296 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
|
|
|
6297 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
|
|
|
6298 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
|
|
|
6299
|
|
|
6300 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
|
|
|
6301 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
6302 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
6303
|
|
|
6304 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
|
|
|
6305 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6306 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6307 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
|
|
|
6308 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
|
|
|
6309
|
|
|
6310 /******************* Bit definition for TIM_CCER register *******************/
|
|
|
6311 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
|
|
|
6312 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
|
|
|
6313 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
|
|
|
6314 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
|
|
|
6315 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
|
|
|
6316 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
|
|
|
6317 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
|
|
|
6318 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
|
|
|
6319 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
|
|
|
6320 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
|
|
|
6321 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
|
|
|
6322 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
|
|
|
6323 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
|
|
|
6324 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
|
|
|
6325 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
|
|
|
6326
|
|
|
6327 /******************* Bit definition for TIM_CNT register ********************/
|
|
|
6328 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
|
|
|
6329
|
|
|
6330 /******************* Bit definition for TIM_PSC register ********************/
|
|
|
6331 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
|
|
|
6332
|
|
|
6333 /******************* Bit definition for TIM_ARR register ********************/
|
|
|
6334 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
|
|
|
6335
|
|
|
6336 /******************* Bit definition for TIM_RCR register ********************/
|
|
|
6337 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
|
|
|
6338
|
|
|
6339 /******************* Bit definition for TIM_CCR1 register *******************/
|
|
|
6340 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
|
|
|
6341
|
|
|
6342 /******************* Bit definition for TIM_CCR2 register *******************/
|
|
|
6343 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
|
|
|
6344
|
|
|
6345 /******************* Bit definition for TIM_CCR3 register *******************/
|
|
|
6346 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
|
|
|
6347
|
|
|
6348 /******************* Bit definition for TIM_CCR4 register *******************/
|
|
|
6349 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
|
|
|
6350
|
|
|
6351 /******************* Bit definition for TIM_BDTR register *******************/
|
|
|
6352 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
|
|
|
6353 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6354 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6355 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
6356 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
6357 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
6358 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
6359 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
6360 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
6361
|
|
|
6362 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
|
|
|
6363 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6364 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6365
|
|
|
6366 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
|
|
|
6367 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
|
|
|
6368 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
|
|
|
6369 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
|
|
|
6370 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
|
|
|
6371 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
|
|
|
6372
|
|
|
6373 /******************* Bit definition for TIM_DCR register ********************/
|
|
|
6374 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
|
|
|
6375 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6376 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6377 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
6378 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
6379 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
6380
|
|
|
6381 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
|
|
|
6382 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
|
|
|
6383 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
|
|
|
6384 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
|
|
|
6385 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
|
|
|
6386 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
|
|
|
6387
|
|
|
6388 /******************* Bit definition for TIM_DMAR register *******************/
|
|
|
6389 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
|
|
|
6390
|
|
|
6391 /******************* Bit definition for TIM_OR register *********************/
|
|
|
6392 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
|
|
|
6393 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
|
|
|
6394 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
|
|
|
6395 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
|
|
|
6396 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
|
|
|
6397 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
|
|
|
6398
|
|
|
6399
|
|
|
6400 /******************************************************************************/
|
|
|
6401 /* */
|
|
|
6402 /* Universal Synchronous Asynchronous Receiver Transmitter */
|
|
|
6403 /* */
|
|
|
6404 /******************************************************************************/
|
|
|
6405 /******************* Bit definition for USART_SR register *******************/
|
|
|
6406 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
|
|
|
6407 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
|
|
|
6408 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
|
|
|
6409 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
|
|
|
6410 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
|
|
|
6411 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
|
|
|
6412 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
|
|
|
6413 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
|
|
|
6414 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
|
|
|
6415 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
|
|
|
6416
|
|
|
6417 /******************* Bit definition for USART_DR register *******************/
|
|
|
6418 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
|
|
|
6419
|
|
|
6420 /****************** Bit definition for USART_BRR register *******************/
|
|
|
6421 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
|
|
|
6422 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
|
|
|
6423
|
|
|
6424 /****************** Bit definition for USART_CR1 register *******************/
|
|
|
6425 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
|
|
|
6426 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
|
|
|
6427 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
|
|
|
6428 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
|
|
|
6429 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
|
|
|
6430 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
|
|
|
6431 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
|
|
|
6432 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
|
|
|
6433 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
|
|
|
6434 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
|
|
|
6435 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
|
|
|
6436 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
|
|
|
6437 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
|
|
|
6438 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
|
|
|
6439 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
|
|
|
6440
|
|
|
6441 /****************** Bit definition for USART_CR2 register *******************/
|
|
|
6442 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
|
|
|
6443 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
|
|
|
6444 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
|
|
|
6445 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
|
|
|
6446 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
|
|
|
6447 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
|
|
|
6448 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
|
|
|
6449
|
|
|
6450 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
|
|
|
6451 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
|
|
|
6452 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
|
|
|
6453
|
|
|
6454 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
|
|
|
6455
|
|
|
6456 /****************** Bit definition for USART_CR3 register *******************/
|
|
|
6457 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
|
|
|
6458 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
|
|
|
6459 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
|
|
|
6460 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
|
|
|
6461 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
|
|
|
6462 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
|
|
|
6463 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
|
|
|
6464 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
|
|
|
6465 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
|
|
|
6466 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
|
|
|
6467 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
|
|
|
6468 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
|
|
|
6469
|
|
|
6470 /****************** Bit definition for USART_GTPR register ******************/
|
|
|
6471 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
|
|
6472 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6473 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6474 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
6475 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
6476 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
6477 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
6478 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
6479 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
|
|
|
6480
|
|
|
6481 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
|
|
|
6482
|
|
|
6483 /******************************************************************************/
|
|
|
6484 /* */
|
|
|
6485 /* Window WATCHDOG */
|
|
|
6486 /* */
|
|
|
6487 /******************************************************************************/
|
|
|
6488 /******************* Bit definition for WWDG_CR register ********************/
|
|
|
6489 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
|
|
|
6490 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
|
|
|
6491 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
|
|
|
6492 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
|
|
|
6493 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
|
|
|
6494 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
|
|
|
6495 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
|
|
|
6496 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
|
|
|
6497
|
|
|
6498 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
|
|
|
6499
|
|
|
6500 /******************* Bit definition for WWDG_CFR register *******************/
|
|
|
6501 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
|
|
|
6502 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
|
|
|
6503 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
|
|
|
6504 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
|
|
|
6505 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
|
|
|
6506 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
|
|
|
6507 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
|
|
|
6508 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
|
|
|
6509
|
|
|
6510 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
|
|
|
6511 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
|
|
|
6512 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
|
|
|
6513
|
|
|
6514 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
|
|
|
6515
|
|
|
6516 /******************* Bit definition for WWDG_SR register ********************/
|
|
|
6517 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
|
|
|
6518
|
|
|
6519
|
|
|
6520 /******************************************************************************/
|
|
|
6521 /* */
|
|
|
6522 /* DBG */
|
|
|
6523 /* */
|
|
|
6524 /******************************************************************************/
|
|
|
6525 /******************** Bit definition for DBGMCU_IDCODE register *************/
|
|
|
6526 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
|
|
|
6527 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
|
|
|
6528
|
|
|
6529 /******************** Bit definition for DBGMCU_CR register *****************/
|
|
|
6530 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
|
|
|
6531 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
|
|
|
6532 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
|
|
|
6533 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
|
|
|
6534
|
|
|
6535 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
|
|
|
6536 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
|
|
|
6537 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
|
|
|
6538
|
|
|
6539 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
|
|
|
6540 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
|
|
|
6541 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
|
|
|
6542 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
|
|
|
6543 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
|
|
|
6544 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
|
|
|
6545 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
|
|
|
6546 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
|
|
|
6547 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
|
|
|
6548 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
|
|
|
6549 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
|
|
|
6550 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
|
|
|
6551 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
|
|
|
6552 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
|
|
6553 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
|
|
6554 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
|
|
|
6555 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
|
|
|
6556 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
|
|
|
6557 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
|
|
|
6558 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
|
|
|
6559
|
|
|
6560 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
|
|
|
6561 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
|
|
|
6562 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
|
|
|
6563 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
|
|
|
6564 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
|
|
|
6565 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
|
|
|
6566
|
|
|
6567 /******************************************************************************/
|
|
|
6568 /* */
|
|
|
6569 /* Ethernet MAC Registers bits definitions */
|
|
|
6570 /* */
|
|
|
6571 /******************************************************************************/
|
|
|
6572 /* Bit definition for Ethernet MAC Control Register register */
|
|
|
6573 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
|
|
|
6574 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
|
|
|
6575 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
|
|
|
6576 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
|
|
|
6577 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
|
|
|
6578 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
|
|
|
6579 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
|
|
|
6580 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
|
|
|
6581 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
|
|
|
6582 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
|
|
|
6583 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
|
|
|
6584 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
|
|
|
6585 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
|
|
|
6586 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
|
|
|
6587 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
|
|
|
6588 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
|
|
|
6589 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
|
|
|
6590 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
|
|
|
6591 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
|
|
|
6592 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
|
|
|
6593 a transmission attempt during retries after a collision: 0 =< r <2^k */
|
|
|
6594 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
|
|
|
6595 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
|
|
|
6596 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
|
|
|
6597 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
|
|
|
6598 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
|
|
|
6599 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
|
|
|
6600 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
|
|
|
6601
|
|
|
6602 /* Bit definition for Ethernet MAC Frame Filter Register */
|
|
|
6603 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
|
|
|
6604 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
|
|
|
6605 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
|
|
|
6606 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
|
|
|
6607 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
|
|
|
6608 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
|
|
|
6609 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
|
|
|
6610 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
|
|
|
6611 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
|
|
|
6612 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
|
|
|
6613 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
|
|
|
6614 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
|
|
|
6615 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
|
|
|
6616 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
|
|
|
6617
|
|
|
6618 /* Bit definition for Ethernet MAC Hash Table High Register */
|
|
|
6619 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
|
|
|
6620
|
|
|
6621 /* Bit definition for Ethernet MAC Hash Table Low Register */
|
|
|
6622 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
|
|
|
6623
|
|
|
6624 /* Bit definition for Ethernet MAC MII Address Register */
|
|
|
6625 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
|
|
|
6626 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
|
|
|
6627 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
|
|
|
6628 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
|
|
|
6629 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
|
|
|
6630 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
|
|
|
6631 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
|
|
|
6632 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
|
|
|
6633 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
|
|
|
6634 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
|
|
|
6635
|
|
|
6636 /* Bit definition for Ethernet MAC MII Data Register */
|
|
|
6637 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
|
|
|
6638
|
|
|
6639 /* Bit definition for Ethernet MAC Flow Control Register */
|
|
|
6640 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
|
|
|
6641 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
|
|
|
6642 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
|
|
|
6643 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
|
|
|
6644 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
|
|
|
6645 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
|
|
|
6646 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
|
|
|
6647 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
|
|
|
6648 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
|
|
|
6649 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
|
|
|
6650 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
|
|
|
6651
|
|
|
6652 /* Bit definition for Ethernet MAC VLAN Tag Register */
|
|
|
6653 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
|
|
|
6654 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
|
|
|
6655
|
|
|
6656 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
|
|
|
6657 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
|
|
|
6658 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
|
|
|
6659 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
|
|
|
6660 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
|
|
|
6661 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
|
|
|
6662 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
|
|
|
6663 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
|
|
|
6664 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
|
|
|
6665 RSVD - Filter1 Command - RSVD - Filter0 Command
|
|
|
6666 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
|
|
|
6667 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
|
|
|
6668 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
|
|
|
6669
|
|
|
6670 /* Bit definition for Ethernet MAC PMT Control and Status Register */
|
|
|
6671 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
|
|
|
6672 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
|
|
|
6673 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
|
|
|
6674 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
|
|
|
6675 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
|
|
|
6676 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
|
|
|
6677 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
|
|
|
6678
|
|
|
6679 /* Bit definition for Ethernet MAC Status Register */
|
|
|
6680 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
|
|
|
6681 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
|
|
|
6682 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
|
|
|
6683 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
|
|
|
6684 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
|
|
|
6685
|
|
|
6686 /* Bit definition for Ethernet MAC Interrupt Mask Register */
|
|
|
6687 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
|
|
|
6688 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
|
|
|
6689
|
|
|
6690 /* Bit definition for Ethernet MAC Address0 High Register */
|
|
|
6691 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
|
|
|
6692
|
|
|
6693 /* Bit definition for Ethernet MAC Address0 Low Register */
|
|
|
6694 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
|
|
|
6695
|
|
|
6696 /* Bit definition for Ethernet MAC Address1 High Register */
|
|
|
6697 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
6698 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
6699 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
|
|
|
6700 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
6701 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
6702 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
6703 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
6704 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
6705 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
|
|
|
6706 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
|
|
6707
|
|
|
6708 /* Bit definition for Ethernet MAC Address1 Low Register */
|
|
|
6709 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
|
|
|
6710
|
|
|
6711 /* Bit definition for Ethernet MAC Address2 High Register */
|
|
|
6712 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
6713 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
6714 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
|
|
6715 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
6716 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
6717 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
6718 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
6719 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
6720 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
|
|
6721 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
|
|
|
6722
|
|
|
6723 /* Bit definition for Ethernet MAC Address2 Low Register */
|
|
|
6724 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
|
|
|
6725
|
|
|
6726 /* Bit definition for Ethernet MAC Address3 High Register */
|
|
|
6727 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
|
|
|
6728 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
|
|
|
6729 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
|
|
|
6730 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
|
|
|
6731 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
|
|
|
6732 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
|
|
|
6733 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
|
|
|
6734 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
|
|
|
6735 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
|
|
|
6736 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
|
|
|
6737
|
|
|
6738 /* Bit definition for Ethernet MAC Address3 Low Register */
|
|
|
6739 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
|
|
|
6740
|
|
|
6741 /******************************************************************************/
|
|
|
6742 /* Ethernet MMC Registers bits definition */
|
|
|
6743 /******************************************************************************/
|
|
|
6744
|
|
|
6745 /* Bit definition for Ethernet MMC Contol Register */
|
|
|
6746 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
|
|
|
6747 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
|
|
|
6748 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
|
|
|
6749 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
|
|
|
6750 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
|
|
|
6751 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
|
|
|
6752
|
|
|
6753 /* Bit definition for Ethernet MMC Receive Interrupt Register */
|
|
|
6754 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
|
|
|
6755 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
|
|
|
6756 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
|
|
|
6757
|
|
|
6758 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
|
|
|
6759 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
|
|
|
6760 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
|
|
|
6761 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
|
|
|
6762
|
|
|
6763 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
|
|
|
6764 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
|
|
|
6765 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
|
|
|
6766 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
|
|
|
6767
|
|
|
6768 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
|
|
|
6769 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
|
|
|
6770 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
|
|
|
6771 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
|
|
|
6772
|
|
|
6773 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
|
|
|
6774 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
|
|
|
6775
|
|
|
6776 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
|
|
|
6777 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
|
|
|
6778
|
|
|
6779 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
|
|
|
6780 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
|
|
|
6781
|
|
|
6782 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
|
|
|
6783 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
|
|
|
6784
|
|
|
6785 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
|
|
|
6786 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
|
|
|
6787
|
|
|
6788 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
|
|
|
6789 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
|
|
|
6790
|
|
|
6791 /******************************************************************************/
|
|
|
6792 /* Ethernet PTP Registers bits definition */
|
|
|
6793 /******************************************************************************/
|
|
|
6794
|
|
|
6795 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
|
|
|
6796 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
|
|
|
6797 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
|
|
|
6798 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
|
|
|
6799 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
|
|
|
6800 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
|
|
|
6801 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
|
|
|
6802 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
|
|
|
6803 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
|
|
|
6804 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
|
|
|
6805
|
|
|
6806 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
|
|
|
6807 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
|
|
|
6808 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
|
|
|
6809 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
|
|
|
6810 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
|
|
|
6811 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
|
|
|
6812
|
|
|
6813 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
|
|
|
6814 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
|
|
|
6815
|
|
|
6816 /* Bit definition for Ethernet PTP Time Stamp High Register */
|
|
|
6817 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
|
|
|
6818
|
|
|
6819 /* Bit definition for Ethernet PTP Time Stamp Low Register */
|
|
|
6820 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
|
|
|
6821 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
|
|
|
6822
|
|
|
6823 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
|
|
|
6824 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
|
|
|
6825
|
|
|
6826 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
|
|
|
6827 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
|
|
|
6828 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
|
|
|
6829
|
|
|
6830 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
|
|
|
6831 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
|
|
|
6832
|
|
|
6833 /* Bit definition for Ethernet PTP Target Time High Register */
|
|
|
6834 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
|
|
|
6835
|
|
|
6836 /* Bit definition for Ethernet PTP Target Time Low Register */
|
|
|
6837 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
|
|
|
6838
|
|
|
6839 /* Bit definition for Ethernet PTP Time Stamp Status Register */
|
|
|
6840 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
|
|
|
6841 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
|
|
|
6842
|
|
|
6843 /******************************************************************************/
|
|
|
6844 /* Ethernet DMA Registers bits definition */
|
|
|
6845 /******************************************************************************/
|
|
|
6846
|
|
|
6847 /* Bit definition for Ethernet DMA Bus Mode Register */
|
|
|
6848 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
|
|
|
6849 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
|
|
|
6850 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
|
|
|
6851 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
|
|
|
6852 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
|
|
|
6853 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
|
|
|
6854 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
6855 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
6856 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
6857 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
6858 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
|
|
|
6859 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
|
|
|
6860 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
|
|
|
6861 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
|
|
|
6862 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
|
|
|
6863 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
|
|
|
6864 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
|
|
|
6865 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
|
|
6866 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
|
|
|
6867 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
|
|
|
6868 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
|
|
|
6869 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
|
|
|
6870 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
|
|
|
6871 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
|
|
|
6872 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
|
|
|
6873 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
6874 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
6875 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
6876 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
6877 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
|
|
|
6878 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
|
|
|
6879 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
|
|
|
6880 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
|
|
|
6881 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
|
|
|
6882 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
|
|
|
6883 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
|
|
|
6884 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
|
|
|
6885 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
|
|
|
6886 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
|
|
|
6887
|
|
|
6888 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
|
|
|
6889 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
|
|
|
6890
|
|
|
6891 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
|
|
|
6892 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
|
|
|
6893
|
|
|
6894 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
|
|
|
6895 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
|
|
|
6896
|
|
|
6897 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
|
|
|
6898 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
|
|
|
6899
|
|
|
6900 /* Bit definition for Ethernet DMA Status Register */
|
|
|
6901 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
|
|
|
6902 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
|
|
|
6903 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
|
|
|
6904 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
|
|
|
6905 /* combination with EBS[2:0] for GetFlagStatus function */
|
|
|
6906 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
|
|
|
6907 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
|
|
|
6908 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
|
|
|
6909 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
|
|
|
6910 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
|
|
|
6911 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
|
|
|
6912 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
|
|
|
6913 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
|
|
|
6914 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
|
|
|
6915 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
|
|
|
6916 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
|
|
|
6917 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
|
|
|
6918 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
|
|
|
6919 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
|
|
|
6920 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
|
|
|
6921 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
|
|
|
6922 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
|
|
|
6923 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
|
|
|
6924 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
|
|
|
6925 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
|
|
|
6926 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
|
|
|
6927 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
|
|
|
6928 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
|
|
|
6929 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
|
|
|
6930 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
|
|
|
6931 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
|
|
|
6932 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
|
|
|
6933 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
|
|
|
6934 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
|
|
|
6935 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
|
|
|
6936 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
|
|
|
6937 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
|
|
|
6938
|
|
|
6939 /* Bit definition for Ethernet DMA Operation Mode Register */
|
|
|
6940 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
|
|
|
6941 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
|
|
|
6942 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
|
|
|
6943 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
|
|
|
6944 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
|
|
|
6945 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
|
|
|
6946 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
|
|
|
6947 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
|
|
|
6948 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
|
|
|
6949 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
|
|
|
6950 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
|
|
|
6951 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
|
|
|
6952 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
|
|
|
6953 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
|
|
|
6954 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
|
|
|
6955 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
|
|
|
6956 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
|
|
|
6957 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
|
|
|
6958 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
|
|
|
6959 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
|
|
|
6960 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
|
|
|
6961 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
|
|
|
6962 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
|
|
|
6963 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
|
|
|
6964
|
|
|
6965 /* Bit definition for Ethernet DMA Interrupt Enable Register */
|
|
|
6966 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
|
|
|
6967 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
|
|
|
6968 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
|
|
|
6969 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
|
|
|
6970 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
|
|
|
6971 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
|
|
|
6972 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
|
|
|
6973 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
|
|
|
6974 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
|
|
|
6975 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
|
|
|
6976 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
|
|
|
6977 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
|
|
|
6978 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
|
|
|
6979 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
|
|
|
6980 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
|
|
|
6981
|
|
|
6982 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
|
|
|
6983 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
|
|
|
6984 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
|
|
|
6985 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
|
|
|
6986 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
|
|
|
6987
|
|
|
6988 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
|
|
|
6989 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
|
|
|
6990
|
|
|
6991 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
|
|
|
6992 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
|
|
|
6993
|
|
|
6994 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
|
|
|
6995 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
|
|
|
6996
|
|
|
6997 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
|
|
|
6998 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
|
|
|
6999
|
|
|
7000 /******************************************************************************/
|
|
|
7001 /* */
|
|
|
7002 /* USB_OTG */
|
|
|
7003 /* */
|
|
|
7004 /******************************************************************************/
|
|
|
7005 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
|
|
|
7006 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
|
|
|
7007 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
|
|
|
7008 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
|
|
|
7009 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
|
|
|
7010 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
|
|
|
7011 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
|
|
|
7012 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
|
|
|
7013 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
|
|
|
7014 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
|
|
|
7015 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
|
|
|
7016
|
|
|
7017 /******************** Bit definition forUSB_OTG_HCFG register ********************/
|
|
|
7018
|
|
|
7019 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
|
|
|
7020 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7021 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7022 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
|
|
|
7023
|
|
|
7024 /******************** Bit definition forUSB_OTG_DCFG register ********************/
|
|
|
7025
|
|
|
7026 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
|
|
|
7027 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7028 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7029 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
|
|
|
7030
|
|
|
7031 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
|
|
|
7032 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
7033 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
7034 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
7035 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
|
|
|
7036 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
|
|
|
7037 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
|
|
|
7038 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
|
|
|
7039
|
|
|
7040 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
|
|
|
7041 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
7042 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
7043
|
|
|
7044 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
|
|
|
7045 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
7046 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
7047
|
|
|
7048 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
|
|
|
7049 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
|
|
|
7050 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
|
|
|
7051 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
|
|
|
7052
|
|
|
7053 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
|
|
|
7054 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
|
|
|
7055 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
|
|
|
7056 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
|
|
|
7057 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
|
|
|
7058 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
|
|
|
7059 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
|
|
|
7060
|
|
|
7061 /******************** Bit definition forUSB_OTG_DCTL register ********************/
|
|
|
7062 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
|
|
|
7063 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
|
|
|
7064 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
|
|
|
7065 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
|
|
|
7066
|
|
|
7067 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
|
|
|
7068 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
|
|
|
7069 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
|
|
|
7070 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
|
|
|
7071 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
|
|
|
7072 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
|
|
|
7073 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
|
|
|
7074 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
|
|
|
7075 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
|
|
|
7076
|
|
|
7077 /******************** Bit definition forUSB_OTG_HFIR register ********************/
|
|
|
7078 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
|
|
|
7079
|
|
|
7080 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
|
|
|
7081 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
|
|
|
7082 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
|
|
|
7083
|
|
|
7084 /******************** Bit definition forUSB_OTG_DSTS register ********************/
|
|
|
7085 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
|
|
|
7086
|
|
|
7087 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
|
|
|
7088 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
7089 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
7090 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
|
|
|
7091 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
|
|
|
7092
|
|
|
7093 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
|
|
|
7094 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
|
|
|
7095
|
|
|
7096 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
|
|
|
7097 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
7098 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
|
|
|
7099 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
|
|
|
7100 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
|
|
|
7101 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
|
|
|
7102 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
|
|
|
7103 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
|
|
|
7104
|
|
|
7105 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
|
|
|
7106
|
|
|
7107 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
|
|
|
7108 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7109 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7110 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7111 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
|
|
|
7112 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
|
|
|
7113 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
|
|
|
7114
|
|
|
7115 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
|
|
|
7116 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
7117 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
7118 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
|
|
|
7119 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
|
|
|
7120 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
|
|
|
7121 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
|
|
|
7122 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
|
|
|
7123 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
|
|
|
7124 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
|
|
|
7125 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
|
|
|
7126 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
|
|
|
7127 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
|
|
|
7128 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
|
|
|
7129 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
|
|
|
7130 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
|
|
|
7131 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
|
|
|
7132 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
|
|
|
7133
|
|
|
7134 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
|
|
7135 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
|
|
|
7136 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
|
|
|
7137 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
|
|
|
7138 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
|
|
|
7139 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
|
|
|
7140
|
|
|
7141 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
|
|
|
7142 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
|
|
|
7143 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
|
|
|
7144 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
|
|
|
7145 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
|
|
|
7146 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
|
|
|
7147 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
|
|
|
7148 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
|
|
|
7149
|
|
|
7150 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
|
|
|
7151 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
7152 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
7153 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
7154 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
7155 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
7156 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
7157 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
7158 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
7159
|
|
|
7160 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
|
|
|
7161 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
|
|
|
7162
|
|
|
7163 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
|
|
|
7164 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
7165 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
7166 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
7167 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
7168 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
7169 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
7170 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
7171 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
7172
|
|
|
7173 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
|
|
|
7174 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
7175 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
7176 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
7177 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
7178 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
7179 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
7180 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
7181 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
|
|
|
7182
|
|
|
7183 /******************** Bit definition forUSB_OTG_HAINT register ********************/
|
|
|
7184 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
|
|
|
7185
|
|
|
7186 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
|
|
|
7187 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
7188 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
7189 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
|
|
|
7190 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
|
|
|
7191 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
|
|
|
7192 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
7193 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
7194
|
|
|
7195 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
|
|
|
7196 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
|
|
|
7197 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
|
|
|
7198 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
|
|
|
7199 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
|
|
|
7200 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
|
|
|
7201 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
|
|
|
7202 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
|
|
|
7203 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
|
|
|
7204 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
|
|
|
7205 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
|
|
|
7206 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
|
|
|
7207 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
|
|
|
7208 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
|
|
|
7209 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
|
|
|
7210 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
|
|
|
7211 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
|
|
|
7212 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
|
|
|
7213 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
|
|
|
7214 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
|
|
|
7215 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
|
|
|
7216 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
|
|
|
7217 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
|
|
|
7218 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
|
|
|
7219 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
|
|
|
7220 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
|
|
|
7221 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
|
|
|
7222
|
|
|
7223 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
|
|
|
7224 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
|
|
|
7225 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
|
|
|
7226 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
|
|
|
7227 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
|
|
|
7228 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
|
|
|
7229 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
|
|
|
7230 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
|
|
|
7231 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
|
|
|
7232 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
|
|
|
7233 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
|
|
|
7234 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
|
|
|
7235 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
|
|
|
7236 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
|
|
|
7237 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
|
|
|
7238 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
|
|
|
7239 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
|
|
|
7240 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
|
|
|
7241 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
|
|
|
7242 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
|
|
|
7243 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
|
|
|
7244 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
|
|
|
7245 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
|
|
|
7246 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
|
|
|
7247 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
|
|
|
7248 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
|
|
|
7249 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
|
|
|
7250
|
|
|
7251 /******************** Bit definition forUSB_OTG_DAINT register ********************/
|
|
|
7252 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
|
|
|
7253 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
|
|
|
7254
|
|
|
7255 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
|
|
|
7256 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
|
|
|
7257
|
|
|
7258 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
|
|
|
7259 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
|
|
|
7260 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
|
|
|
7261 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
|
|
|
7262 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
|
|
|
7263
|
|
|
7264 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
|
|
|
7265 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
|
|
|
7266 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
|
|
|
7267
|
|
|
7268 /******************** Bit definition for OTG register ********************/
|
|
|
7269
|
|
|
7270 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
7271 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7272 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7273 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7274 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
7275 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
7276
|
|
|
7277 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
7278 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
7279 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
7280
|
|
|
7281 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
7282 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
7283 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
7284 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
7285 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
7286
|
|
|
7287 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
7288 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7289 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7290 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7291 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
7292
|
|
|
7293 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
7294 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
7295 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
7296 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
7297 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
7298
|
|
|
7299 /******************** Bit definition for OTG register ********************/
|
|
|
7300
|
|
|
7301 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
|
|
|
7302 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7303 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7304 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7305 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
7306 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
|
|
|
7307
|
|
|
7308 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
|
|
|
7309 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
|
|
|
7310 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
|
|
|
7311
|
|
|
7312 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
|
|
|
7313 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
7314 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
7315 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
7316 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
7317
|
|
|
7318 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
|
|
|
7319 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7320 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7321 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7322 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
7323
|
|
|
7324 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
|
|
|
7325 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
|
|
|
7326 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
|
|
|
7327 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
|
|
|
7328 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
|
|
|
7329
|
|
|
7330 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
|
|
|
7331 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
|
|
|
7332
|
|
|
7333 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
|
|
|
7334 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
|
|
|
7335
|
|
|
7336 /******************** Bit definition for OTG register ********************/
|
|
|
7337 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
|
|
|
7338 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
|
|
|
7339 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
|
|
|
7340 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
|
|
|
7341
|
|
|
7342 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
|
|
|
7343 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
|
|
|
7344
|
|
|
7345 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
|
|
|
7346 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
|
|
|
7347
|
|
|
7348 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
|
|
|
7349 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
|
|
|
7350 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
|
|
|
7351 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
|
|
|
7352 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
|
|
|
7353 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
|
|
|
7354 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
|
|
|
7355 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
|
|
|
7356 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
|
|
|
7357
|
|
|
7358 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
|
|
|
7359 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
|
|
|
7360 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
|
|
|
7361 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
|
|
|
7362 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
|
|
|
7363 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
|
|
|
7364 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
|
|
|
7365 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
|
|
|
7366
|
|
|
7367 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
|
|
|
7368 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
|
|
|
7369 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
|
|
|
7370
|
|
|
7371 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
|
|
|
7372 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
|
|
|
7373 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
|
|
|
7374 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
|
|
|
7375 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
|
|
|
7376 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
|
|
|
7377 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
|
|
|
7378 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
|
|
|
7379 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
|
|
|
7380 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
|
|
|
7381 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
|
|
|
7382
|
|
|
7383 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
|
|
|
7384 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
7385 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
7386 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
|
|
|
7387 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
|
|
|
7388 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
|
|
|
7389 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
|
|
|
7390 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
|
|
|
7391 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
|
|
|
7392 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
|
|
|
7393 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
|
|
|
7394
|
|
|
7395 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
|
|
|
7396 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
|
|
|
7397
|
|
|
7398 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
|
|
|
7399 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
|
|
|
7400 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
|
|
|
7401
|
|
|
7402 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
|
|
|
7403 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
|
|
|
7404 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
|
|
|
7405 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
|
|
|
7406 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
|
|
|
7407 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
|
|
|
7408 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
|
|
|
7409
|
|
|
7410 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
|
|
|
7411 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
|
|
|
7412 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
|
|
|
7413
|
|
|
7414 /******************** Bit definition forUSB_OTG_CID register ********************/
|
|
|
7415 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
|
|
|
7416
|
|
|
7417 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
|
|
|
7418 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
7419 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
7420 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
|
|
|
7421 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
7422 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
7423 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
7424 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
|
|
|
7425 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
7426 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
7427
|
|
|
7428 /******************** Bit definition forUSB_OTG_HPRT register ********************/
|
|
|
7429 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
|
|
|
7430 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
|
|
|
7431 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
|
|
|
7432 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
|
|
|
7433 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
|
|
|
7434 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
|
|
|
7435 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
|
|
|
7436 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
|
|
|
7437 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
|
|
|
7438
|
|
|
7439 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
|
|
|
7440 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
|
|
|
7441 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
|
|
|
7442 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
|
|
|
7443
|
|
|
7444 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
|
|
|
7445 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
|
|
|
7446 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
|
|
|
7447 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
|
|
|
7448 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
|
|
|
7449
|
|
|
7450 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
|
|
|
7451 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
|
|
|
7452 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
|
|
|
7453
|
|
|
7454 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
|
|
|
7455 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
|
|
|
7456 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
|
|
|
7457 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
|
|
|
7458 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
|
|
|
7459 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
|
|
|
7460 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
|
|
|
7461 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
|
|
|
7462 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
|
|
|
7463 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
|
|
|
7464 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
|
|
|
7465 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
|
|
|
7466
|
|
|
7467 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
|
|
|
7468 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
|
|
|
7469 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
|
|
|
7470
|
|
|
7471 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
|
|
|
7472 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
7473 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
7474 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
|
|
|
7475 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
7476
|
|
|
7477 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
7478 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
7479 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
7480 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
7481
|
|
|
7482 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
|
|
|
7483 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
7484 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
7485 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
7486 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
7487 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
7488 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
7489 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
7490 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
7491 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
7492 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
7493
|
|
|
7494 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
|
|
|
7495 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
|
|
|
7496
|
|
|
7497 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
|
|
|
7498 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
|
|
|
7499 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
|
|
|
7500 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
|
|
|
7501 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
|
|
|
7502 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
|
|
|
7503 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
|
|
|
7504
|
|
|
7505 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
7506 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
7507 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
7508
|
|
|
7509 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
|
|
|
7510 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
|
|
|
7511 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
|
|
|
7512
|
|
|
7513 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
|
|
|
7514 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
|
|
|
7515 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
|
|
|
7516 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
|
|
|
7517 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
|
|
|
7518 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
|
|
|
7519 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
|
|
|
7520 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
|
|
|
7521 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
|
|
|
7522 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
|
|
|
7523 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
|
|
|
7524
|
|
|
7525 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
|
|
|
7526
|
|
|
7527 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
|
|
|
7528 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
|
|
|
7529 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
|
|
|
7530 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
|
|
|
7531 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
|
|
|
7532 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
|
|
|
7533 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
|
|
|
7534 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
|
|
|
7535
|
|
|
7536 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
|
|
|
7537 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
|
|
|
7538 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
|
|
|
7539 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
|
|
|
7540 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
|
|
|
7541 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
|
|
|
7542 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
|
|
|
7543 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
|
|
|
7544
|
|
|
7545 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
|
|
|
7546 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
|
|
|
7547 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
|
|
|
7548 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
|
|
|
7549 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
|
|
|
7550
|
|
|
7551 /******************** Bit definition forUSB_OTG_HCINT register ********************/
|
|
|
7552 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
|
|
|
7553 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
|
|
|
7554 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
7555 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
|
|
|
7556 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
|
|
|
7557 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
|
|
|
7558 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
|
|
|
7559 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
|
|
|
7560 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
|
|
|
7561 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
|
|
|
7562 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
|
|
|
7563
|
|
|
7564 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
|
|
|
7565 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
7566 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
7567 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
|
|
|
7568 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
|
|
|
7569 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
|
|
|
7570 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
|
|
|
7571 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
|
|
|
7572 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
|
|
|
7573 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
|
|
|
7574 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
|
|
|
7575 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
|
|
|
7576
|
|
|
7577 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
|
|
|
7578 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
|
|
|
7579 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
|
|
|
7580 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
|
|
|
7581 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
|
|
|
7582 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
|
|
|
7583 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
|
|
|
7584 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
|
|
|
7585 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
|
|
|
7586 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
|
|
|
7587 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
|
|
|
7588 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
|
|
|
7589
|
|
|
7590 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
|
|
|
7591
|
|
|
7592 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
7593 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
7594 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
|
|
|
7595 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
|
|
|
7596 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
7597 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
7598 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
|
|
|
7599 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
|
|
|
7600 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
7601 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
7602
|
|
|
7603 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
|
|
|
7604 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
7605
|
|
|
7606 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
|
|
|
7607 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
|
|
|
7608
|
|
|
7609 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
|
|
|
7610 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
|
|
|
7611
|
|
|
7612 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
|
|
|
7613 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
|
|
|
7614 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
|
|
|
7615
|
|
|
7616 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
|
|
|
7617
|
|
|
7618 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
|
|
|
7619 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
|
|
|
7620 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
|
|
|
7621 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
|
|
|
7622 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
|
|
|
7623 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
|
|
|
7624 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
|
|
|
7625 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
|
|
|
7626 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
|
|
|
7627 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
|
|
|
7628 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
|
|
|
7629 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
|
|
|
7630 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
|
|
|
7631 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
|
|
|
7632
|
|
|
7633 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
|
|
|
7634 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
|
|
|
7635 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
|
|
|
7636 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
|
|
|
7637 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
|
|
|
7638 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
|
|
|
7639 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
|
|
|
7640
|
|
|
7641 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
|
|
|
7642
|
|
|
7643 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
|
|
|
7644 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
|
|
|
7645
|
|
|
7646 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
|
|
|
7647 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
|
|
|
7648 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
|
|
|
7649
|
|
|
7650 /******************** Bit definition for PCGCCTL register ********************/
|
|
|
7651 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
|
|
|
7652 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
|
|
|
7653 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
|
|
|
7654
|
|
|
7655 /**
|
|
|
7656 * @}
|
|
|
7657 */
|
|
|
7658
|
|
|
7659 /**
|
|
|
7660 * @}
|
|
|
7661 */
|
|
|
7662
|
|
|
7663 /** @addtogroup Exported_macros
|
|
|
7664 * @{
|
|
|
7665 */
|
|
|
7666
|
|
|
7667 /******************************* ADC Instances ********************************/
|
|
|
7668 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
|
|
|
7669 ((INSTANCE) == ADC2) || \
|
|
|
7670 ((INSTANCE) == ADC3))
|
|
|
7671
|
|
|
7672 /******************************* CAN Instances ********************************/
|
|
|
7673 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
|
|
|
7674 ((INSTANCE) == CAN2))
|
|
|
7675
|
|
|
7676 /******************************* CRC Instances ********************************/
|
|
|
7677 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
|
|
|
7678
|
|
|
7679 /******************************* DAC Instances ********************************/
|
|
|
7680 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
|
|
|
7681
|
|
|
7682 /******************************* DCMI Instances *******************************/
|
|
|
7683 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
|
|
|
7684
|
|
|
7685 /******************************** DMA Instances *******************************/
|
|
|
7686 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
|
|
|
7687 ((INSTANCE) == DMA1_Stream1) || \
|
|
|
7688 ((INSTANCE) == DMA1_Stream2) || \
|
|
|
7689 ((INSTANCE) == DMA1_Stream3) || \
|
|
|
7690 ((INSTANCE) == DMA1_Stream4) || \
|
|
|
7691 ((INSTANCE) == DMA1_Stream5) || \
|
|
|
7692 ((INSTANCE) == DMA1_Stream6) || \
|
|
|
7693 ((INSTANCE) == DMA1_Stream7) || \
|
|
|
7694 ((INSTANCE) == DMA2_Stream0) || \
|
|
|
7695 ((INSTANCE) == DMA2_Stream1) || \
|
|
|
7696 ((INSTANCE) == DMA2_Stream2) || \
|
|
|
7697 ((INSTANCE) == DMA2_Stream3) || \
|
|
|
7698 ((INSTANCE) == DMA2_Stream4) || \
|
|
|
7699 ((INSTANCE) == DMA2_Stream5) || \
|
|
|
7700 ((INSTANCE) == DMA2_Stream6) || \
|
|
|
7701 ((INSTANCE) == DMA2_Stream7))
|
|
|
7702
|
|
|
7703 /******************************* GPIO Instances *******************************/
|
|
|
7704 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
|
|
7705 ((INSTANCE) == GPIOB) || \
|
|
|
7706 ((INSTANCE) == GPIOC) || \
|
|
|
7707 ((INSTANCE) == GPIOD) || \
|
|
|
7708 ((INSTANCE) == GPIOE) || \
|
|
|
7709 ((INSTANCE) == GPIOF) || \
|
|
|
7710 ((INSTANCE) == GPIOG) || \
|
|
|
7711 ((INSTANCE) == GPIOH) || \
|
|
|
7712 ((INSTANCE) == GPIOI))
|
|
|
7713
|
|
|
7714 /******************************** I2C Instances *******************************/
|
|
|
7715 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
|
|
7716 ((INSTANCE) == I2C2) || \
|
|
|
7717 ((INSTANCE) == I2C3))
|
|
|
7718
|
|
|
7719 /******************************** I2S Instances *******************************/
|
|
|
7720 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
|
|
|
7721 ((INSTANCE) == SPI3))
|
|
|
7722
|
|
|
7723 /*************************** I2S Extended Instances ***************************/
|
|
|
7724 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
|
|
|
7725 ((INSTANCE) == SPI3) || \
|
|
|
7726 ((INSTANCE) == I2S2ext) || \
|
|
|
7727 ((INSTANCE) == I2S3ext))
|
|
|
7728
|
|
|
7729 /******************************* RNG Instances ********************************/
|
|
|
7730 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
|
|
|
7731
|
|
|
7732 /****************************** RTC Instances *********************************/
|
|
|
7733 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
|
|
|
7734
|
|
|
7735 /******************************** SPI Instances *******************************/
|
|
|
7736 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
7737 ((INSTANCE) == SPI2) || \
|
|
|
7738 ((INSTANCE) == SPI3))
|
|
|
7739
|
|
|
7740 /*************************** SPI Extended Instances ***************************/
|
|
|
7741 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
|
|
|
7742 ((INSTANCE) == SPI2) || \
|
|
|
7743 ((INSTANCE) == SPI3) || \
|
|
|
7744 ((INSTANCE) == I2S2ext) || \
|
|
|
7745 ((INSTANCE) == I2S3ext))
|
|
|
7746
|
|
|
7747 /****************** TIM Instances : All supported instances *******************/
|
|
|
7748 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7749 ((INSTANCE) == TIM2) || \
|
|
|
7750 ((INSTANCE) == TIM3) || \
|
|
|
7751 ((INSTANCE) == TIM4) || \
|
|
|
7752 ((INSTANCE) == TIM5) || \
|
|
|
7753 ((INSTANCE) == TIM6) || \
|
|
|
7754 ((INSTANCE) == TIM7) || \
|
|
|
7755 ((INSTANCE) == TIM8) || \
|
|
|
7756 ((INSTANCE) == TIM9) || \
|
|
|
7757 ((INSTANCE) == TIM10) || \
|
|
|
7758 ((INSTANCE) == TIM11) || \
|
|
|
7759 ((INSTANCE) == TIM12) || \
|
|
|
7760 ((INSTANCE) == TIM13) || \
|
|
|
7761 ((INSTANCE) == TIM14))
|
|
|
7762
|
|
|
7763 /************* TIM Instances : at least 1 capture/compare channel *************/
|
|
|
7764 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7765 ((INSTANCE) == TIM2) || \
|
|
|
7766 ((INSTANCE) == TIM3) || \
|
|
|
7767 ((INSTANCE) == TIM4) || \
|
|
|
7768 ((INSTANCE) == TIM5) || \
|
|
|
7769 ((INSTANCE) == TIM8) || \
|
|
|
7770 ((INSTANCE) == TIM9) || \
|
|
|
7771 ((INSTANCE) == TIM10) || \
|
|
|
7772 ((INSTANCE) == TIM11) || \
|
|
|
7773 ((INSTANCE) == TIM12) || \
|
|
|
7774 ((INSTANCE) == TIM13) || \
|
|
|
7775 ((INSTANCE) == TIM14))
|
|
|
7776
|
|
|
7777 /************ TIM Instances : at least 2 capture/compare channels *************/
|
|
|
7778 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7779 ((INSTANCE) == TIM2) || \
|
|
|
7780 ((INSTANCE) == TIM3) || \
|
|
|
7781 ((INSTANCE) == TIM4) || \
|
|
|
7782 ((INSTANCE) == TIM5) || \
|
|
|
7783 ((INSTANCE) == TIM8) || \
|
|
|
7784 ((INSTANCE) == TIM9) || \
|
|
|
7785 ((INSTANCE) == TIM12))
|
|
|
7786
|
|
|
7787 /************ TIM Instances : at least 3 capture/compare channels *************/
|
|
|
7788 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7789 ((INSTANCE) == TIM2) || \
|
|
|
7790 ((INSTANCE) == TIM3) || \
|
|
|
7791 ((INSTANCE) == TIM4) || \
|
|
|
7792 ((INSTANCE) == TIM5) || \
|
|
|
7793 ((INSTANCE) == TIM8))
|
|
|
7794
|
|
|
7795 /************ TIM Instances : at least 4 capture/compare channels *************/
|
|
|
7796 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7797 ((INSTANCE) == TIM2) || \
|
|
|
7798 ((INSTANCE) == TIM3) || \
|
|
|
7799 ((INSTANCE) == TIM4) || \
|
|
|
7800 ((INSTANCE) == TIM5) || \
|
|
|
7801 ((INSTANCE) == TIM8))
|
|
|
7802
|
|
|
7803 /******************** TIM Instances : Advanced-control timers *****************/
|
|
|
7804 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7805 ((INSTANCE) == TIM8))
|
|
|
7806
|
|
|
7807 /******************* TIM Instances : Timer input XOR function *****************/
|
|
|
7808 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7809 ((INSTANCE) == TIM2) || \
|
|
|
7810 ((INSTANCE) == TIM3) || \
|
|
|
7811 ((INSTANCE) == TIM4) || \
|
|
|
7812 ((INSTANCE) == TIM5) || \
|
|
|
7813 ((INSTANCE) == TIM8))
|
|
|
7814
|
|
|
7815 /****************** TIM Instances : DMA requests generation (UDE) *************/
|
|
|
7816 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7817 ((INSTANCE) == TIM2) || \
|
|
|
7818 ((INSTANCE) == TIM3) || \
|
|
|
7819 ((INSTANCE) == TIM4) || \
|
|
|
7820 ((INSTANCE) == TIM5) || \
|
|
|
7821 ((INSTANCE) == TIM6) || \
|
|
|
7822 ((INSTANCE) == TIM7) || \
|
|
|
7823 ((INSTANCE) == TIM8))
|
|
|
7824
|
|
|
7825 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
|
|
|
7826 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7827 ((INSTANCE) == TIM2) || \
|
|
|
7828 ((INSTANCE) == TIM3) || \
|
|
|
7829 ((INSTANCE) == TIM4) || \
|
|
|
7830 ((INSTANCE) == TIM5) || \
|
|
|
7831 ((INSTANCE) == TIM8))
|
|
|
7832
|
|
|
7833 /************ TIM Instances : DMA requests generation (COMDE) *****************/
|
|
|
7834 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7835 ((INSTANCE) == TIM2) || \
|
|
|
7836 ((INSTANCE) == TIM3) || \
|
|
|
7837 ((INSTANCE) == TIM4) || \
|
|
|
7838 ((INSTANCE) == TIM5) || \
|
|
|
7839 ((INSTANCE) == TIM8))
|
|
|
7840
|
|
|
7841 /******************** TIM Instances : DMA burst feature ***********************/
|
|
|
7842 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7843 ((INSTANCE) == TIM2) || \
|
|
|
7844 ((INSTANCE) == TIM3) || \
|
|
|
7845 ((INSTANCE) == TIM4) || \
|
|
|
7846 ((INSTANCE) == TIM5) || \
|
|
|
7847 ((INSTANCE) == TIM8))
|
|
|
7848
|
|
|
7849 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
|
|
7850 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7851 ((INSTANCE) == TIM2) || \
|
|
|
7852 ((INSTANCE) == TIM3) || \
|
|
|
7853 ((INSTANCE) == TIM4) || \
|
|
|
7854 ((INSTANCE) == TIM5) || \
|
|
|
7855 ((INSTANCE) == TIM6) || \
|
|
|
7856 ((INSTANCE) == TIM7) || \
|
|
|
7857 ((INSTANCE) == TIM8) || \
|
|
|
7858 ((INSTANCE) == TIM9) || \
|
|
|
7859 ((INSTANCE) == TIM12))
|
|
|
7860
|
|
|
7861 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
|
|
7862 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7863 ((INSTANCE) == TIM2) || \
|
|
|
7864 ((INSTANCE) == TIM3) || \
|
|
|
7865 ((INSTANCE) == TIM4) || \
|
|
|
7866 ((INSTANCE) == TIM5) || \
|
|
|
7867 ((INSTANCE) == TIM8) || \
|
|
|
7868 ((INSTANCE) == TIM9) || \
|
|
|
7869 ((INSTANCE) == TIM12))
|
|
|
7870
|
|
|
7871 /********************** TIM Instances : 32 bit Counter ************************/
|
|
|
7872 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
|
|
|
7873 ((INSTANCE) == TIM5))
|
|
|
7874
|
|
|
7875 /***************** TIM Instances : external trigger input availabe ************/
|
|
|
7876 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
|
|
|
7877 ((INSTANCE) == TIM2) || \
|
|
|
7878 ((INSTANCE) == TIM3) || \
|
|
|
7879 ((INSTANCE) == TIM4) || \
|
|
|
7880 ((INSTANCE) == TIM5) || \
|
|
|
7881 ((INSTANCE) == TIM8))
|
|
|
7882
|
|
|
7883 /****************** TIM Instances : remapping capability **********************/
|
|
|
7884 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
|
|
7885 ((INSTANCE) == TIM5) || \
|
|
|
7886 ((INSTANCE) == TIM11))
|
|
|
7887
|
|
|
7888 /******************* TIM Instances : output(s) available **********************/
|
|
|
7889 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
7890 ((((INSTANCE) == TIM1) && \
|
|
|
7891 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7892 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7893 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7894 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7895 || \
|
|
|
7896 (((INSTANCE) == TIM2) && \
|
|
|
7897 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7898 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7899 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7900 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7901 || \
|
|
|
7902 (((INSTANCE) == TIM3) && \
|
|
|
7903 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7904 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7905 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7906 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7907 || \
|
|
|
7908 (((INSTANCE) == TIM4) && \
|
|
|
7909 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7910 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7911 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7912 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7913 || \
|
|
|
7914 (((INSTANCE) == TIM5) && \
|
|
|
7915 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7916 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7917 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7918 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7919 || \
|
|
|
7920 (((INSTANCE) == TIM8) && \
|
|
|
7921 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7922 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7923 ((CHANNEL) == TIM_CHANNEL_3) || \
|
|
|
7924 ((CHANNEL) == TIM_CHANNEL_4))) \
|
|
|
7925 || \
|
|
|
7926 (((INSTANCE) == TIM9) && \
|
|
|
7927 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7928 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
7929 || \
|
|
|
7930 (((INSTANCE) == TIM10) && \
|
|
|
7931 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
7932 || \
|
|
|
7933 (((INSTANCE) == TIM11) && \
|
|
|
7934 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
7935 || \
|
|
|
7936 (((INSTANCE) == TIM12) && \
|
|
|
7937 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7938 ((CHANNEL) == TIM_CHANNEL_2))) \
|
|
|
7939 || \
|
|
|
7940 (((INSTANCE) == TIM13) && \
|
|
|
7941 (((CHANNEL) == TIM_CHANNEL_1))) \
|
|
|
7942 || \
|
|
|
7943 (((INSTANCE) == TIM14) && \
|
|
|
7944 (((CHANNEL) == TIM_CHANNEL_1))))
|
|
|
7945
|
|
|
7946 /************ TIM Instances : complementary output(s) available ***************/
|
|
|
7947 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
|
|
|
7948 ((((INSTANCE) == TIM1) && \
|
|
|
7949 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7950 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7951 ((CHANNEL) == TIM_CHANNEL_3))) \
|
|
|
7952 || \
|
|
|
7953 (((INSTANCE) == TIM8) && \
|
|
|
7954 (((CHANNEL) == TIM_CHANNEL_1) || \
|
|
|
7955 ((CHANNEL) == TIM_CHANNEL_2) || \
|
|
|
7956 ((CHANNEL) == TIM_CHANNEL_3))))
|
|
|
7957
|
|
|
7958 /******************** USART Instances : Synchronous mode **********************/
|
|
|
7959 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
7960 ((INSTANCE) == USART2) || \
|
|
|
7961 ((INSTANCE) == USART3) || \
|
|
|
7962 ((INSTANCE) == USART6))
|
|
|
7963
|
|
|
7964 /******************** UART Instances : Asynchronous mode **********************/
|
|
|
7965 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
7966 ((INSTANCE) == USART2) || \
|
|
|
7967 ((INSTANCE) == USART3) || \
|
|
|
7968 ((INSTANCE) == UART4) || \
|
|
|
7969 ((INSTANCE) == UART5) || \
|
|
|
7970 ((INSTANCE) == USART6))
|
|
|
7971
|
|
|
7972 /****************** UART Instances : Hardware Flow control ********************/
|
|
|
7973 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
7974 ((INSTANCE) == USART2) || \
|
|
|
7975 ((INSTANCE) == USART3) || \
|
|
|
7976 ((INSTANCE) == USART6))
|
|
|
7977
|
|
|
7978 /********************* UART Instances : Smard card mode ***********************/
|
|
|
7979 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
7980 ((INSTANCE) == USART2) || \
|
|
|
7981 ((INSTANCE) == USART3) || \
|
|
|
7982 ((INSTANCE) == USART6))
|
|
|
7983
|
|
|
7984 /*********************** UART Instances : IRDA mode ***************************/
|
|
|
7985 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
|
|
|
7986 ((INSTANCE) == USART2) || \
|
|
|
7987 ((INSTANCE) == USART3) || \
|
|
|
7988 ((INSTANCE) == UART4) || \
|
|
|
7989 ((INSTANCE) == UART5) || \
|
|
|
7990 ((INSTANCE) == USART6))
|
|
|
7991
|
|
|
7992 /****************************** IWDG Instances ********************************/
|
|
|
7993 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
|
|
|
7994
|
|
|
7995 /****************************** WWDG Instances ********************************/
|
|
|
7996 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
|
|
|
7997
|
|
|
7998 /****************************** SDIO Instances ********************************/
|
|
|
7999 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
|
|
|
8000
|
|
|
8001 /****************************** USB Exported Constants ************************/
|
|
|
8002 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
|
|
|
8003 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
|
|
|
8004 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
|
|
|
8005 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
|
|
|
8006
|
|
|
8007 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12
|
|
|
8008 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
|
|
|
8009 #define USB_OTG_HS_MAX_IN_ENDPOINTS 6 /* Including EP0 */
|
|
|
8010 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096 /* in Bytes */
|
|
|
8011
|
|
|
8012 /******************************************************************************/
|
|
|
8013 /* For a painless codes migration between the STM32F4xx device product */
|
|
|
8014 /* lines, the aliases defined below are put in place to overcome the */
|
|
|
8015 /* differences in the interrupt handlers and IRQn definitions. */
|
|
|
8016 /* No need to update developed interrupt code when moving across */
|
|
|
8017 /* product lines within the same STM32F4 Family */
|
|
|
8018 /******************************************************************************/
|
|
|
8019
|
|
|
8020 /* Aliases for __IRQn */
|
|
|
8021 #define FMC_IRQn FSMC_IRQn
|
|
|
8022
|
|
|
8023 /* Aliases for __IRQHandler */
|
|
|
8024 #define FMC_IRQHandler FSMC_IRQHandler
|
|
|
8025
|
|
|
8026 /**
|
|
|
8027 * @}
|
|
|
8028 */
|
|
|
8029
|
|
|
8030 /**
|
|
|
8031 * @}
|
|
|
8032 */
|
|
|
8033
|
|
|
8034 /**
|
|
|
8035 * @}
|
|
|
8036 */
|
|
|
8037
|
|
|
8038 #ifdef __cplusplus
|
|
|
8039 }
|
|
|
8040 #endif /* __cplusplus */
|
|
|
8041
|
|
|
8042 #endif /* __STM32F407xx_H */
|
|
|
8043
|
|
|
8044
|
|
|
8045
|
|
|
8046 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
