Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h @ 240:625d20070261 div-fixes-5
Improvement SPI stability/recoverability
The core part of this commit comes from careful code reading. The core is the
swap of Scheduler_Request_sync_with_SPI(SPI_SYNC_METHOD_SOFT) and
SPI_Start_single_TxRx_with_Master(). This code is sitting in an if-clause
that is triggered on SPI comms failure. Instead of blindly trying to
communicate again (which will very likely fail again), first try to reset
the comms link, and then try to communicate again. That simply makes
more sense in this case.
This is heavily tested, on 2 simple dives, and 5 very long deco schedules
from the simulator (10+ hour deco's), and a lot of small simulated dives
(upto 2h runtime). Of all these tests, only one long session failed after
9 out of 11h runtime. Analyzing that one failure, suggests that the
RTE is looping in some error handler, which (obviously) results in
a SPI comms failure as a result. I consider this not part of this change.
Additionally, some more cleanup is done in this code.
Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
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date | Mon, 08 Apr 2019 11:49:13 +0200 |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_ll_cortex.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of CORTEX LL module. |
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6 @verbatim |
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7 ============================================================================== |
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8 ##### How to use this driver ##### |
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9 ============================================================================== |
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10 [..] |
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11 The LL CORTEX driver contains a set of generic APIs that can be |
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12 used by user: |
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13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick |
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14 functions |
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15 (+) Low power mode configuration (SCB register of Cortex-MCU) |
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16 (+) MPU API to configure and enable regions |
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17 (MPU services provided only on some devices) |
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18 (+) API to access to MCU info (CPUID register) |
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19 (+) API to enable fault handler (SHCSR accesses) |
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20 |
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21 @endverbatim |
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22 ****************************************************************************** |
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23 * @attention |
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24 * |
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25 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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26 * |
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27 * Redistribution and use in source and binary forms, with or without modification, |
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28 * are permitted provided that the following conditions are met: |
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29 * 1. Redistributions of source code must retain the above copyright notice, |
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30 * this list of conditions and the following disclaimer. |
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31 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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32 * this list of conditions and the following disclaimer in the documentation |
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33 * and/or other materials provided with the distribution. |
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34 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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35 * may be used to endorse or promote products derived from this software |
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36 * without specific prior written permission. |
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37 * |
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38 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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39 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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41 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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44 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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45 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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46 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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48 * |
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49 ****************************************************************************** |
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50 */ |
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51 |
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52 /* Define to prevent recursive inclusion -------------------------------------*/ |
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53 #ifndef __STM32F4xx_LL_CORTEX_H |
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54 #define __STM32F4xx_LL_CORTEX_H |
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55 |
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56 #ifdef __cplusplus |
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57 extern "C" { |
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58 #endif |
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59 |
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60 /* Includes ------------------------------------------------------------------*/ |
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61 #include "stm32f4xx.h" |
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62 |
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63 /** @addtogroup STM32F4xx_LL_Driver |
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64 * @{ |
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65 */ |
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66 |
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67 /** @defgroup CORTEX_LL CORTEX |
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68 * @{ |
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69 */ |
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70 |
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71 /* Private types -------------------------------------------------------------*/ |
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72 /* Private variables ---------------------------------------------------------*/ |
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73 |
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74 /* Private constants ---------------------------------------------------------*/ |
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75 |
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76 /* Private macros ------------------------------------------------------------*/ |
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77 |
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78 /* Exported types ------------------------------------------------------------*/ |
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79 /* Exported constants --------------------------------------------------------*/ |
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80 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants |
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81 * @{ |
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82 */ |
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83 |
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84 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source |
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85 * @{ |
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86 */ |
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87 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ |
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88 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ |
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89 /** |
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90 * @} |
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91 */ |
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92 |
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93 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type |
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94 * @{ |
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95 */ |
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96 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ |
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97 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ |
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98 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ |
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99 /** |
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100 * @} |
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101 */ |
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102 |
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103 #if __MPU_PRESENT |
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104 |
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105 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control |
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106 * @{ |
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107 */ |
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108 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ |
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109 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ |
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110 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ |
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111 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ |
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112 /** |
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113 * @} |
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114 */ |
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115 |
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116 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number |
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117 * @{ |
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118 */ |
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119 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ |
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120 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ |
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121 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ |
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122 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ |
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123 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ |
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124 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ |
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125 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ |
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126 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ |
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127 /** |
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128 * @} |
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129 */ |
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130 |
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131 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size |
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132 * @{ |
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133 */ |
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134 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ |
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135 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ |
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136 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ |
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137 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ |
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138 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ |
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139 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ |
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140 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ |
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141 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ |
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142 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ |
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143 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ |
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144 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ |
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145 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ |
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146 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ |
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147 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ |
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148 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ |
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149 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ |
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150 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ |
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151 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ |
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152 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ |
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153 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ |
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154 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ |
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155 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ |
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156 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ |
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157 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ |
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158 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ |
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159 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ |
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160 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ |
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161 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ |
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162 /** |
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163 * @} |
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164 */ |
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165 |
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166 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges |
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167 * @{ |
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168 */ |
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169 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ |
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170 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ |
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171 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ |
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172 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ |
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173 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ |
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174 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ |
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175 /** |
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176 * @} |
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177 */ |
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178 |
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179 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level |
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180 * @{ |
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181 */ |
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182 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ |
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183 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ |
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184 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ |
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185 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ |
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186 /** |
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187 * @} |
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188 */ |
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189 |
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190 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access |
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191 * @{ |
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192 */ |
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193 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ |
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194 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ |
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195 /** |
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196 * @} |
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197 */ |
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198 |
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199 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access |
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200 * @{ |
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201 */ |
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202 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ |
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203 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ |
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204 /** |
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205 * @} |
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206 */ |
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207 |
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208 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access |
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209 * @{ |
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210 */ |
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211 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ |
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212 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ |
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213 /** |
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214 * @} |
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215 */ |
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216 |
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217 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access |
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218 * @{ |
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219 */ |
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220 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ |
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221 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ |
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222 /** |
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223 * @} |
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224 */ |
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225 #endif /* __MPU_PRESENT */ |
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226 /** |
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227 * @} |
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228 */ |
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229 |
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230 /* Exported macro ------------------------------------------------------------*/ |
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231 |
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232 /* Exported functions --------------------------------------------------------*/ |
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233 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions |
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234 * @{ |
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235 */ |
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236 |
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237 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK |
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238 * @{ |
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239 */ |
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240 |
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241 /** |
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242 * @brief This function checks if the Systick counter flag is active or not. |
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243 * @note It can be used in timeout function on application side. |
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244 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag |
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245 * @retval State of bit (1 or 0). |
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246 */ |
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247 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) |
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248 { |
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249 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); |
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250 } |
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251 |
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252 /** |
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253 * @brief Configures the SysTick clock source |
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254 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource |
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255 * @param Source This parameter can be one of the following values: |
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256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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257 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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258 * @retval None |
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259 */ |
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260 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) |
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261 { |
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262 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) |
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263 { |
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264 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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265 } |
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266 else |
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267 { |
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268 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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269 } |
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270 } |
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271 |
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272 /** |
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273 * @brief Get the SysTick clock source |
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274 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource |
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275 * @retval Returned value can be one of the following values: |
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276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 |
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277 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK |
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278 */ |
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279 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) |
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280 { |
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281 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); |
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282 } |
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283 |
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284 /** |
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285 * @brief Enable SysTick exception request |
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286 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT |
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287 * @retval None |
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288 */ |
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289 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) |
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290 { |
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291 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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292 } |
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293 |
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294 /** |
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295 * @brief Disable SysTick exception request |
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296 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT |
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297 * @retval None |
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298 */ |
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299 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) |
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300 { |
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301 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); |
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302 } |
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303 |
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304 /** |
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305 * @brief Checks if the SYSTICK interrupt is enabled or disabled. |
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306 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT |
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307 * @retval State of bit (1 or 0). |
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308 */ |
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309 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) |
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310 { |
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311 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); |
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312 } |
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313 |
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314 /** |
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315 * @} |
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316 */ |
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317 |
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318 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE |
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319 * @{ |
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320 */ |
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321 |
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322 /** |
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323 * @brief Processor uses sleep as its low power mode |
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324 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep |
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325 * @retval None |
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326 */ |
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327 __STATIC_INLINE void LL_LPM_EnableSleep(void) |
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328 { |
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329 /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
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330 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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331 } |
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332 |
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333 /** |
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334 * @brief Processor uses deep sleep as its low power mode |
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335 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep |
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336 * @retval None |
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337 */ |
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338 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) |
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339 { |
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340 /* Set SLEEPDEEP bit of Cortex System Control Register */ |
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341 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); |
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342 } |
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343 |
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344 /** |
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345 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. |
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346 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an |
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347 * empty main application. |
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348 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit |
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349 * @retval None |
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350 */ |
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351 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) |
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352 { |
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353 /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
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354 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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355 } |
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356 |
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357 /** |
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358 * @brief Do not sleep when returning to Thread mode. |
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359 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit |
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360 * @retval None |
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361 */ |
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362 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) |
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363 { |
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364 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
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365 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
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366 } |
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367 |
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368 /** |
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369 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the |
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370 * processor. |
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371 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend |
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372 * @retval None |
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373 */ |
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374 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) |
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375 { |
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376 /* Set SEVEONPEND bit of Cortex System Control Register */ |
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377 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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378 } |
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379 |
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380 /** |
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381 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are |
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382 * excluded |
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383 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend |
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384 * @retval None |
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385 */ |
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386 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) |
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387 { |
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388 /* Clear SEVEONPEND bit of Cortex System Control Register */ |
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389 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
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390 } |
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391 |
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392 /** |
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393 * @} |
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394 */ |
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395 |
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396 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER |
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397 * @{ |
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398 */ |
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399 |
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400 /** |
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401 * @brief Enable a fault in System handler control register (SHCSR) |
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402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault |
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403 * @param Fault This parameter can be a combination of the following values: |
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404 * @arg @ref LL_HANDLER_FAULT_USG |
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405 * @arg @ref LL_HANDLER_FAULT_BUS |
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406 * @arg @ref LL_HANDLER_FAULT_MEM |
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407 * @retval None |
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408 */ |
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409 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) |
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410 { |
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411 /* Enable the system handler fault */ |
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412 SET_BIT(SCB->SHCSR, Fault); |
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413 } |
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414 |
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415 /** |
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416 * @brief Disable a fault in System handler control register (SHCSR) |
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417 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault |
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418 * @param Fault This parameter can be a combination of the following values: |
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419 * @arg @ref LL_HANDLER_FAULT_USG |
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420 * @arg @ref LL_HANDLER_FAULT_BUS |
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421 * @arg @ref LL_HANDLER_FAULT_MEM |
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422 * @retval None |
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423 */ |
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424 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) |
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425 { |
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426 /* Disable the system handler fault */ |
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427 CLEAR_BIT(SCB->SHCSR, Fault); |
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428 } |
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429 |
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430 /** |
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431 * @} |
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432 */ |
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433 |
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434 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO |
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435 * @{ |
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436 */ |
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437 |
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438 /** |
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439 * @brief Get Implementer code |
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440 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer |
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441 * @retval Value should be equal to 0x41 for ARM |
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442 */ |
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443 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) |
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444 { |
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445 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); |
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446 } |
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447 |
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448 /** |
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449 * @brief Get Variant number (The r value in the rnpn product revision identifier) |
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450 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant |
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451 * @retval Value between 0 and 255 (0x0: revision 0) |
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452 */ |
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453 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) |
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454 { |
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455 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); |
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456 } |
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457 |
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458 /** |
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459 * @brief Get Constant number |
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460 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant |
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461 * @retval Value should be equal to 0xF for Cortex-M4 devices |
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462 */ |
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463 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) |
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464 { |
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465 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); |
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466 } |
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467 |
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468 /** |
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469 * @brief Get Part number |
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470 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo |
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471 * @retval Value should be equal to 0xC24 for Cortex-M4 |
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472 */ |
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473 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) |
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474 { |
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475 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); |
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476 } |
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477 |
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478 /** |
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479 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) |
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480 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision |
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481 * @retval Value between 0 and 255 (0x1: patch 1) |
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482 */ |
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483 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) |
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484 { |
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485 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); |
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486 } |
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487 |
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488 /** |
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489 * @} |
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490 */ |
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491 |
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492 #if __MPU_PRESENT |
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493 /** @defgroup CORTEX_LL_EF_MPU MPU |
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494 * @{ |
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495 */ |
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496 |
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497 /** |
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498 * @brief Enable MPU with input options |
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499 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable |
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500 * @param Options This parameter can be one of the following values: |
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501 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE |
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502 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI |
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503 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT |
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504 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF |
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505 * @retval None |
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506 */ |
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507 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) |
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508 { |
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509 /* Enable the MPU*/ |
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510 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); |
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511 /* Ensure MPU settings take effects */ |
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512 __DSB(); |
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513 /* Sequence instruction fetches using update settings */ |
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514 __ISB(); |
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515 } |
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516 |
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517 /** |
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518 * @brief Disable MPU |
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519 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable |
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520 * @retval None |
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521 */ |
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522 __STATIC_INLINE void LL_MPU_Disable(void) |
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523 { |
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524 /* Make sure outstanding transfers are done */ |
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525 __DMB(); |
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526 /* Disable MPU*/ |
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527 WRITE_REG(MPU->CTRL, 0U); |
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528 } |
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529 |
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530 /** |
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531 * @brief Check if MPU is enabled or not |
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532 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled |
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533 * @retval State of bit (1 or 0). |
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534 */ |
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535 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) |
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536 { |
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537 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); |
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538 } |
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539 |
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540 /** |
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541 * @brief Enable a MPU region |
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542 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion |
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543 * @param Region This parameter can be one of the following values: |
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544 * @arg @ref LL_MPU_REGION_NUMBER0 |
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545 * @arg @ref LL_MPU_REGION_NUMBER1 |
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546 * @arg @ref LL_MPU_REGION_NUMBER2 |
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547 * @arg @ref LL_MPU_REGION_NUMBER3 |
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548 * @arg @ref LL_MPU_REGION_NUMBER4 |
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549 * @arg @ref LL_MPU_REGION_NUMBER5 |
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550 * @arg @ref LL_MPU_REGION_NUMBER6 |
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551 * @arg @ref LL_MPU_REGION_NUMBER7 |
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552 * @retval None |
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553 */ |
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554 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) |
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555 { |
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556 /* Set Region number */ |
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557 WRITE_REG(MPU->RNR, Region); |
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558 /* Enable the MPU region */ |
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559 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
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560 } |
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561 |
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562 /** |
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563 * @brief Configure and enable a region |
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564 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n |
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565 * MPU_RBAR REGION LL_MPU_ConfigRegion\n |
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566 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n |
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567 * MPU_RASR XN LL_MPU_ConfigRegion\n |
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568 * MPU_RASR AP LL_MPU_ConfigRegion\n |
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569 * MPU_RASR S LL_MPU_ConfigRegion\n |
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570 * MPU_RASR C LL_MPU_ConfigRegion\n |
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571 * MPU_RASR B LL_MPU_ConfigRegion\n |
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572 * MPU_RASR SIZE LL_MPU_ConfigRegion |
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573 * @param Region This parameter can be one of the following values: |
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574 * @arg @ref LL_MPU_REGION_NUMBER0 |
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575 * @arg @ref LL_MPU_REGION_NUMBER1 |
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576 * @arg @ref LL_MPU_REGION_NUMBER2 |
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577 * @arg @ref LL_MPU_REGION_NUMBER3 |
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578 * @arg @ref LL_MPU_REGION_NUMBER4 |
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579 * @arg @ref LL_MPU_REGION_NUMBER5 |
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580 * @arg @ref LL_MPU_REGION_NUMBER6 |
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581 * @arg @ref LL_MPU_REGION_NUMBER7 |
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582 * @param Address Value of region base address |
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583 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF |
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584 * @param Attributes This parameter can be a combination of the following values: |
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585 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B |
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586 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB |
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587 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB |
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588 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB |
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589 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB |
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590 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB |
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591 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS |
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592 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO |
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593 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 |
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594 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE |
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595 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE |
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596 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE |
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597 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE |
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598 * @retval None |
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599 */ |
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600 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) |
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601 { |
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602 /* Set Region number */ |
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603 WRITE_REG(MPU->RNR, Region); |
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604 /* Set base address */ |
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605 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); |
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606 /* Configure MPU */ |
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607 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); |
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608 } |
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609 |
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610 /** |
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611 * @brief Disable a region |
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612 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n |
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613 * MPU_RASR ENABLE LL_MPU_DisableRegion |
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614 * @param Region This parameter can be one of the following values: |
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615 * @arg @ref LL_MPU_REGION_NUMBER0 |
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616 * @arg @ref LL_MPU_REGION_NUMBER1 |
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617 * @arg @ref LL_MPU_REGION_NUMBER2 |
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618 * @arg @ref LL_MPU_REGION_NUMBER3 |
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619 * @arg @ref LL_MPU_REGION_NUMBER4 |
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620 * @arg @ref LL_MPU_REGION_NUMBER5 |
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621 * @arg @ref LL_MPU_REGION_NUMBER6 |
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622 * @arg @ref LL_MPU_REGION_NUMBER7 |
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623 * @retval None |
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624 */ |
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625 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) |
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626 { |
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627 /* Set Region number */ |
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628 WRITE_REG(MPU->RNR, Region); |
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629 /* Disable the MPU region */ |
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630 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); |
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631 } |
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632 |
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633 /** |
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634 * @} |
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635 */ |
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636 |
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637 #endif /* __MPU_PRESENT */ |
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638 /** |
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639 * @} |
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640 */ |
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641 |
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642 /** |
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643 * @} |
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644 */ |
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645 |
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646 /** |
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647 * @} |
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648 */ |
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649 |
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650 #ifdef __cplusplus |
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651 } |
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652 #endif |
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653 |
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654 #endif /* __STM32F4xx_LL_CORTEX_H */ |
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655 |
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656 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |