annotate Common/Drivers/CMSIS/Include/core_cm7.h @ 882:608d3e918146 Evo_2_23

Added slow exit timer function: At the end of the dive the final ascent to surface should be done slowly. The new function provides a comparison of the current divers depth compared to a linear ascent simulated by the OSTC. The visualization is shown instead of the ascent speed with a little different appearance. The linear ascent is starting from the last stop depth and the time for the ascent may be configurated in the deco settings. The simulated and real peth is compared and the depth color changes based on the difference of the values. In case the diver is much below the timer depth then the timer will stop and wait for the diver to follow.
author Ideenmodellierer
date Sat, 31 Aug 2024 17:35:52 +0200
parents c78bcbd5deda
children
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1 /**************************************************************************//**
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2 * @file core_cm7.h
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3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
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4 * @version V4.30
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5 * @date 20. October 2015
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6 ******************************************************************************/
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7 /* Copyright (c) 2009 - 2015 ARM LIMITED
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8
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9 All rights reserved.
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10 Redistribution and use in source and binary forms, with or without
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11 modification, are permitted provided that the following conditions are met:
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12 - Redistributions of source code must retain the above copyright
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13 notice, this list of conditions and the following disclaimer.
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14 - Redistributions in binary form must reproduce the above copyright
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15 notice, this list of conditions and the following disclaimer in the
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16 documentation and/or other materials provided with the distribution.
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17 - Neither the name of ARM nor the names of its contributors may be used
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18 to endorse or promote products derived from this software without
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19 specific prior written permission.
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20 *
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21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 POSSIBILITY OF SUCH DAMAGE.
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32 ---------------------------------------------------------------------------*/
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33
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34
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35 #if defined ( __ICCARM__ )
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36 #pragma system_include /* treat file as system include file for MISRA check */
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37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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38 #pragma clang system_header /* treat file as system include file */
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39 #endif
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40
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41 #ifndef __CORE_CM7_H_GENERIC
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42 #define __CORE_CM7_H_GENERIC
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43
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44 #include <stdint.h>
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45
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46 #ifdef __cplusplus
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47 extern "C" {
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48 #endif
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49
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50 /**
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51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
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52 CMSIS violates the following MISRA-C:2004 rules:
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53
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54 \li Required Rule 8.5, object/function definition in header file.<br>
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55 Function definitions in header files are used to allow 'inlining'.
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56
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57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
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58 Unions are used for effective representation of core registers.
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59
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60 \li Advisory Rule 19.7, Function-like macro defined.<br>
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61 Function-like macros are used to allow more efficient code.
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62 */
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63
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64
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65 /*******************************************************************************
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66 * CMSIS definitions
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67 ******************************************************************************/
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68 /**
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69 \ingroup Cortex_M7
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70 @{
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71 */
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72
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73 /* CMSIS CM7 definitions */
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74 #define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
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75 #define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
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76 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
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77 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
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78
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79 #define __CORTEX_M (0x07U) /*!< Cortex-M Core */
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80
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81
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82 #if defined ( __CC_ARM )
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83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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85 #define __STATIC_INLINE static __inline
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86
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87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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88 #define __ASM __asm /*!< asm keyword for ARM Compiler */
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89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
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90 #define __STATIC_INLINE static __inline
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91
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92 #elif defined ( __GNUC__ )
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93 #define __ASM __asm /*!< asm keyword for GNU Compiler */
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94 #define __INLINE inline /*!< inline keyword for GNU Compiler */
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95 #define __STATIC_INLINE static inline
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96
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97 #elif defined ( __ICCARM__ )
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98 #define __ASM __asm /*!< asm keyword for IAR Compiler */
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99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
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100 #define __STATIC_INLINE static inline
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101
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102 #elif defined ( __TMS470__ )
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103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
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104 #define __STATIC_INLINE static inline
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105
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106 #elif defined ( __TASKING__ )
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107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
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108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
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109 #define __STATIC_INLINE static inline
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110
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111 #elif defined ( __CSMC__ )
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112 #define __packed
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113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
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114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
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115 #define __STATIC_INLINE static inline
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116
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117 #else
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118 #error Unknown compiler
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119 #endif
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120
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121 /** __FPU_USED indicates whether an FPU is used or not.
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122 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
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123 */
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124 #if defined ( __CC_ARM )
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125 #if defined __TARGET_FPU_VFP
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126 #if (__FPU_PRESENT == 1U)
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127 #define __FPU_USED 1U
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128 #else
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129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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130 #define __FPU_USED 0U
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131 #endif
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132 #else
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133 #define __FPU_USED 0U
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134 #endif
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135
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136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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137 #if defined __ARM_PCS_VFP
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138 #if (__FPU_PRESENT == 1)
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139 #define __FPU_USED 1U
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140 #else
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141 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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142 #define __FPU_USED 0U
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143 #endif
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144 #else
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145 #define __FPU_USED 0U
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146 #endif
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147
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148 #elif defined ( __GNUC__ )
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149 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
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150 #if (__FPU_PRESENT == 1U)
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151 #define __FPU_USED 1U
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152 #else
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153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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154 #define __FPU_USED 0U
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155 #endif
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156 #else
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157 #define __FPU_USED 0U
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158 #endif
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159
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160 #elif defined ( __ICCARM__ )
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161 #if defined __ARMVFP__
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162 #if (__FPU_PRESENT == 1U)
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163 #define __FPU_USED 1U
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164 #else
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165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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166 #define __FPU_USED 0U
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167 #endif
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168 #else
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169 #define __FPU_USED 0U
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170 #endif
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171
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172 #elif defined ( __TMS470__ )
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173 #if defined __TI_VFP_SUPPORT__
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174 #if (__FPU_PRESENT == 1U)
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175 #define __FPU_USED 1U
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176 #else
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177 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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178 #define __FPU_USED 0U
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179 #endif
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180 #else
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181 #define __FPU_USED 0U
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182 #endif
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183
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184 #elif defined ( __TASKING__ )
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185 #if defined __FPU_VFP__
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186 #if (__FPU_PRESENT == 1U)
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187 #define __FPU_USED 1U
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188 #else
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189 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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190 #define __FPU_USED 0U
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191 #endif
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192 #else
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193 #define __FPU_USED 0U
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194 #endif
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195
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196 #elif defined ( __CSMC__ )
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197 #if ( __CSMC__ & 0x400U)
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198 #if (__FPU_PRESENT == 1U)
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199 #define __FPU_USED 1U
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200 #else
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201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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202 #define __FPU_USED 0U
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203 #endif
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204 #else
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205 #define __FPU_USED 0U
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206 #endif
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207
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208 #endif
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209
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210 #include "core_cmInstr.h" /* Core Instruction Access */
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211 #include "core_cmFunc.h" /* Core Function Access */
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212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
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213
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214 #ifdef __cplusplus
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215 }
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216 #endif
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217
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218 #endif /* __CORE_CM7_H_GENERIC */
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219
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220 #ifndef __CMSIS_GENERIC
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221
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222 #ifndef __CORE_CM7_H_DEPENDANT
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223 #define __CORE_CM7_H_DEPENDANT
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224
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225 #ifdef __cplusplus
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226 extern "C" {
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227 #endif
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228
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229 /* check device defines and use defaults */
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230 #if defined __CHECK_DEVICE_DEFINES
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231 #ifndef __CM7_REV
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232 #define __CM7_REV 0x0000U
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233 #warning "__CM7_REV not defined in device header file; using default!"
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234 #endif
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235
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236 #ifndef __FPU_PRESENT
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237 #define __FPU_PRESENT 0U
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238 #warning "__FPU_PRESENT not defined in device header file; using default!"
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239 #endif
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240
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241 #ifndef __MPU_PRESENT
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242 #define __MPU_PRESENT 0U
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243 #warning "__MPU_PRESENT not defined in device header file; using default!"
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244 #endif
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245
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246 #ifndef __ICACHE_PRESENT
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247 #define __ICACHE_PRESENT 0U
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248 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
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249 #endif
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250
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251 #ifndef __DCACHE_PRESENT
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252 #define __DCACHE_PRESENT 0U
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253 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
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254 #endif
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255
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256 #ifndef __DTCM_PRESENT
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257 #define __DTCM_PRESENT 0U
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258 #warning "__DTCM_PRESENT not defined in device header file; using default!"
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259 #endif
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260
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261 #ifndef __NVIC_PRIO_BITS
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262 #define __NVIC_PRIO_BITS 3U
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263 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
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264 #endif
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265
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266 #ifndef __Vendor_SysTickConfig
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267 #define __Vendor_SysTickConfig 0U
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268 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
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269 #endif
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270 #endif
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271
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272 /* IO definitions (access restrictions to peripheral registers) */
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273 /**
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274 \defgroup CMSIS_glob_defs CMSIS Global Defines
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275
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276 <strong>IO Type Qualifiers</strong> are used
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277 \li to specify the access to peripheral variables.
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278 \li for automatic generation of peripheral register debug information.
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279 */
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280 #ifdef __cplusplus
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281 #define __I volatile /*!< Defines 'read only' permissions */
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282 #else
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283 #define __I volatile const /*!< Defines 'read only' permissions */
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284 #endif
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285 #define __O volatile /*!< Defines 'write only' permissions */
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286 #define __IO volatile /*!< Defines 'read / write' permissions */
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287
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288 /* following defines should be used for structure members */
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289 #define __IM volatile const /*! Defines 'read only' structure member permissions */
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290 #define __OM volatile /*! Defines 'write only' structure member permissions */
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291 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
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292
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293 /*@} end of group Cortex_M7 */
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294
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295
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296
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297 /*******************************************************************************
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298 * Register Abstraction
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299 Core Register contain:
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300 - Core Register
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301 - Core NVIC Register
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302 - Core SCB Register
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303 - Core SysTick Register
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304 - Core Debug Register
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305 - Core MPU Register
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306 - Core FPU Register
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307 ******************************************************************************/
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308 /**
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309 \defgroup CMSIS_core_register Defines and Type Definitions
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310 \brief Type definitions and defines for Cortex-M processor based devices.
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311 */
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312
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313 /**
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314 \ingroup CMSIS_core_register
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315 \defgroup CMSIS_CORE Status and Control Registers
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316 \brief Core Register type definitions.
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317 @{
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318 */
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319
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320 /**
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321 \brief Union type to access the Application Program Status Register (APSR).
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322 */
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323 typedef union
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324 {
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325 struct
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326 {
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327 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
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328 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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329 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
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330 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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331 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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332 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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333 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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334 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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335 } b; /*!< Structure used for bit access */
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336 uint32_t w; /*!< Type used for word access */
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337 } APSR_Type;
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338
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339 /* APSR Register Definitions */
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340 #define APSR_N_Pos 31U /*!< APSR: N Position */
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341 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
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342
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343 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
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344 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
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345
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346 #define APSR_C_Pos 29U /*!< APSR: C Position */
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347 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
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348
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349 #define APSR_V_Pos 28U /*!< APSR: V Position */
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350 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
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351
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352 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
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353 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
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354
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355 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
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356 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
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357
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358
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359 /**
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360 \brief Union type to access the Interrupt Program Status Register (IPSR).
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361 */
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362 typedef union
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363 {
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364 struct
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365 {
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366 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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367 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
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368 } b; /*!< Structure used for bit access */
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369 uint32_t w; /*!< Type used for word access */
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370 } IPSR_Type;
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371
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372 /* IPSR Register Definitions */
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373 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
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374 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
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375
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376
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377 /**
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378 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
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379 */
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380 typedef union
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381 {
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382 struct
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383 {
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384 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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385 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
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386 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
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387 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
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388 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
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389 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
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390 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
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391 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
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392 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
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393 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
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394 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
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395 } b; /*!< Structure used for bit access */
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396 uint32_t w; /*!< Type used for word access */
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397 } xPSR_Type;
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398
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399 /* xPSR Register Definitions */
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400 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
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401 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
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402
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403 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
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404 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
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405
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406 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
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407 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
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408
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409 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
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410 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
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411
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412 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
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413 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
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414
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415 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
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416 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
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417
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418 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
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419 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
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420
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421 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
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422 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
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423
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424 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
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425 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
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426
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427
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428 /**
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429 \brief Union type to access the Control Registers (CONTROL).
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430 */
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431 typedef union
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432 {
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433 struct
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434 {
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435 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
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436 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
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437 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
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438 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
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439 } b; /*!< Structure used for bit access */
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440 uint32_t w; /*!< Type used for word access */
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441 } CONTROL_Type;
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442
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443 /* CONTROL Register Definitions */
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444 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
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445 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
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446
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447 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
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448 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
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449
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450 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
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451 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
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452
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453 /*@} end of group CMSIS_CORE */
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454
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455
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456 /**
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457 \ingroup CMSIS_core_register
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458 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
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459 \brief Type definitions for the NVIC Registers
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460 @{
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461 */
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462
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463 /**
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464 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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465 */
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466 typedef struct
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467 {
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468 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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469 uint32_t RESERVED0[24U];
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470 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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471 uint32_t RSERVED1[24U];
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472 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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473 uint32_t RESERVED2[24U];
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474 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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475 uint32_t RESERVED3[24U];
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476 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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477 uint32_t RESERVED4[56U];
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478 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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479 uint32_t RESERVED5[644U];
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480 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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481 } NVIC_Type;
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482
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483 /* Software Triggered Interrupt Register Definitions */
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484 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
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485 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
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486
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487 /*@} end of group CMSIS_NVIC */
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488
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489
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490 /**
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491 \ingroup CMSIS_core_register
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492 \defgroup CMSIS_SCB System Control Block (SCB)
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493 \brief Type definitions for the System Control Block Registers
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494 @{
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495 */
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496
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497 /**
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498 \brief Structure type to access the System Control Block (SCB).
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499 */
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500 typedef struct
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501 {
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502 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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503 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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504 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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505 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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506 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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507 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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508 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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509 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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510 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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511 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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512 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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513 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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514 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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515 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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516 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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517 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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518 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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519 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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520 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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521 uint32_t RESERVED0[1U];
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522 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
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523 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
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524 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
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525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
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526 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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527 uint32_t RESERVED3[93U];
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528 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
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529 uint32_t RESERVED4[15U];
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530 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
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531 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
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532 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
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533 uint32_t RESERVED5[1U];
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534 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
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535 uint32_t RESERVED6[1U];
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536 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
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537 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
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538 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
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539 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
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540 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
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541 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
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542 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
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543 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
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544 uint32_t RESERVED7[6U];
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545 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
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546 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
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547 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
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548 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
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549 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
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550 uint32_t RESERVED8[1U];
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551 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
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552 } SCB_Type;
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553
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554 /* SCB CPUID Register Definitions */
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555 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
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556 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
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557
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558 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
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559 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
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560
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561 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
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562 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
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563
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564 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
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565 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
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566
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567 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
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568 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
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569
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570 /* SCB Interrupt Control State Register Definitions */
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571 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
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572 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
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573
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574 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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575 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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576
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577 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
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578 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
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579
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580 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
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581 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
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582
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583 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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584 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
585
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
586 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
587 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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588
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
589 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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590 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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591
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
592 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
593 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
594
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
595 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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596 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
597
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
598 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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599 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
600
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
601 /* SCB Vector Table Offset Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
602 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
603 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
604
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
605 /* SCB Application Interrupt and Reset Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
606 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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607 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
608
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
609 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
610 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
611
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
612 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
613 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
614
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
615 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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616 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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617
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
618 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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619 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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620
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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621 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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622 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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623
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
624 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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625 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
626
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
627 /* SCB System Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
628 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
629 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
630
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
631 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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632 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
633
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
634 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
635 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
636
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
637 /* SCB Configuration Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
638 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
639 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
640
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
641 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
642 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
643
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
644 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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645 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
646
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
647 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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648 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
649
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
650 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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651 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
652
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
653 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
654 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
655
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
656 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
657 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
658
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
659 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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660 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
661
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
662 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
663 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
664
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
665 /* SCB System Handler Control and State Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
666 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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667 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
668
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
669 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
670 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
671
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
672 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
673 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
674
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
675 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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676 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
677
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
678 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
679 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
680
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
681 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
682 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
683
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
684 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
685 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
686
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
687 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
688 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
689
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
690 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
691 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
692
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
693 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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694 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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695
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
696 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
697 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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698
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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699 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
700 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
701
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
702 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
703 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
704
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
705 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
706 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
707
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
708 /* SCB Configurable Fault Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
709 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
710 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
711
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
712 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
713 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
714
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
715 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
716 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
717
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
718 /* SCB Hard Fault Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
719 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
720 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
721
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
722 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
723 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
724
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
725 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
726 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
727
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
728 /* SCB Debug Fault Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
729 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
730 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
731
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
732 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
733 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
734
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
735 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
736 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
737
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
738 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
739 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
740
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
741 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
742 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
743
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
744 /* SCB Cache Level ID Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
745 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
746 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
747
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
748 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
749 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
750
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
751 /* SCB Cache Type Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
752 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
753 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
754
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
755 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
756 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
757
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
758 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
759 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
760
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
761 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
762 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
763
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
764 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
765 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
766
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
767 /* SCB Cache Size ID Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
768 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
769 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
770
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
771 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
772 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
773
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
774 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
775 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
776
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
777 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
778 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
779
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
780 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
781 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
782
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
783 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
784 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
785
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
786 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
787 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
788
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
789 /* SCB Cache Size Selection Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
790 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
791 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
792
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
793 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
794 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
795
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
796 /* SCB Software Triggered Interrupt Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
797 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
798 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
799
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
800 /* SCB D-Cache Invalidate by Set-way Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
801 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
802 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
803
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
804 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
805 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
806
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
807 /* SCB D-Cache Clean by Set-way Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
808 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
809 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
810
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
811 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
812 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
813
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
814 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
815 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
816 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
817
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
818 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
819 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
820
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
821 /* Instruction Tightly-Coupled Memory Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
822 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
823 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
824
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
825 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
826 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
827
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
828 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
829 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
830
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
831 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
832 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
833
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
834 /* Data Tightly-Coupled Memory Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
835 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
836 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
837
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
838 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
839 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
840
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
841 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
842 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
843
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
844 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
845 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
846
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
847 /* AHBP Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
848 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
849 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
850
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
851 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
852 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
853
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
854 /* L1 Cache Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
855 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
856 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
857
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
858 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
859 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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860
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
861 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
862 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
863
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
864 /* AHBS Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
865 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
866 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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867
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
868 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
869 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
870
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
871 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
872 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
873
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
874 /* Auxiliary Bus Fault Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
875 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
876 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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877
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
878 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
879 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
880
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
881 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
882 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
883
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
884 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
885 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
886
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
887 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
888 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
889
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
890 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
891 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
892
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
893 /*@} end of group CMSIS_SCB */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
894
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
895
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
896 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
897 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
898 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
899 \brief Type definitions for the System Control and ID Register not in the SCB
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
900 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
901 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
902
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
903 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
904 \brief Structure type to access the System Control and ID Register not in the SCB.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
905 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
906 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
907 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
908 uint32_t RESERVED0[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
909 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
910 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
911 } SCnSCB_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
912
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
913 /* Interrupt Controller Type Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
914 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
915 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
916
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
917 /* Auxiliary Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
918 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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919 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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920
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
921 #define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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922 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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923
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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924 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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925 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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926
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
927 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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928 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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929
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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930 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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931 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
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932
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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933 /*@} end of group CMSIS_SCnotSCB */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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934
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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935
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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936 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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937 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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938 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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939 \brief Type definitions for the System Timer Registers.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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940 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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941 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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942
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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943 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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944 \brief Structure type to access the System Timer (SysTick).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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945 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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946 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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947 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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948 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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949 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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950 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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951 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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952 } SysTick_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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953
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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954 /* SysTick Control / Status Register Definitions */
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955 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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956 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
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957
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958 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
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959 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
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960
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961 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
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962 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
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963
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964 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
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965 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
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966
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967 /* SysTick Reload Register Definitions */
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968 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
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969 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
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970
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971 /* SysTick Current Register Definitions */
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972 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
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973 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
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974
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975 /* SysTick Calibration Register Definitions */
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976 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
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977 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
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978
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979 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
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980 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
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981
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982 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
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983 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
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984
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985 /*@} end of group CMSIS_SysTick */
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986
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987
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988 /**
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989 \ingroup CMSIS_core_register
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990 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
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991 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
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992 @{
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993 */
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994
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995 /**
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996 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
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997 */
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998 typedef struct
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999 {
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1000 __OM union
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1001 {
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1002 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
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1003 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
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1004 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
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1005 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
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1006 uint32_t RESERVED0[864U];
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1007 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
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1008 uint32_t RESERVED1[15U];
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1009 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
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1010 uint32_t RESERVED2[15U];
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1011 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
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1012 uint32_t RESERVED3[29U];
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1013 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
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1014 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
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1015 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
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1016 uint32_t RESERVED4[43U];
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1017 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
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1018 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
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1019 uint32_t RESERVED5[6U];
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1020 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
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1021 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
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1022 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
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1023 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
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1024 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
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1025 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
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1026 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
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1027 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
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1028 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
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1029 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
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1030 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
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1031 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
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1032 } ITM_Type;
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1033
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1034 /* ITM Trace Privilege Register Definitions */
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1035 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
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1036 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
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1037
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1038 /* ITM Trace Control Register Definitions */
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1039 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
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1040 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
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1041
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1042 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
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1043 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
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1044
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1045 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
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1046 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
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1047
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1048 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
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1049 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
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1050
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1051 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
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1052 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
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1053
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1054 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
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1055 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
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1056
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1057 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
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1058 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
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1059
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1060 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
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1061 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
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1062
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1063 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
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1064 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
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1065
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1066 /* ITM Integration Write Register Definitions */
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1067 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
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1068 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
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1069
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1070 /* ITM Integration Read Register Definitions */
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1071 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
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1072 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
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1073
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1074 /* ITM Integration Mode Control Register Definitions */
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1075 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
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1076 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
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1077
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1078 /* ITM Lock Status Register Definitions */
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1079 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
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1080 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
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1081
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1082 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
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1083 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
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1084
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1085 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
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1086 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
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1087
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1088 /*@}*/ /* end of group CMSIS_ITM */
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1089
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1090
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1091 /**
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1092 \ingroup CMSIS_core_register
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1093 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
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1094 \brief Type definitions for the Data Watchpoint and Trace (DWT)
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1095 @{
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1096 */
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1097
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1098 /**
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1099 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
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1100 */
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1101 typedef struct
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1102 {
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1103 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
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1104 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
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1105 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
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1106 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
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1107 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
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1108 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
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1109 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
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1110 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
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1111 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
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1112 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
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1113 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
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1114 uint32_t RESERVED0[1U];
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1115 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
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1116 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
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1117 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
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1118 uint32_t RESERVED1[1U];
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1119 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
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1120 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
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1121 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
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1122 uint32_t RESERVED2[1U];
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1123 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
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1124 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
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1125 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
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1126 uint32_t RESERVED3[981U];
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1127 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
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1128 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
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1129 } DWT_Type;
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1130
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1131 /* DWT Control Register Definitions */
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1132 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1133 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
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1134
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1135 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1136 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
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1137
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1138 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1139 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1140
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1141 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1142 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
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1143
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1144 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1145 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
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1146
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1147 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1148 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1149
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1150 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1151 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1152
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1153 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1154 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
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1155
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1156 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
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1157 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
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1158
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1159 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
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1160 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
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1161
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1162 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
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1163 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
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1164
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1165 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
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1166 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
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1167
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1168 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1169 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
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1170
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1171 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
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1172 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
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1173
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1174 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
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1175 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
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1176
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1177 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
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1178 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
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1179
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1180 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
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1181 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
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1182
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1183 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
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1184 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
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1185
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1186 /* DWT CPI Count Register Definitions */
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1187 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
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1188 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
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1189
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1190 /* DWT Exception Overhead Count Register Definitions */
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1191 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
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1192 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
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1193
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1194 /* DWT Sleep Count Register Definitions */
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1195 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
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1196 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
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1197
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1198 /* DWT LSU Count Register Definitions */
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1199 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
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1200 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
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1201
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1202 /* DWT Folded-instruction Count Register Definitions */
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1203 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
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1204 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
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1205
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1206 /* DWT Comparator Mask Register Definitions */
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1207 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1208 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1209
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1210 /* DWT Comparator Function Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1211 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1212 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1213
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1214 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1215 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1216
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1217 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1218 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1219
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1220 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1221 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1222
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1223 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1224 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1225
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1226 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1227 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1228
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1229 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1230 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1231
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1232 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1233 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1234
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1235 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1236 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1237
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1238 /*@}*/ /* end of group CMSIS_DWT */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1239
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1240
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1241 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1242 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1243 \defgroup CMSIS_TPI Trace Port Interface (TPI)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1244 \brief Type definitions for the Trace Port Interface (TPI)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1245 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1246 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1247
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1248 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1249 \brief Structure type to access the Trace Port Interface Register (TPI).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1250 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1251 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1252 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1253 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1254 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1255 uint32_t RESERVED0[2U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1256 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1257 uint32_t RESERVED1[55U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1258 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1259 uint32_t RESERVED2[131U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1260 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1261 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1262 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1263 uint32_t RESERVED3[759U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1264 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1265 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1266 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1267 uint32_t RESERVED4[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1268 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1269 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1270 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1271 uint32_t RESERVED5[39U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1272 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1273 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1274 uint32_t RESERVED7[8U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1275 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1276 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1277 } TPI_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1278
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1279 /* TPI Asynchronous Clock Prescaler Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1280 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1281 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1282
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1283 /* TPI Selected Pin Protocol Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1284 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1285 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1286
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1287 /* TPI Formatter and Flush Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1288 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1289 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1290
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1291 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1292 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1293
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1294 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1295 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1296
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1297 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1298 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1299
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1300 /* TPI Formatter and Flush Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1301 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1302 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1303
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1304 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1305 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1306
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1307 /* TPI TRIGGER Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1308 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1309 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1310
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1311 /* TPI Integration ETM Data Register Definitions (FIFO0) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1312 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
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1313 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
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1314
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1315 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
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1316 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
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1317
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1318 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
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1319 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
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1320
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1321 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1322 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1323
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1324 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1325 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
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1326
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1327 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
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1328 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
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1329
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1330 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
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1331 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1332
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1333 /* TPI ITATBCTR2 Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1334 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1335 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1336
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1337 /* TPI Integration ITM Data Register Definitions (FIFO1) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1338 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1339 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1340
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1341 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1342 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1343
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1344 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1345 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1346
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1347 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1348 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1349
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1350 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1351 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1352
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1353 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1354 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
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1355
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1356 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1357 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1358
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1359 /* TPI ITATBCTR0 Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1360 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1361 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
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1362
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1363 /* TPI Integration Mode Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1364 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1365 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1366
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1367 /* TPI DEVID Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1368 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1369 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1370
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1371 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1372 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
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1373
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1374 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1375 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1376
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1377 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1378 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1379
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1380 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1381 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1382
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1383 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1384 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1385
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1386 /* TPI DEVTYPE Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1387 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1388 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1389
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1390 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1391 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1392
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1393 /*@}*/ /* end of group CMSIS_TPI */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1394
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1395
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1396 #if (__MPU_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1397 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1398 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1399 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1400 \brief Type definitions for the Memory Protection Unit (MPU)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1401 @{
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1402 */
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1403
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1404 /**
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1405 \brief Structure type to access the Memory Protection Unit (MPU).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1406 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1407 typedef struct
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1408 {
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1409 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1410 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1411 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
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1412 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
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1413 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
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1414 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
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1415 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
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1416 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
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1417 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
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1418 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
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1419 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
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1420 } MPU_Type;
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1421
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1422 /* MPU Type Register Definitions */
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1423 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
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1424 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
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1425
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1426 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
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1427 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
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1428
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1429 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
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1430 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
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1431
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1432 /* MPU Control Register Definitions */
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1433 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
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1434 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
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1435
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1436 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
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1437 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
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1438
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1439 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1440 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
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1441
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1442 /* MPU Region Number Register Definitions */
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1443 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
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1444 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
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1445
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1446 /* MPU Region Base Address Register Definitions */
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1447 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
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1448 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
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1449
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1450 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
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1451 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
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1452
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1453 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
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1454 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
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diff changeset
1455
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1456 /* MPU Region Attribute and Size Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1457 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1458 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1459
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1460 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1461 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1462
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1463 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1464 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1465
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1466 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1467 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1468
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1469 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1470 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1471
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1472 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1473 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1474
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1475 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1476 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1477
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1478 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1479 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1480
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1481 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1482 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1483
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1484 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1485 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1486
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1487 /*@} end of group CMSIS_MPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1488 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1489
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1490
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1491 #if (__FPU_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1492 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1493 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1494 \defgroup CMSIS_FPU Floating Point Unit (FPU)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1495 \brief Type definitions for the Floating Point Unit (FPU)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1496 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1497 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1498
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1499 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1500 \brief Structure type to access the Floating Point Unit (FPU).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1501 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1502 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1503 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1504 uint32_t RESERVED0[1U];
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1505 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1506 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1507 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1508 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1509 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1510 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1511 } FPU_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1512
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1513 /* Floating-Point Context Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1514 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1515 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1516
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1517 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1518 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1519
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1520 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1521 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1522
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1523 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1524 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1525
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1526 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1527 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1528
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1529 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1530 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1531
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1532 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1533 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1534
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1535 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1536 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1537
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1538 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1539 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1540
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1541 /* Floating-Point Context Address Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1542 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1543 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1544
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1545 /* Floating-Point Default Status Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1546 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1547 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1548
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1549 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1550 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1551
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1552 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1553 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1554
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1555 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1556 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1557
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1558 /* Media and FP Feature Register 0 Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1559 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1560 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1561
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1562 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1563 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1564
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1565 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1566 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1567
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1568 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1569 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1570
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1571 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1572 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1573
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1574 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1575 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1576
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1577 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1578 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1579
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1580 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1581 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1582
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1583 /* Media and FP Feature Register 1 Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1584 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1585 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1586
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1587 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1588 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1589
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1590 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1591 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1592
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1593 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1594 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1595
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1596 /* Media and FP Feature Register 2 Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1597
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1598 /*@} end of group CMSIS_FPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1599 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1600
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1601
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1602 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1603 \ingroup CMSIS_core_register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1604 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1605 \brief Type definitions for the Core Debug Registers
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1606 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1607 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1608
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1609 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1610 \brief Structure type to access the Core Debug Register (CoreDebug).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1611 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1612 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1613 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1614 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1615 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1616 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1617 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1618 } CoreDebug_Type;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1619
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1620 /* Debug Halting Control and Status Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1621 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1622 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1623
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1624 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1625 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1626
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1627 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1628 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1629
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1630 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1631 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1632
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1633 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1634 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1635
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1636 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1637 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1638
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1639 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1640 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1641
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1642 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1643 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1644
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1645 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1646 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1647
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1648 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1649 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1650
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1651 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1652 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1653
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1654 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1655 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1656
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1657 /* Debug Core Register Selector Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1658 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1659 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1660
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1661 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1662 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1663
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1664 /* Debug Exception and Monitor Control Register Definitions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1665 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1666 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1667
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1668 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1669 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1670
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1671 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1672 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1673
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1674 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1675 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1676
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1677 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1678 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1679
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1680 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1681 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1682
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1683 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1684 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1685
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1686 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1687 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1688
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1689 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1690 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1691
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1692 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1693 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1694
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1695 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1696 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1697
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1698 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1699 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1700
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1701 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1702 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
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1703
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1704 /*@} end of group CMSIS_CoreDebug */
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1705
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diff changeset
1706
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1707 /**
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diff changeset
1708 \ingroup CMSIS_core_register
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1709 \defgroup CMSIS_core_bitfield Core register bit field macros
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1710 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
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1711 @{
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1712 */
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1713
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1714 /**
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1715 \brief Mask and shift a bit field value for use in a register bit range.
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1716 \param[in] field Name of the register bit field.
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1717 \param[in] value Value of the bit field.
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1718 \return Masked and shifted value.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1719 */
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1720 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
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1721
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1722 /**
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1723 \brief Mask and shift a register value to extract a bit filed value.
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1724 \param[in] field Name of the register bit field.
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1725 \param[in] value Value of register.
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1726 \return Masked and shifted bit field value.
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1727 */
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1728 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
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1729
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1730 /*@} end of group CMSIS_core_bitfield */
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1731
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1732
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1733 /**
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1734 \ingroup CMSIS_core_register
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1735 \defgroup CMSIS_core_base Core Definitions
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1736 \brief Definitions for base addresses, unions, and structures.
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1737 @{
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1738 */
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1739
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diff changeset
1740 /* Memory mapping of Cortex-M4 Hardware */
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1741 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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1742 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
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1743 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
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1744 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
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1745 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
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1746 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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1747 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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1748 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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1749
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1750 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
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1751 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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1752 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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1753 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
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1754 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
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1755 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
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1756 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
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1757 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
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1758
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1759 #if (__MPU_PRESENT == 1U)
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1760 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
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1761 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
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1762 #endif
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1763
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1764 #if (__FPU_PRESENT == 1U)
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1765 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
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1766 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
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1767 #endif
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1768
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1769 /*@} */
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1770
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1771
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1772
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1773 /*******************************************************************************
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1774 * Hardware Abstraction Layer
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1775 Core Function Interface contains:
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1776 - Core NVIC Functions
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1777 - Core SysTick Functions
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1778 - Core Debug Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1779 - Core Register Access Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1780 ******************************************************************************/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1781 /**
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1782 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1783 */
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1784
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diff changeset
1785
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1786
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1787 /* ########################## NVIC functions #################################### */
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1788 /**
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1789 \ingroup CMSIS_Core_FunctionInterface
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1790 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
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1791 \brief Functions that manage interrupts and exceptions via the NVIC.
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1792 @{
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1793 */
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1794
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1795 /**
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1796 \brief Set Priority Grouping
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1797 \details Sets the priority grouping field using the required unlock sequence.
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1798 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
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1799 Only values from 0..7 are used.
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1800 In case of a conflict between priority grouping and available
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1801 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1802 \param [in] PriorityGroup Priority grouping field.
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1803 */
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1804 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
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1805 {
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1806 uint32_t reg_value;
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1807 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1808
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1809 reg_value = SCB->AIRCR; /* read old register configuration */
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1810 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
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1811 reg_value = (reg_value |
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1812 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
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1813 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
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1814 SCB->AIRCR = reg_value;
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1815 }
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1816
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1817
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1818 /**
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1819 \brief Get Priority Grouping
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1820 \details Reads the priority grouping field from the NVIC Interrupt Controller.
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1821 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
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1822 */
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1823 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
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1824 {
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1825 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
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1826 }
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1827
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1828
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1829 /**
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1830 \brief Enable External Interrupt
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1831 \details Enables a device-specific interrupt in the NVIC interrupt controller.
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1832 \param [in] IRQn External interrupt number. Value cannot be negative.
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1833 */
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1834 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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1835 {
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1836 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1837 }
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1838
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1839
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1840 /**
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1841 \brief Disable External Interrupt
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1842 \details Disables a device-specific interrupt in the NVIC interrupt controller.
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1843 \param [in] IRQn External interrupt number. Value cannot be negative.
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1844 */
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1845 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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1846 {
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1847 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1848 }
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1849
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diff changeset
1850
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1851 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1852 \brief Get Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1853 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1854 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1855 \return 0 Interrupt status is not pending.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1856 \return 1 Interrupt status is pending.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1857 */
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1858 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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1859 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1860 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1861 }
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1862
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1863
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1864 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1865 \brief Set Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1866 \details Sets the pending bit of an external interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1867 \param [in] IRQn Interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1868 */
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1869 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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1870 {
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1871 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1872 }
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1873
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1874
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1875 /**
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1876 \brief Clear Pending Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1877 \details Clears the pending bit of an external interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1878 \param [in] IRQn External interrupt number. Value cannot be negative.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1879 */
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1880 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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1881 {
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1882 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
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1883 }
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1884
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diff changeset
1885
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1886 /**
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1887 \brief Get Active Interrupt
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1888 \details Reads the active register in NVIC and returns the active bit.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1889 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1890 \return 0 Interrupt status is not active.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1891 \return 1 Interrupt status is active.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1892 */
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1893 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
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1894 {
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1895 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
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1896 }
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1897
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
1898
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1899 /**
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1900 \brief Set Interrupt Priority
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1901 \details Sets the priority of an interrupt.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1902 \note The priority cannot be set for every core interrupt.
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1903 \param [in] IRQn Interrupt number.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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1904 \param [in] priority Priority to set.
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1905 */
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1906 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
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1907 {
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1908 if ((int32_t)(IRQn) < 0)
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1909 {
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1910 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
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1911 }
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1912 else
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1913 {
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1914 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
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1915 }
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1916 }
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1917
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1918
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1919 /**
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1920 \brief Get Interrupt Priority
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1921 \details Reads the priority of an interrupt.
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1922 The interrupt number can be positive to specify an external (device specific) interrupt,
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1923 or negative to specify an internal (core) interrupt.
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1924 \param [in] IRQn Interrupt number.
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1925 \return Interrupt Priority.
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1926 Value is aligned automatically to the implemented priority bits of the microcontroller.
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1927 */
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1928 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
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1929 {
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1930
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1931 if ((int32_t)(IRQn) < 0)
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1932 {
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1933 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
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1934 }
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1935 else
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1936 {
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1937 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
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1938 }
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1939 }
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1940
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1941
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1942 /**
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1943 \brief Encode Priority
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1944 \details Encodes the priority for an interrupt with the given priority group,
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1945 preemptive priority value, and subpriority value.
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1946 In case of a conflict between priority grouping and available
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1947 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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1948 \param [in] PriorityGroup Used priority group.
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1949 \param [in] PreemptPriority Preemptive priority value (starting from 0).
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1950 \param [in] SubPriority Subpriority value (starting from 0).
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1951 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
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1952 */
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1953 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
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1954 {
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1955 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1956 uint32_t PreemptPriorityBits;
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1957 uint32_t SubPriorityBits;
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1958
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1959 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1960 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1961
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1962 return (
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1963 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
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1964 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
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1965 );
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1966 }
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1967
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1968
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1969 /**
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1970 \brief Decode Priority
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1971 \details Decodes an interrupt priority value with a given priority group to
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1972 preemptive priority value and subpriority value.
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1973 In case of a conflict between priority grouping and available
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1974 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
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1975 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
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1976 \param [in] PriorityGroup Used priority group.
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1977 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
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1978 \param [out] pSubPriority Subpriority value (starting from 0).
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1979 */
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1980 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
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1981 {
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1982 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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1983 uint32_t PreemptPriorityBits;
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1984 uint32_t SubPriorityBits;
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1985
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1986 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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1987 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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1988
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1989 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
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1990 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
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1991 }
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1992
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1993
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
1994 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
1995 \brief System Reset
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
1996 \details Initiates a system reset request to reset the MCU.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
1997 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
1998 __STATIC_INLINE void NVIC_SystemReset(void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
1999 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2000 __DSB(); /* Ensure all outstanding memory accesses included
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2001 buffered write are completed before reset */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2002 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2003 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2004 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2005 __DSB(); /* Ensure completion of memory access */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2006
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2007 for(;;) /* wait until reset */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2008 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2009 __NOP();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2010 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2011 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2012
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2013 /*@} end of CMSIS_Core_NVICFunctions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2014
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2015
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2016 /* ########################## FPU functions #################################### */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2017 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2018 \ingroup CMSIS_Core_FunctionInterface
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2019 \defgroup CMSIS_Core_FpuFunctions FPU Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2020 \brief Function that provides FPU type.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2021 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2022 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2023
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2024 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2025 \brief get FPU type
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2026 \details returns the FPU type
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2027 \returns
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2028 - \b 0: No FPU
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2029 - \b 1: Single precision FPU
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2030 - \b 2: Double + Single precision FPU
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2031 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2032 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2033 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2034 uint32_t mvfr0;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2035
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2036 mvfr0 = SCB->MVFR0;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2037 if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2038 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2039 return 2UL; /* Double + Single precision FPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2040 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2041 else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2042 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2043 return 1UL; /* Single precision FPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2044 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2045 else
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2046 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2047 return 0UL; /* No FPU */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2048 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2049 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2050
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2051
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2052 /*@} end of CMSIS_Core_FpuFunctions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2053
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2054
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2055
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2056 /* ########################## Cache functions #################################### */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2057 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2058 \ingroup CMSIS_Core_FunctionInterface
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2059 \defgroup CMSIS_Core_CacheFunctions Cache Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2060 \brief Functions that configure Instruction and Data cache.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2061 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2062 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2063
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2064 /* Cache Size ID Register Macros */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2065 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2066 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2067
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2068
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2069 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2070 \brief Enable I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2071 \details Turns on I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2072 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2073 __STATIC_INLINE void SCB_EnableICache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2074 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2075 #if (__ICACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2076 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2077 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2078 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2079 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2080 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2081 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2082 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2083 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2084
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2085
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2086 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2087 \brief Disable I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2088 \details Turns off I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2089 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2090 __STATIC_INLINE void SCB_DisableICache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2091 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2092 #if (__ICACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2093 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2094 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2095 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2096 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2097 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2098 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2099 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2100 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2101
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2102
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2103 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2104 \brief Invalidate I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2105 \details Invalidates I-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2106 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2107 __STATIC_INLINE void SCB_InvalidateICache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2108 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2109 #if (__ICACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2110 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2111 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2112 SCB->ICIALLU = 0UL;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2113 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2114 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2115 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2116 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2117
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2118
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2119 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2120 \brief Enable D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2121 \details Turns on D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2122 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2123 __STATIC_INLINE void SCB_EnableDCache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2124 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2125 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2126 uint32_t ccsidr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2127 uint32_t sets;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2128 uint32_t ways;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2129
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2130 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2131 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2132
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2133 ccsidr = SCB->CCSIDR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2134
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2135 /* invalidate D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2137 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2139 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2140 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2141 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2142 #if defined ( __CC_ARM )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2143 __schedule_barrier();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2144 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2145 } while (ways--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2146 } while(sets--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2147 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2148
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2149 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2150
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2151 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2152 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2153 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2154 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2155
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2156
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2157 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2158 \brief Disable D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2159 \details Turns off D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2160 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2161 __STATIC_INLINE void SCB_DisableDCache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2162 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2163 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2164 uint32_t ccsidr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2165 uint32_t sets;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2166 uint32_t ways;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2167
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2168 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2169 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2170
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2171 ccsidr = SCB->CCSIDR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2172
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2173 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2174
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2175 /* clean & invalidate D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2176 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2177 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2178 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2179 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2180 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2181 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2182 #if defined ( __CC_ARM )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2183 __schedule_barrier();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2184 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2185 } while (ways--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2186 } while(sets--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2187
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2188 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2189 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2190 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2191 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2192
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2193
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2194 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2195 \brief Invalidate D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2196 \details Invalidates D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2197 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2198 __STATIC_INLINE void SCB_InvalidateDCache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2199 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2200 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2201 uint32_t ccsidr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2202 uint32_t sets;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2203 uint32_t ways;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2204
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2205 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2206 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2207
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2208 ccsidr = SCB->CCSIDR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2209
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2210 /* invalidate D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2211 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2212 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2213 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2214 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2215 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2216 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2217 #if defined ( __CC_ARM )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2218 __schedule_barrier();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2219 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2220 } while (ways--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2221 } while(sets--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2222
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2223 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2224 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2225 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2226 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2227
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2228
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2229 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2230 \brief Clean D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2231 \details Cleans D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2232 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2233 __STATIC_INLINE void SCB_CleanDCache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2234 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2235 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2236 uint32_t ccsidr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2237 uint32_t sets;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2238 uint32_t ways;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2239
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2240 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2241 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2242
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2243 ccsidr = SCB->CCSIDR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2244
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2245 /* clean D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2246 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2247 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2248 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2249 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2250 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2251 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2252 #if defined ( __CC_ARM )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2253 __schedule_barrier();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2254 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2255 } while (ways--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2256 } while(sets--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2257
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2258 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2259 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2260 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2261 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2262
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2263
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2264 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2265 \brief Clean & Invalidate D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2266 \details Cleans and Invalidates D-Cache
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2267 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2268 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2269 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2270 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2271 uint32_t ccsidr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2272 uint32_t sets;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2273 uint32_t ways;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2274
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2275 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2276 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2277
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2278 ccsidr = SCB->CCSIDR;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2279
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2280 /* clean & invalidate D-Cache */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2281 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2282 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2283 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2284 do {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2285 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2286 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2287 #if defined ( __CC_ARM )
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2288 __schedule_barrier();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2289 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2290 } while (ways--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2291 } while(sets--);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2292
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2293 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2294 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2295 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2296 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2297
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2298
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2299 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2300 \brief D-Cache Invalidate by address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2301 \details Invalidates D-Cache for the given address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2302 \param[in] addr address (aligned to 32-byte boundary)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2303 \param[in] dsize size of memory block (in number of bytes)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2304 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2305 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2306 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2307 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2308 int32_t op_size = dsize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2309 uint32_t op_addr = (uint32_t)addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2310 int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2311
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2312 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2313
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2314 while (op_size > 0) {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2315 SCB->DCIMVAC = op_addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2316 op_addr += linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2317 op_size -= linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2318 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2319
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2320 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2321 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2322 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2323 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2324
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2325
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2326 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2327 \brief D-Cache Clean by address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2328 \details Cleans D-Cache for the given address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2329 \param[in] addr address (aligned to 32-byte boundary)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2330 \param[in] dsize size of memory block (in number of bytes)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2331 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2332 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2333 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2334 #if (__DCACHE_PRESENT == 1)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2335 int32_t op_size = dsize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2336 uint32_t op_addr = (uint32_t) addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2337 int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2338
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2339 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2340
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2341 while (op_size > 0) {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2342 SCB->DCCMVAC = op_addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2343 op_addr += linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2344 op_size -= linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2345 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2346
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2347 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2348 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2349 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2350 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2351
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2352
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2353 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2354 \brief D-Cache Clean and Invalidate by address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2355 \details Cleans and invalidates D_Cache for the given address
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2356 \param[in] addr address (aligned to 32-byte boundary)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2357 \param[in] dsize size of memory block (in number of bytes)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2358 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2359 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2360 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2361 #if (__DCACHE_PRESENT == 1U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2362 int32_t op_size = dsize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2363 uint32_t op_addr = (uint32_t) addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2364 int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2365
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2366 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2367
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2368 while (op_size > 0) {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2369 SCB->DCCIMVAC = op_addr;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2370 op_addr += linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2371 op_size -= linesize;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2372 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2373
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2374 __DSB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2375 __ISB();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2376 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2377 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2378
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2379
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2380 /*@} end of CMSIS_Core_CacheFunctions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2381
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2382
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2383
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2384 /* ################################## SysTick function ############################################ */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2385 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2386 \ingroup CMSIS_Core_FunctionInterface
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2387 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2388 \brief Functions that configure the System.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2389 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2390 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2391
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2392 #if (__Vendor_SysTickConfig == 0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2393
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2394 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2395 \brief System Tick Configuration
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2396 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2397 Counter is in free running mode to generate periodic interrupts.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2398 \param [in] ticks Number of ticks between two interrupts.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2399 \return 0 Function succeeded.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2400 \return 1 Function failed.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2401 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2402 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2403 must contain a vendor-specific implementation of this function.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2404 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2405 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2406 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2407 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2408 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2409 return (1UL); /* Reload value impossible */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2410 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2411
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2412 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2413 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2414 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2415 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2416 SysTick_CTRL_TICKINT_Msk |
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2417 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2418 return (0UL); /* Function successful */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
2419 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2420
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2421 #endif
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Ideenmodellierer
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diff changeset
2422
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2423 /*@} end of CMSIS_Core_SysTickFunctions */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2424
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2425
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2426
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2427 /* ##################################### Debug In/Output function ########################################### */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2428 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2429 \ingroup CMSIS_Core_FunctionInterface
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff changeset
2430 \defgroup CMSIS_core_DebugFunctions ITM Functions
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2431 \brief Functions that access the ITM debug interface.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2432 @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2433 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2434
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2435 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2436 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff changeset
2437
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2438
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2439 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2440 \brief ITM Send Character
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2441 \details Transmits a character via the ITM channel 0, and
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2442 \li Just returns when no debugger is connected that has booked the output.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2443 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2444 \param [in] ch Character to transmit.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2445 \returns Character to transmit.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2446 */
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diff changeset
2447 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
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diff changeset
2448 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2449 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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Ideenmodellierer
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2450 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2451 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2452 while (ITM->PORT[0U].u32 == 0UL)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2453 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2454 __NOP();
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2455 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2456 ITM->PORT[0U].u8 = (uint8_t)ch;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2457 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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diff changeset
2458 return (ch);
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2459 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2460
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2461
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2462 /**
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2463 \brief ITM Receive Character
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2464 \details Inputs a character via the external variable \ref ITM_RxBuffer.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2465 \return Received character.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2466 \return -1 No character pending.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2467 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2468 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2469 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2470 int32_t ch = -1; /* no character available */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2471
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2472 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2473 {
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2474 ch = ITM_RxBuffer;
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2475 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
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2476 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2477
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2478 return (ch);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2479 }
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2480
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2481
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2482 /**
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2483 \brief ITM Check Character
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2484 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
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2485 \return 0 No character available.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2486 \return 1 Character available.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2487 */
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2488 __STATIC_INLINE int32_t ITM_CheckChar (void)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2489 {
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2490
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2491 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2492 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2493 return (0); /* no character available */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2494 }
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2495 else
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2496 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2497 return (1); /* character available */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2498 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2499 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2500
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2501 /*@} end of CMSIS_core_DebugFunctions */
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2502
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2503
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2504
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2505
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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2506 #ifdef __cplusplus
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2507 }
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2508 #endif
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2509
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2510 #endif /* __CORE_CM7_H_DEPENDANT */
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2511
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2512 #endif /* __CMSIS_GENERIC */