ostc4: Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal

author	heinrichsweikamp
date	Tue, 28 Jan 2025 16:15:31 +0100 (2 months ago)
parents	c78bcbd5deda
children

rev	line source
128 c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	1 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	2 ******************************************************************************
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	3 * @file stm32f4xx_hal_rcc.h
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	4 * @author MCD Application Team
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	5 * @brief Header file of RCC HAL module.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	6 ******************************************************************************
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	7 * @attention
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	8 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	10 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	11 * Redistribution and use in source and binary forms, with or without modification,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	12 * are permitted provided that the following conditions are met:
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	13 * 1. Redistributions of source code must retain the above copyright notice,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	14 * this list of conditions and the following disclaimer.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	15 * 2. Redistributions in binary form must reproduce the above copyright notice,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	16 * this list of conditions and the following disclaimer in the documentation
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	17 * and/or other materials provided with the distribution.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	19 * may be used to endorse or promote products derived from this software
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	20 * without specific prior written permission.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	21 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	32 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	33 ******************************************************************************
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	34 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	35
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	36 /* Define to prevent recursive inclusion -------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	37 #ifndef __STM32F4xx_HAL_RCC_H
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	38 #define __STM32F4xx_HAL_RCC_H
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	39
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	40 #ifdef __cplusplus
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	41 extern "C" {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	42 #endif
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	43
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	44 /* Includes ------------------------------------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	45 #include "stm32f4xx_hal_def.h"
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	46
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	47 /* Include RCC HAL Extended module */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	48 /* (include on top of file since RCC structures are defined in extended file) */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	49 #include "stm32f4xx_hal_rcc_ex.h"
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	50
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	51 /** @addtogroup STM32F4xx_HAL_Driver
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	52 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	53 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	54
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	55 /** @addtogroup RCC
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	56 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	57 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	58
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	59 /* Exported types ------------------------------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	60 /** @defgroup RCC_Exported_Types RCC Exported Types
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	61 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	62 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	63
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	64 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	65 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	66 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	67 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	68 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	69 uint32_t OscillatorType; /*!< The oscillators to be configured.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	70 This parameter can be a value of @ref RCC_Oscillator_Type */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	71
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	72 uint32_t HSEState; /*!< The new state of the HSE.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	73 This parameter can be a value of @ref RCC_HSE_Config */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	74
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	75 uint32_t LSEState; /*!< The new state of the LSE.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	76 This parameter can be a value of @ref RCC_LSE_Config */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	77
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	78 uint32_t HSIState; /*!< The new state of the HSI.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	79 This parameter can be a value of @ref RCC_HSI_Config */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	80
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	81 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	82 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	83
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	84 uint32_t LSIState; /*!< The new state of the LSI.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	85 This parameter can be a value of @ref RCC_LSI_Config */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	86
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	87 RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	88 }RCC_OscInitTypeDef;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	89
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	90 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	91 * @brief RCC System, AHB and APB busses clock configuration structure definition
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	92 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	93 typedef struct
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	94 {
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	95 uint32_t ClockType; /*!< The clock to be configured.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	96 This parameter can be a value of @ref RCC_System_Clock_Type */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	97
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	98 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	99 This parameter can be a value of @ref RCC_System_Clock_Source */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	100
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	102 This parameter can be a value of @ref RCC_AHB_Clock_Source */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	103
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	106
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	109
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	110 }RCC_ClkInitTypeDef;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	111
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	112 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	113 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	114 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	115
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	116 /* Exported constants --------------------------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	117 /** @defgroup RCC_Exported_Constants RCC Exported Constants
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	118 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	119 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	120
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	121 /** @defgroup RCC_Oscillator_Type Oscillator Type
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	122 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	123 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	129 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	130 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	131 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	132
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	133 /** @defgroup RCC_HSE_Config HSE Config
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	134 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	135 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	136 #define RCC_HSE_OFF 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	137 #define RCC_HSE_ON RCC_CR_HSEON
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	139 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	140 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	141 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	142
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	143 /** @defgroup RCC_LSE_Config LSE Config
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	144 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	145 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	146 #define RCC_LSE_OFF 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	147 #define RCC_LSE_ON RCC_BDCR_LSEON
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	149 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	150 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	151 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	152
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	153 /** @defgroup RCC_HSI_Config HSI Config
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	154 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	155 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	156 #define RCC_HSI_OFF ((uint8_t)0x00)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	157 #define RCC_HSI_ON ((uint8_t)0x01)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	158
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	160 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	161 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	162 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	163
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	164 /** @defgroup RCC_LSI_Config LSI Config
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	165 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	166 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	167 #define RCC_LSI_OFF ((uint8_t)0x00)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	168 #define RCC_LSI_ON ((uint8_t)0x01)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	169 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	170 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	171 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	172
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	173 /** @defgroup RCC_PLL_Config PLL Config
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	174 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	175 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	176 #define RCC_PLL_NONE ((uint8_t)0x00)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	177 #define RCC_PLL_OFF ((uint8_t)0x01)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	178 #define RCC_PLL_ON ((uint8_t)0x02)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	179 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	180 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	181 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	182
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	184 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	185 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	186 #define RCC_PLLP_DIV2 0x00000002U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	187 #define RCC_PLLP_DIV4 0x00000004U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	188 #define RCC_PLLP_DIV6 0x00000006U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	189 #define RCC_PLLP_DIV8 0x00000008U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	190 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	191 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	192 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	193
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	195 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	196 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	199 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	200 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	201 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	202
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	203 /** @defgroup RCC_System_Clock_Type System Clock Type
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	204 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	205 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	207 #define RCC_CLOCKTYPE_HCLK 0x00000002U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	210 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	211 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	212 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	213
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	214 /** @defgroup RCC_System_Clock_Source System Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	216 * STM32F446xx devices.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	217 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	218 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	223 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	224 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	225 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	226
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	229 * STM32F446xx devices.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	230 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	231 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 \| RCC_CFGR_SWS_1)) /!< PLLR used as system clock /
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	236 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	237 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	238 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	239
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	241 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	242 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	252 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	253 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	254 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	255
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	257 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	258 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	264 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	265 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	266 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	267
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	269 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	270 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	305 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	306 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	307 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	308
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	309 /** @defgroup RCC_MCO_Index MCO Index
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	310 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	311 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	312 #define RCC_MCO1 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	313 #define RCC_MCO2 0x00000001U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	314 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	315 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	316 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	317
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	319 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	320 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	321 #define RCC_MCO1SOURCE_HSI 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	325 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	326 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	327 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	328
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	330 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	331 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	332 #define RCC_MCODIV_1 0x00000000U
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	337 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	338 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	339 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	340
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	341 /** @defgroup RCC_Interrupt Interrupts
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	342 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	343 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	344 #define RCC_IT_LSIRDY ((uint8_t)0x01)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	345 #define RCC_IT_LSERDY ((uint8_t)0x02)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	346 #define RCC_IT_HSIRDY ((uint8_t)0x04)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	347 #define RCC_IT_HSERDY ((uint8_t)0x08)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	348 #define RCC_IT_PLLRDY ((uint8_t)0x10)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	350 #define RCC_IT_CSS ((uint8_t)0x80)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	351 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	352 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	353 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	354
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	355 /** @defgroup RCC_Flag Flags
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	356 * Elements values convention: 0XXYYYYYb
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	357 * - YYYYY : Flag position in the register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	358 * - 0XX : Register index
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	359 * - 01: CR register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	360 * - 10: BDCR register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	361 * - 11: CSR register
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	362 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	363 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	364 /* Flags in the CR register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	369
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	370 /* Flags in the BDCR register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	372
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	373 /* Flags in the CSR register */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	375 #define RCC_FLAG_BORRST ((uint8_t)0x79)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	382 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	383 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	384 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	385
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	386 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	387 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	388 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	389
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	390 /* Exported macro ------------------------------------------------------------*/
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	391 /** @defgroup RCC_Exported_Macros RCC Exported Macros
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	392 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	393 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	394
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	396 * @brief Enable or disable the AHB1 peripheral clock.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	397 * @note After reset, the peripheral clock (used for registers read/write access)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	398 * is disabled and the application software has to enable this clock before
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	399 * using it.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	400 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	401 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	403 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	405 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	407 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	408 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	410 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	412 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	414 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	415 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	417 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	419 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	421 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	422 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	424 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	426 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	428 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	429 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	431 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	433 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	435 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	436 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	438 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	440 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	442 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	443 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	444
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	451 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	452 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	453 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	454
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	456 * @brief Get the enable or disable status of the AHB1 peripheral clock.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	457 * @note After reset, the peripheral clock (used for registers read/write access)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	458 * is disabled and the application software has to enable this clock before
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	459 * using it.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	460 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	461 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	468
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	475 /**
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	476 * @}
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	477 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	478
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	481 * @note After reset, the peripheral clock (used for registers read/write access)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	482 * is disabled and the application software has to enable this clock before
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	483 * using it.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	484 * @{
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	485 */
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	487 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	489 /* Delay after an RCC peripheral clock enabling */ \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	491 UNUSED(tmpreg); \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	492 } while(0U)
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	494 __IO uint32_t tmpreg = 0x00U; \
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure Ideenmodellierer parents: diff changeset	495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
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128

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1 /**

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2 ******************************************************************************

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3 * @file stm32f4xx_hal_rcc.h

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4 * @author MCD Application Team

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5 * @brief Header file of RCC HAL module.

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6 ******************************************************************************

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7 * @attention

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8 *

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10 *

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11 * Redistribution and use in source and binary forms, with or without modification,

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12 * are permitted provided that the following conditions are met:

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13 * 1. Redistributions of source code must retain the above copyright notice,

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14 * this list of conditions and the following disclaimer.

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15 * 2. Redistributions in binary form must reproduce the above copyright notice,

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16 * this list of conditions and the following disclaimer in the documentation

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17 * and/or other materials provided with the distribution.

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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors

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19 * may be used to endorse or promote products derived from this software

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20 * without specific prior written permission.

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21 *

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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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32 *

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33 ******************************************************************************

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34 */

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35

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36 /* Define to prevent recursive inclusion -------------------------------------*/

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37 #ifndef __STM32F4xx_HAL_RCC_H

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38 #define __STM32F4xx_HAL_RCC_H

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39

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40 #ifdef __cplusplus

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41 extern "C" {

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42 #endif

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43

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44 /* Includes ------------------------------------------------------------------*/

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45 #include "stm32f4xx_hal_def.h"

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46

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47 /* Include RCC HAL Extended module */

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48 /* (include on top of file since RCC structures are defined in extended file) */

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49 #include "stm32f4xx_hal_rcc_ex.h"

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50

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51 /** @addtogroup STM32F4xx_HAL_Driver

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52 * @{

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53 */

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54

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55 /** @addtogroup RCC

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56 * @{

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57 */

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58

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59 /* Exported types ------------------------------------------------------------*/

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60 /** @defgroup RCC_Exported_Types RCC Exported Types

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61 * @{

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62 */

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63

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64 /**

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65 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition

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66 */

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67 typedef struct

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68 {

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69 uint32_t OscillatorType; /*!< The oscillators to be configured.

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70 This parameter can be a value of @ref RCC_Oscillator_Type */

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71

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72 uint32_t HSEState; /*!< The new state of the HSE.

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73 This parameter can be a value of @ref RCC_HSE_Config */

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74

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75 uint32_t LSEState; /*!< The new state of the LSE.

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76 This parameter can be a value of @ref RCC_LSE_Config */

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77

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78 uint32_t HSIState; /*!< The new state of the HSI.

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79 This parameter can be a value of @ref RCC_HSI_Config */

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80

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81 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).

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82 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */

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83

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84 uint32_t LSIState; /*!< The new state of the LSI.

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85 This parameter can be a value of @ref RCC_LSI_Config */

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86

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87 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */

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88 }RCC_OscInitTypeDef;

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89

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90 /**

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91 * @brief RCC System, AHB and APB busses clock configuration structure definition

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92 */

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93 typedef struct

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94 {

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95 uint32_t ClockType; /*!< The clock to be configured.

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96 This parameter can be a value of @ref RCC_System_Clock_Type */

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97

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98 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.

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99 This parameter can be a value of @ref RCC_System_Clock_Source */

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100

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101 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).

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102 This parameter can be a value of @ref RCC_AHB_Clock_Source */

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103

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104 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).

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105 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */

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106

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107 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).

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108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */

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109

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110 }RCC_ClkInitTypeDef;

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111

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112 /**

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113 * @}

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114 */

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115

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116 /* Exported constants --------------------------------------------------------*/

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117 /** @defgroup RCC_Exported_Constants RCC Exported Constants

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118 * @{

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119 */

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120

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121 /** @defgroup RCC_Oscillator_Type Oscillator Type

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122 * @{

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123 */

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124 #define RCC_OSCILLATORTYPE_NONE 0x00000000U

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125 #define RCC_OSCILLATORTYPE_HSE 0x00000001U

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126 #define RCC_OSCILLATORTYPE_HSI 0x00000002U

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127 #define RCC_OSCILLATORTYPE_LSE 0x00000004U

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128 #define RCC_OSCILLATORTYPE_LSI 0x00000008U

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129 /**

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130 * @}

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131 */

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132

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133 /** @defgroup RCC_HSE_Config HSE Config

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134 * @{

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135 */

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136 #define RCC_HSE_OFF 0x00000000U

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137 #define RCC_HSE_ON RCC_CR_HSEON

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138 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

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139 /**

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140 * @}

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141 */

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142

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143 /** @defgroup RCC_LSE_Config LSE Config

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144 * @{

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145 */

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146 #define RCC_LSE_OFF 0x00000000U

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147 #define RCC_LSE_ON RCC_BDCR_LSEON

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148 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

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149 /**

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150 * @}

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151 */

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152

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153 /** @defgroup RCC_HSI_Config HSI Config

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154 * @{

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155 */

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156 #define RCC_HSI_OFF ((uint8_t)0x00)

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157 #define RCC_HSI_ON ((uint8_t)0x01)

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158

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159 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */

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160 /**

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161 * @}

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162 */

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163

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164 /** @defgroup RCC_LSI_Config LSI Config

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165 * @{

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166 */

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167 #define RCC_LSI_OFF ((uint8_t)0x00)

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168 #define RCC_LSI_ON ((uint8_t)0x01)

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169 /**

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170 * @}

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171 */

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172

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173 /** @defgroup RCC_PLL_Config PLL Config

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174 * @{

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175 */

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176 #define RCC_PLL_NONE ((uint8_t)0x00)

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177 #define RCC_PLL_OFF ((uint8_t)0x01)

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178 #define RCC_PLL_ON ((uint8_t)0x02)

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179 /**

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180 * @}

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181 */

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182

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183 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider

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184 * @{

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185 */

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186 #define RCC_PLLP_DIV2 0x00000002U

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187 #define RCC_PLLP_DIV4 0x00000004U

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188 #define RCC_PLLP_DIV6 0x00000006U

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189 #define RCC_PLLP_DIV8 0x00000008U

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190 /**

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191 * @}

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192 */

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193

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194 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source

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195 * @{

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196 */

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197 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI

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198 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE

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199 /**

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200 * @}

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201 */

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202

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203 /** @defgroup RCC_System_Clock_Type System Clock Type

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204 * @{

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205 */

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206 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U

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207 #define RCC_CLOCKTYPE_HCLK 0x00000002U

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208 #define RCC_CLOCKTYPE_PCLK1 0x00000004U

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209 #define RCC_CLOCKTYPE_PCLK2 0x00000008U

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210 /**

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211 * @}

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212 */

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213

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214 /** @defgroup RCC_System_Clock_Source System Clock Source

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215 * @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for

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216 * STM32F446xx devices.

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217 * @{

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218 */

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219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

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220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

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221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

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222 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))

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223 /**

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224 * @}

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225 */

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226

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227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status

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228 * @note The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for

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229 * STM32F446xx devices.

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230 * @{

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231 */

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232 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */

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233 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */

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234 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */

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235 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1)) /*!< PLLR used as system clock */

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236 /**

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237 * @}

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238 */

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239

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240 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source

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241 * @{

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242 */

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243 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

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244 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

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245 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

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246 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

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247 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

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248 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

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249 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

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250 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

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251 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

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252 /**

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253 * @}

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254 */

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255

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256 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source

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257 * @{

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258 */

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259 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

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260 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

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261 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

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262 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

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263 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

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264 /**

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265 * @}

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266 */

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267

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268 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source

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269 * @{

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270 */

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271 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U

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272 #define RCC_RTCCLKSOURCE_LSE 0x00000100U

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273 #define RCC_RTCCLKSOURCE_LSI 0x00000200U

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274 #define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U

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275 #define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U

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276 #define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U

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277 #define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U

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278 #define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U

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279 #define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U

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280 #define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U

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281 #define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U

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282 #define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U

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283 #define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U

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284 #define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U

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285 #define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U

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286 #define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U

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287 #define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U

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288 #define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U

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289 #define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U

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290 #define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U

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291 #define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U

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292 #define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U

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293 #define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U

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294 #define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U

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295 #define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U

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296 #define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U

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297 #define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U

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298 #define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U

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299 #define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U

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300 #define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U

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301 #define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U

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302 #define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U

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303 #define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U

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304 #define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U

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305 /**

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306 * @}

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307 */

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308

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309 /** @defgroup RCC_MCO_Index MCO Index

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310 * @{

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311 */

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312 #define RCC_MCO1 0x00000000U

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313 #define RCC_MCO2 0x00000001U

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314 /**

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315 * @}

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316 */

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317

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318 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source

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319 * @{

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320 */

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321 #define RCC_MCO1SOURCE_HSI 0x00000000U

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322 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

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323 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

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324 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1

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325 /**

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326 * @}

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327 */

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328

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329 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler

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330 * @{

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331 */

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332 #define RCC_MCODIV_1 0x00000000U

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333 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2

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334 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

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335 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

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336 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE

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337 /**

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338 * @}

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339 */

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340

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341 /** @defgroup RCC_Interrupt Interrupts

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342 * @{

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343 */

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344 #define RCC_IT_LSIRDY ((uint8_t)0x01)

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345 #define RCC_IT_LSERDY ((uint8_t)0x02)

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346 #define RCC_IT_HSIRDY ((uint8_t)0x04)

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347 #define RCC_IT_HSERDY ((uint8_t)0x08)

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348 #define RCC_IT_PLLRDY ((uint8_t)0x10)

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349 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)

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350 #define RCC_IT_CSS ((uint8_t)0x80)

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351 /**

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352 * @}

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353 */

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354

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355 /** @defgroup RCC_Flag Flags

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356 * Elements values convention: 0XXYYYYYb

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357 * - YYYYY : Flag position in the register

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358 * - 0XX : Register index

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359 * - 01: CR register

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360 * - 10: BDCR register

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361 * - 11: CSR register

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362 * @{

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363 */

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364 /* Flags in the CR register */

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365 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)

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366 #define RCC_FLAG_HSERDY ((uint8_t)0x31)

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367 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)

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368 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)

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369

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370 /* Flags in the BDCR register */

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371 #define RCC_FLAG_LSERDY ((uint8_t)0x41)

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372

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373 /* Flags in the CSR register */

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374 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)

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375 #define RCC_FLAG_BORRST ((uint8_t)0x79)

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376 #define RCC_FLAG_PINRST ((uint8_t)0x7A)

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377 #define RCC_FLAG_PORRST ((uint8_t)0x7B)

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378 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)

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379 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)

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380 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)

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381 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)

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382 /**

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383 * @}

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384 */

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385

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386 /**

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387 * @}

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388 */

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389

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390 /* Exported macro ------------------------------------------------------------*/

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391 /** @defgroup RCC_Exported_Macros RCC Exported Macros

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392 * @{

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393 */

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394

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395 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable

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396 * @brief Enable or disable the AHB1 peripheral clock.

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397 * @note After reset, the peripheral clock (used for registers read/write access)

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398 * is disabled and the application software has to enable this clock before

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399 * using it.

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400 * @{

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401 */

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402 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \

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403 __IO uint32_t tmpreg = 0x00U; \

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404 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\

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405 /* Delay after an RCC peripheral clock enabling */ \

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406 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\

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407 UNUSED(tmpreg); \

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408 } while(0U)

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409 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \

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410 __IO uint32_t tmpreg = 0x00U; \

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411 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\

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412 /* Delay after an RCC peripheral clock enabling */ \

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413 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\

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414 UNUSED(tmpreg); \

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415 } while(0U)

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416 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \

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417 __IO uint32_t tmpreg = 0x00U; \

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418 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\

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419 /* Delay after an RCC peripheral clock enabling */ \

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420 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\

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421 UNUSED(tmpreg); \

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422 } while(0U)

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423 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \

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424 __IO uint32_t tmpreg = 0x00U; \

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425 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\

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426 /* Delay after an RCC peripheral clock enabling */ \

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427 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\

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428 UNUSED(tmpreg); \

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429 } while(0U)

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430 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \

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431 __IO uint32_t tmpreg = 0x00U; \

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432 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

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433 /* Delay after an RCC peripheral clock enabling */ \

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434 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

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435 UNUSED(tmpreg); \

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436 } while(0U)

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437 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \

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438 __IO uint32_t tmpreg = 0x00U; \

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439 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

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440 /* Delay after an RCC peripheral clock enabling */ \

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441 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

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442 UNUSED(tmpreg); \

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443 } while(0U)

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444

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445 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))

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446 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))

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447 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))

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448 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))

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449 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))

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450 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))

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451 /**

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452 * @}

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453 */

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454

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455 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status

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456 * @brief Get the enable or disable status of the AHB1 peripheral clock.

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457 * @note After reset, the peripheral clock (used for registers read/write access)

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458 * is disabled and the application software has to enable this clock before

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459 * using it.

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460 * @{

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461 */

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462 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)

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463 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)

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464 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)

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465 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)

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466 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)

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467 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)

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468

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469 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)

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470 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)

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471 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)

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472 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)

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473 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)

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474 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)

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475 /**

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476 * @}

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477 */

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478

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479 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable

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480 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.

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481 * @note After reset, the peripheral clock (used for registers read/write access)

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482 * is disabled and the application software has to enable this clock before

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483 * using it.

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484 * @{

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485 */

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486 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \

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487 __IO uint32_t tmpreg = 0x00U; \

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488 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\

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489 /* Delay after an RCC peripheral clock enabling */ \

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490 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\

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491 UNUSED(tmpreg); \

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492 } while(0U)

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493 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \

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494 __IO uint32_t tmpreg = 0x00U; \

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495 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\

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496 /* Delay after an RCC peripheral clock enabling */ \

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497 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\

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498 UNUSED(tmpreg); \

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499 } while(0U)

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500 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \

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501 __IO uint32_t tmpreg = 0x00U; \

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502 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\

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503 /* Delay after an RCC peripheral clock enabling */ \

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504 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\

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505 UNUSED(tmpreg); \

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506 } while(0U)

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507 #define __HAL_RCC_USART2_CLK_ENABLE() do { \

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508 __IO uint32_t tmpreg = 0x00U; \

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509 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\

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510 /* Delay after an RCC peripheral clock enabling */ \

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511 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\

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512 UNUSED(tmpreg); \

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513 } while(0U)

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514 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \

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515 __IO uint32_t tmpreg = 0x00U; \

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516 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\

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517 /* Delay after an RCC peripheral clock enabling */ \

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518 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\

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519 UNUSED(tmpreg); \

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520 } while(0U)

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521 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \

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522 __IO uint32_t tmpreg = 0x00U; \

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523 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\

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524 /* Delay after an RCC peripheral clock enabling */ \

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525 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\

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526 UNUSED(tmpreg); \

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527 } while(0U)

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528 #define __HAL_RCC_PWR_CLK_ENABLE() do { \

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529 __IO uint32_t tmpreg = 0x00U; \

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530 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\

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531 /* Delay after an RCC peripheral clock enabling */ \

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532 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\

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533 UNUSED(tmpreg); \

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534 } while(0U)

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535

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536 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

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537 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

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538 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))

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539 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

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540 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

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541 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))

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542 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

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543 /**

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544 * @}

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545 */

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546

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547 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status

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548 * @brief Get the enable or disable status of the APB1 peripheral clock.

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549 * @note After reset, the peripheral clock (used for registers read/write access)

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550 * is disabled and the application software has to enable this clock before

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551 * using it.

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552 * @{

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553 */

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554 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)

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555 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

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556 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)

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557 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

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558 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

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559 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)

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560 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

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561

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562 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)

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563 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

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564 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)

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565 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

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566 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

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567 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)

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568 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

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569 /**

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570 * @}

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571 */

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572

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573 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable

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574 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.

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575 * @note After reset, the peripheral clock (used for registers read/write access)

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576 * is disabled and the application software has to enable this clock before

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577 * using it.

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578 * @{

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579 */

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580 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \

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581 __IO uint32_t tmpreg = 0x00U; \

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582 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

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583 /* Delay after an RCC peripheral clock enabling */ \

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584 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

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585 UNUSED(tmpreg); \

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586 } while(0U)

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587 #define __HAL_RCC_USART1_CLK_ENABLE() do { \

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588 __IO uint32_t tmpreg = 0x00U; \

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589 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

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590 /* Delay after an RCC peripheral clock enabling */ \

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591 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

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592 UNUSED(tmpreg); \

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593 } while(0U)

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594 #define __HAL_RCC_USART6_CLK_ENABLE() do { \

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595 __IO uint32_t tmpreg = 0x00U; \

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596 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

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597 /* Delay after an RCC peripheral clock enabling */ \

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598 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

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599 UNUSED(tmpreg); \

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600 } while(0U)

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601 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \

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602 __IO uint32_t tmpreg = 0x00U; \

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603 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\

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604 /* Delay after an RCC peripheral clock enabling */ \

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605 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\

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606 UNUSED(tmpreg); \

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607 } while(0U)

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608 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \

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609 __IO uint32_t tmpreg = 0x00U; \

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610 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

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611 /* Delay after an RCC peripheral clock enabling */ \

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612 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

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613 UNUSED(tmpreg); \

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614 } while(0U)

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615 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \

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616 __IO uint32_t tmpreg = 0x00U; \

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617 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\

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618 /* Delay after an RCC peripheral clock enabling */ \

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619 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\

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620 UNUSED(tmpreg); \

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621 } while(0U)

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622 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \

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623 __IO uint32_t tmpreg = 0x00U; \

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624 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\

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625 /* Delay after an RCC peripheral clock enabling */ \

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626 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\

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627 UNUSED(tmpreg); \

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628 } while(0U)

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629 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \

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630 __IO uint32_t tmpreg = 0x00U; \

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631 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\

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632 /* Delay after an RCC peripheral clock enabling */ \

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633 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\

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634 UNUSED(tmpreg); \

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635 } while(0U)

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636

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637 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

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638 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

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639 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))

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640 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

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641 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

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642 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))

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643 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))

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644 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))

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645 /**

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646 * @}

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647 */

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648

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649 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status

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650 * @brief Get the enable or disable status of the APB2 peripheral clock.

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651 * @note After reset, the peripheral clock (used for registers read/write access)

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652 * is disabled and the application software has to enable this clock before

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653 * using it.

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654 * @{

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655 */

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656 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

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657 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

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658 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)

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659 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

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660 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

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661 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)

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662 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)

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663 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)

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664

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665 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

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666 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

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667 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)

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668 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

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669 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

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670 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)

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671 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)

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672 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)

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673 /**

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674 * @}

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675 */

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676

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677 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset

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678 * @brief Force or release AHB1 peripheral reset.

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679 * @{

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680 */

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681 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)

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682 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))

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683 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))

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684 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))

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685 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))

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686 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

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687 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

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688

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689 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)

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690 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))

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691 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))

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692 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))

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693 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))

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694 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))

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695 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))

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696 /**

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697 * @}

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698 */

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699

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700 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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701 * @brief Force or release APB1 peripheral reset.

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702 * @{

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703 */

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704 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

705 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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706 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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707 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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708 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))

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709 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

710 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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711 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))

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diff changeset

712

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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713 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

714 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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715 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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716 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))

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diff changeset

717 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

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718 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

719 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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720 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

721 /**

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722 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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723 */

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diff changeset

724

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

725 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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726 * @brief Force or release APB2 peripheral reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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727 * @{

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728 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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729 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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730 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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731 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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732 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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733 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

734 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

735 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

736 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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737 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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738

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

739 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

740 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

741 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

742 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

743 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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744 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

745 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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746 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

747 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

748 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

749 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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750 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

751

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

752 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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753 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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754 * @note Peripheral clock gating in SLEEP mode can be used to further reduce

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

755 * power consumption.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

756 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

757 * @note By default, all peripheral clocks are enabled during SLEEP mode.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

758 * @{

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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759 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

760 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

761 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

762 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

763 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

764 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

765 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

766

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

767 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

768 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

769 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

770 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

771 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

772 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

773 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

774 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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775 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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776

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

777 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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778 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

779 * @note Peripheral clock gating in SLEEP mode can be used to further reduce

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

780 * power consumption.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

781 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

782 * @note By default, all peripheral clocks are enabled during SLEEP mode.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

783 * @{

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diff changeset

784 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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785 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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786 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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787 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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788 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

789 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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790 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))

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791 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

792

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diff changeset

793 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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794 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

795 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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796 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

797 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

798 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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799 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))

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800 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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801 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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802 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

803

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

804 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

805 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

806 * @note Peripheral clock gating in SLEEP mode can be used to further reduce

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

807 * power consumption.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

808 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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809 * @note By default, all peripheral clocks are enabled during SLEEP mode.

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810 * @{

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811 */

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812 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))

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813 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))

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814 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))

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815 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))

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816 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))

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817 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))

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818 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))

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819 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))

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820

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821 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))

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822 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))

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823 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))

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824 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))

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825 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))

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826 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))

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827 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))

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828 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))

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829 /**

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830 * @}

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831 */

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832

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833 /** @defgroup RCC_HSI_Configuration HSI Configuration

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834 * @{

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835 */

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836

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837 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).

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838 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.

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839 * It is used (enabled by hardware) as system clock source after startup

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840 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure

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841 * of the HSE used directly or indirectly as system clock (if the Clock

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842 * Security System CSS is enabled).

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843 * @note HSI can not be stopped if it is used as system clock source. In this case,

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844 * you have to select another source of the system clock then stop the HSI.

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845 * @note After enabling the HSI, the application software should wait on HSIRDY

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846 * flag to be set indicating that HSI clock is stable and can be used as

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847 * system clock source.

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848 * This parameter can be: ENABLE or DISABLE.

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849 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator

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850 * clock cycles.

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851 */

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852 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)

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853 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)

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854

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855 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

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856 * @note The calibration is used to compensate for the variations in voltage

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857 * and temperature that influence the frequency of the internal HSI RC.

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858 * @param __HSICalibrationValue__ specifies the calibration trimming value.

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859 * (default is RCC_HSICALIBRATION_DEFAULT).

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860 * This parameter must be a number between 0 and 0x1F.

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861 */

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862 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\

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863 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))

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864 /**

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865 * @}

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866 */

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867

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868 /** @defgroup RCC_LSI_Configuration LSI Configuration

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869 * @{

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870 */

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871

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872 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).

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873 * @note After enabling the LSI, the application software should wait on

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874 * LSIRDY flag to be set indicating that LSI clock is stable and can

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875 * be used to clock the IWDG and/or the RTC.

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876 * @note LSI can not be disabled if the IWDG is running.

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877 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator

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878 * clock cycles.

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879 */

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880 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)

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881 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)

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882 /**

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883 * @}

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884 */

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885

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886 /** @defgroup RCC_HSE_Configuration HSE Configuration

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887 * @{

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888 */

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889

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890 /**

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891 * @brief Macro to configure the External High Speed oscillator (HSE).

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892 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.

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893 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.

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894 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application

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895 * software should wait on HSERDY flag to be set indicating that HSE clock

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896 * is stable and can be used to clock the PLL and/or system clock.

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897 * @note HSE state can not be changed if it is used directly or through the

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898 * PLL as system clock. In this case, you have to select another source

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899 * of the system clock then change the HSE state (ex. disable it).

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900 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.

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901 * @note This function reset the CSSON bit, so if the clock security system(CSS)

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902 * was previously enabled you have to enable it again after calling this

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903 * function.

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904 * @param __STATE__ specifies the new state of the HSE.

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905 * This parameter can be one of the following values:

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906 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after

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907 * 6 HSE oscillator clock cycles.

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908 * @arg RCC_HSE_ON: turn ON the HSE oscillator.

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909 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

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910 */

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911 #define __HAL_RCC_HSE_CONFIG(__STATE__) \

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912 do { \

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913 if ((__STATE__) == RCC_HSE_ON) \

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914 { \

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915 SET_BIT(RCC->CR, RCC_CR_HSEON); \

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916 } \

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917 else if ((__STATE__) == RCC_HSE_BYPASS) \

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918 { \

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919 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \

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920 SET_BIT(RCC->CR, RCC_CR_HSEON); \

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921 } \

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922 else \

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923 { \

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924 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \

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925 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \

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926 } \

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927 } while(0U)

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928 /**

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929 * @}

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930 */

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931

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932 /** @defgroup RCC_LSE_Configuration LSE Configuration

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933 * @{

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934 */

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935

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936 /**

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937 * @brief Macro to configure the External Low Speed oscillator (LSE).

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938 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.

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939 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.

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940 * @note As the LSE is in the Backup domain and write access is denied to

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941 * this domain after reset, you have to enable write access using

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942 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE

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943 * (to be done once after reset).

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944 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application

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945 * software should wait on LSERDY flag to be set indicating that LSE clock

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946 * is stable and can be used to clock the RTC.

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947 * @param __STATE__ specifies the new state of the LSE.

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948 * This parameter can be one of the following values:

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949 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after

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950 * 6 LSE oscillator clock cycles.

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951 * @arg RCC_LSE_ON: turn ON the LSE oscillator.

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952 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

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953 */

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954 #define __HAL_RCC_LSE_CONFIG(__STATE__) \

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955 do { \

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956 if((__STATE__) == RCC_LSE_ON) \

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957 { \

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958 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \

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959 } \

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960 else if((__STATE__) == RCC_LSE_BYPASS) \

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961 { \

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962 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

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963 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \

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964 } \

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965 else \

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966 { \

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967 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \

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968 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

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969 } \

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970 } while(0U)

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971 /**

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972 * @}

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973 */

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974

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975 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration

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976 * @{

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977 */

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978

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979 /** @brief Macros to enable or disable the RTC clock.

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980 * @note These macros must be used only after the RTC clock source was selected.

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981 */

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982 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)

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983 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)

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984

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985 /** @brief Macros to configure the RTC clock (RTCCLK).

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986 * @note As the RTC clock configuration bits are in the Backup domain and write

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987 * access is denied to this domain after reset, you have to enable write

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988 * access using the Power Backup Access macro before to configure

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989 * the RTC clock source (to be done once after reset).

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990 * @note Once the RTC clock is configured it can't be changed unless the

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991 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by

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992 * a Power On Reset (POR).

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993 * @param __RTCCLKSource__ specifies the RTC clock source.

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994 * This parameter can be one of the following values:

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995 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.

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996 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.

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997 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.

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998 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected

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999 * as RTC clock, where x:[2,31]

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1000 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to

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1001 * work in STOP and STANDBY modes, and can be used as wake-up source.

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1002 * However, when the HSE clock is used as RTC clock source, the RTC

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1003 * cannot be used in STOP and STANDBY modes.

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1004 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as

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1005 * RTC clock source).

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1006 */

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1007 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \

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1008 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

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1009

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1010 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \

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1011 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \

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1012 } while(0U)

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1013

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1014 /** @brief Macro to get the RTC clock source.

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1015 * @retval The clock source can be one of the following values:

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1016 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock

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1017 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock

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1018 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock

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1019 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()

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1020 */

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1021 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))

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1022

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1023 /**

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1024 * @brief Get the RTC and HSE clock divider (RTCPRE).

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1025 * @retval Returned value can be one of the following values:

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1026 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected

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1027 * as RTC clock, where x:[2,31]

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1028 */

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1029 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)

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1030

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1031 /** @brief Macros to force or release the Backup domain reset.

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1032 * @note This function resets the RTC peripheral (including the backup registers)

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1033 * and the RTC clock source selection in RCC_CSR register.

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1034 * @note The BKPSRAM is not affected by this reset.

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1035 */

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1036 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)

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1037 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)

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1038 /**

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1039 * @}

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1040 */

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1041

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1042 /** @defgroup RCC_PLL_Configuration PLL Configuration

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1043 * @{

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1044 */

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1045

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1046 /** @brief Macros to enable or disable the main PLL.

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1047 * @note After enabling the main PLL, the application software should wait on

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1048 * PLLRDY flag to be set indicating that PLL clock is stable and can

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1049 * be used as system clock source.

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1050 * @note The main PLL can not be disabled if it is used as system clock source

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1051 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.

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1052 */

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1053 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

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1054 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

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1055

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1056 /** @brief Macro to configure the PLL clock source.

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1057 * @note This function must be used only when the main PLL is disabled.

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1058 * @param __PLLSOURCE__ specifies the PLL entry clock source.

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1059 * This parameter can be one of the following values:

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1060 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

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1061 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

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1062 *

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1063 */

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1064 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))

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1065

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1066 /** @brief Macro to configure the PLL multiplication factor.

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1067 * @note This function must be used only when the main PLL is disabled.

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1068 * @param __PLLM__ specifies the division factor for PLL VCO input clock

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1069 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.

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1070 * @note You have to set the PLLM parameter correctly to ensure that the VCO input

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1071 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency

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1072 * of 2 MHz to limit PLL jitter.

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1073 *

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1074 */

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1075 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))

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1076 /**

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1077 * @}

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1078 */

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1079

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1080 /** @defgroup RCC_Get_Clock_source Get Clock source

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1081 * @{

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1082 */

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1083 /**

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1084 * @brief Macro to configure the system clock source.

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1085 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.

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1086 * This parameter can be one of the following values:

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1087 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.

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1088 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.

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1089 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

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1090 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This

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1091 * parameter is available only for STM32F446xx devices.

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1092 */

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1093 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

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1094

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1095 /** @brief Macro to get the clock source used as system clock.

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1096 * @retval The clock source used as system clock. The returned value can be one

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1097 * of the following:

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1098 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.

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1099 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.

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1100 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.

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1101 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter

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1102 * is available only for STM32F446xx devices.

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1103 */

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1104 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)

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1105

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1106 /** @brief Macro to get the oscillator used as PLL clock source.

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1107 * @retval The oscillator used as PLL clock source. The returned value can be one

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1108 * of the following:

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1109 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.

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1110 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

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1111 */

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1112 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))

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1113 /**

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1114 * @}

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1115 */

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1116

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1117 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config

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1118 * @{

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1119 */

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1120

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1121 /** @brief Macro to configure the MCO1 clock.

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1122 * @param __MCOCLKSOURCE__ specifies the MCO clock source.

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1123 * This parameter can be one of the following values:

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1124 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source

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1125 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source

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1126 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source

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1127 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source

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1128 * @param __MCODIV__ specifies the MCO clock prescaler.

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1129 * This parameter can be one of the following values:

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1130 * @arg RCC_MCODIV_1: no division applied to MCOx clock

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1131 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock

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1132 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock

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1133 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock

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1134 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock

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1135 */

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1136 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

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1137 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

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1138

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1139 /** @brief Macro to configure the MCO2 clock.

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1140 * @param __MCOCLKSOURCE__ specifies the MCO clock source.

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1141 * This parameter can be one of the following values:

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1142 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source

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1143 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx

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1144 * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices

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1145 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source

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1146 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source

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1147 * @param __MCODIV__ specifies the MCO clock prescaler.

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1148 * This parameter can be one of the following values:

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1149 * @arg RCC_MCODIV_1: no division applied to MCOx clock

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1150 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock

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1151 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock

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1152 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock

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1153 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock

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1154 * @note For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have

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1155 * at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).

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1156 */

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1157 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

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1158 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));

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1159 /**

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1160 * @}

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1161 */

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1162

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1163 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management

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1164 * @brief macros to manage the specified RCC Flags and interrupts.

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1165 * @{

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1166 */

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1167

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1168 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable

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1169 * the selected interrupts).

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1170 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.

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1171 * This parameter can be any combination of the following values:

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1172 * @arg RCC_IT_LSIRDY: LSI ready interrupt.

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1173 * @arg RCC_IT_LSERDY: LSE ready interrupt.

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1174 * @arg RCC_IT_HSIRDY: HSI ready interrupt.

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1175 * @arg RCC_IT_HSERDY: HSE ready interrupt.

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1176 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.

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1177 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

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1178 */

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1179 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

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1180

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1181 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable

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1182 * the selected interrupts).

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1183 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.

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1184 * This parameter can be any combination of the following values:

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1185 * @arg RCC_IT_LSIRDY: LSI ready interrupt.

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1186 * @arg RCC_IT_LSERDY: LSE ready interrupt.

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1187 * @arg RCC_IT_HSIRDY: HSI ready interrupt.

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1188 * @arg RCC_IT_HSERDY: HSE ready interrupt.

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1189 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.

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1190 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

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1191 */

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1192 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))

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1193

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1194 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]

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1195 * bits to clear the selected interrupt pending bits.

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1196 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.

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1197 * This parameter can be any combination of the following values:

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1198 * @arg RCC_IT_LSIRDY: LSI ready interrupt.

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1199 * @arg RCC_IT_LSERDY: LSE ready interrupt.

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1200 * @arg RCC_IT_HSIRDY: HSI ready interrupt.

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1201 * @arg RCC_IT_HSERDY: HSE ready interrupt.

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1202 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.

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1203 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

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1204 * @arg RCC_IT_CSS: Clock Security System interrupt

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1205 */

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1206 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

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1207

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1208 /** @brief Check the RCC's interrupt has occurred or not.

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1209 * @param __INTERRUPT__ specifies the RCC interrupt source to check.

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1210 * This parameter can be one of the following values:

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1211 * @arg RCC_IT_LSIRDY: LSI ready interrupt.

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1212 * @arg RCC_IT_LSERDY: LSE ready interrupt.

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1213 * @arg RCC_IT_HSIRDY: HSI ready interrupt.

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1214 * @arg RCC_IT_HSERDY: HSE ready interrupt.

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1215 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.

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1216 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.

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1217 * @arg RCC_IT_CSS: Clock Security System interrupt

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1218 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

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1219 */

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1220 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))

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1221

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1222 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1223 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.

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1224 */

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1225 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)

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diff changeset

1226

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1227 /** @brief Check RCC flag is set or not.

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1228 * @param __FLAG__ specifies the flag to check.

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1229 * This parameter can be one of the following values:

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1230 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1231 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1232 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1233 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.

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diff changeset

1234 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1235 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1236 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1237 * @arg RCC_FLAG_PINRST: Pin reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1238 * @arg RCC_FLAG_PORRST: POR/PDR reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1239 * @arg RCC_FLAG_SFTRST: Software reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1240 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1241 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1242 * @arg RCC_FLAG_LPWRRST: Low Power reset.

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1243 * @retval The new state of __FLAG__ (TRUE or FALSE).

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1244 */

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1245 #define RCC_FLAG_MASK ((uint8_t)0x1FU)

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1246 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

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diff changeset

1247

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1248 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1249 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1250 */

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diff changeset

1251

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1252 /**

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1253 * @}

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1254 */

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1255

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1256 /* Exported functions --------------------------------------------------------*/

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1257 /** @addtogroup RCC_Exported_Functions

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1258 * @{

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1259 */

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1260

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1261 /** @addtogroup RCC_Exported_Functions_Group1

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1262 * @{

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1263 */

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1264 /* Initialization and de-initialization functions ******************************/

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1265 HAL_StatusTypeDef HAL_RCC_DeInit(void);

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1266 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1267 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

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1268 /**

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1269 * @}

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1270 */

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1271

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1272 /** @addtogroup RCC_Exported_Functions_Group2

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1273 * @{

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1274 */

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1275 /* Peripheral Control functions ************************************************/

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1276 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);

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1277 void HAL_RCC_EnableCSS(void);

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1278 void HAL_RCC_DisableCSS(void);

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1279 uint32_t HAL_RCC_GetSysClockFreq(void);

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1280 uint32_t HAL_RCC_GetHCLKFreq(void);

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1281 uint32_t HAL_RCC_GetPCLK1Freq(void);

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1282 uint32_t HAL_RCC_GetPCLK2Freq(void);

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1283 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

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1284 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);

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1285

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1286 /* CSS NMI IRQ handler */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1287 void HAL_RCC_NMI_IRQHandler(void);

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1288

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1289 /* User Callbacks in non blocking mode (IT mode) */

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1290 void HAL_RCC_CSSCallback(void);

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1291

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1292 /**

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1293 * @}

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1294 */

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1295

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1296 /**

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1297 * @}

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1298 */

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1299

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1300 /* Private types -------------------------------------------------------------*/

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1301 /* Private variables ---------------------------------------------------------*/

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1302 /* Private constants ---------------------------------------------------------*/

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1303 /** @defgroup RCC_Private_Constants RCC Private Constants

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1304 * @{

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1305 */

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1306

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1307 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion

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1308 * @brief RCC registers bit address in the alias region

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1309 * @{

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1310 */

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1311 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)

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1312 /* --- CR Register --- */

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1313 /* Alias word address of HSION bit */

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1314 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)

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1315 #define RCC_HSION_BIT_NUMBER 0x00U

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1316 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))

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1317 /* Alias word address of CSSON bit */

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1318 #define RCC_CSSON_BIT_NUMBER 0x13U

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1319 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))

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1320 /* Alias word address of PLLON bit */

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1321 #define RCC_PLLON_BIT_NUMBER 0x18U

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1322 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))

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1323

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1324 /* --- BDCR Register --- */

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1325 /* Alias word address of RTCEN bit */

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1326 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)

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1327 #define RCC_RTCEN_BIT_NUMBER 0x0FU

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1328 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))

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1329 /* Alias word address of BDRST bit */

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1330 #define RCC_BDRST_BIT_NUMBER 0x10U

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1331 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))

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1332

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1333 /* --- CSR Register --- */

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1334 /* Alias word address of LSION bit */

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1335 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)

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1336 #define RCC_LSION_BIT_NUMBER 0x00U

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1337 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))

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1338

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1339 /* CR register byte 3 (Bits[23:16]) base address */

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1340 #define RCC_CR_BYTE2_ADDRESS 0x40023802U

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1341

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1342 /* CIR register byte 2 (Bits[15:8]) base address */

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1343 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))

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1344

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1345 /* CIR register byte 3 (Bits[23:16]) base address */

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1346 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))

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1347

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1348 /* BDCR register base address */

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1349 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)

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1350

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1351 #define RCC_DBP_TIMEOUT_VALUE 2U

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1352 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

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1353

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1354 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

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1355 #define HSI_TIMEOUT_VALUE 2U /* 2 ms */

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1356 #define LSI_TIMEOUT_VALUE 2U /* 2 ms */

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1357 #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */

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1358

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1359 /**

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1360 * @}

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1361 */

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1362

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1363 /**

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1364 * @}

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1365 */

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1366

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1367 /* Private macros ------------------------------------------------------------*/

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1368 /** @defgroup RCC_Private_Macros RCC Private Macros

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1369 * @{

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1370 */

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1371

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1372 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1373 * @{

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1374 */

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1375 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1376

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1377 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1378 ((HSE) == RCC_HSE_BYPASS))

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1379

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1380 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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diff changeset

1381 ((LSE) == RCC_LSE_BYPASS))

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1382

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1383 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))

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1384

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1385 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

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1386

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1387 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))

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1388

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1389 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \

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1390 ((SOURCE) == RCC_PLLSOURCE_HSE))

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1391

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1392 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \

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1393 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \

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1394 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \

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1395 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1396

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1397 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \

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1398 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \

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1399 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1400 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1401 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \

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1402 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \

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1403 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \

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1404 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1405 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1406 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1407 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1408 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \

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1409 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1410 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1411 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1412 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \

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1413 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1414 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1415 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1416 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1417 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1418 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \

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1419 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1420 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1421 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1422 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1423 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1424 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1425 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1426 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1427 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1428 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))

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1429

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1430 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1431

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1432 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1433

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1434 #define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1435

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1436 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \

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1437 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \

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1438 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \

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1439 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1440 ((HCLK) == RCC_SYSCLK_DIV512))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1441

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1442 #define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1443

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1444 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \

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1445 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \

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1446 ((PCLK) == RCC_HCLK_DIV16))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1447

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1448 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

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1449

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1450 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1451 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1452

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1453 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \

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1454 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \

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1455 ((DIV) == RCC_MCODIV_5))

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1456 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1457

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1458 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1459 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1460 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1461

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1462 /**

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1463 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1464 */

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1465

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1466 /**

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1467 * @}

c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure

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1468 */

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1469

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1470 /**

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1471 * @}

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1472 */

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1473

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1474 #ifdef __cplusplus

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1475 }

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1476 #endif

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1477

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1478 #endif /* __STM32F4xx_HAL_RCC_H */

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1479

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1480 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

Mercurial > public > ostc4

annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h @ 974:53900dfe335b Evo_2_23