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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c @ 728:5143e927219f

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Added sensor map to Firmware <=> RTE inferface: The sensor map contains a list of up to five sensors which may be connected to the external interface. The update includes the definition of the type as well as the data structure. to ensure compatibility the RTE and needed RTE version has been set to 3.0
author Ideenmodellierer
date Sat, 14 Jan 2023 20:41:36 +0100
parents c78bcbd5deda
children
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_pwr_ex.c
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4 * @author MCD Application Team
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5 * @brief Extended PWR HAL module driver.
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6 * This file provides firmware functions to manage the following
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7 * functionalities of PWR extension peripheral:
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8 * + Peripheral Extended features functions
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9 *
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10 ******************************************************************************
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11 * @attention
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12 *
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13 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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14 *
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15 * Redistribution and use in source and binary forms, with or without modification,
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16 * are permitted provided that the following conditions are met:
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17 * 1. Redistributions of source code must retain the above copyright notice,
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18 * this list of conditions and the following disclaimer.
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19 * 2. Redistributions in binary form must reproduce the above copyright notice,
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20 * this list of conditions and the following disclaimer in the documentation
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21 * and/or other materials provided with the distribution.
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22 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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23 * may be used to endorse or promote products derived from this software
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24 * without specific prior written permission.
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25 *
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26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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36 *
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37 ******************************************************************************
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38 */
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39
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40 /* Includes ------------------------------------------------------------------*/
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41 #include "stm32f4xx_hal.h"
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42
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43 /** @addtogroup STM32F4xx_HAL_Driver
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44 * @{
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45 */
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46
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47 /** @defgroup PWREx PWREx
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48 * @brief PWR HAL module driver
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49 * @{
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50 */
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51
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52 #ifdef HAL_PWR_MODULE_ENABLED
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53
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54 /* Private typedef -----------------------------------------------------------*/
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55 /* Private define ------------------------------------------------------------*/
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56 /** @addtogroup PWREx_Private_Constants
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57 * @{
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58 */
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59 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U
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60 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U
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61 #define PWR_BKPREG_TIMEOUT_VALUE 1000U
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62 #define PWR_VOSRDY_TIMEOUT_VALUE 1000U
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63 /**
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64 * @}
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65 */
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66
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67
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68 /* Private macro -------------------------------------------------------------*/
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69 /* Private variables ---------------------------------------------------------*/
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70 /* Private function prototypes -----------------------------------------------*/
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71 /* Private functions ---------------------------------------------------------*/
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72 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
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73 * @{
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74 */
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75
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76 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
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77 * @brief Peripheral Extended features functions
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78 *
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79 @verbatim
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80
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81 ===============================================================================
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82 ##### Peripheral extended features functions #####
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83 ===============================================================================
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84
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85 *** Main and Backup Regulators configuration ***
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86 ================================================
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87 [..]
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88 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
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89 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
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90 retained even in Standby or VBAT mode when the low power backup regulator
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91 is enabled. It can be considered as an internal EEPROM when VBAT is
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92 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
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93 enable the low power backup regulator.
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94
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95 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
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96 the backup SRAM is powered from VDD which replaces the VBAT power supply to
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97 save battery life.
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98
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99 (+) The backup SRAM is not mass erased by a tamper event. It is read
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100 protected to prevent confidential data, such as cryptographic private
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101 key, from being accessed. The backup SRAM can be erased only through
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102 the Flash interface when a protection level change from level 1 to
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103 level 0 is requested.
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104 -@- Refer to the description of Read protection (RDP) in the Flash
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105 programming manual.
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106
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107 (+) The main internal regulator can be configured to have a tradeoff between
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108 performance and power consumption when the device does not operate at
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109 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
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110 macro which configure VOS bit in PWR_CR register
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111
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112 Refer to the product datasheets for more details.
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113
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114 *** FLASH Power Down configuration ****
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115 =======================================
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116 [..]
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117 (+) By setting the FPDS bit in the PWR_CR register by using the
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118 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
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119 down mode when the device enters Stop mode. When the Flash memory
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120 is in power down mode, an additional startup delay is incurred when
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121 waking up from Stop mode.
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122
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123 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL
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124 is OFF and the HSI or HSE clock source is selected as system clock.
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125 The new value programmed is active only when the PLL is ON.
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126 When the PLL is OFF, the voltage scale 3 is automatically selected.
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127 Refer to the datasheets for more details.
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128
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129 *** Over-Drive and Under-Drive configuration ****
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130 =================================================
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131 [..]
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132 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
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133 2 operating modes available:
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134 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
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135 voltage scaling (scale 1, scale 2 or scale 3)
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136 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
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137 higher frequency than the normal mode for a given voltage scaling (scale 1,
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138 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
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139 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
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140 the sequence described in Reference manual.
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141
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142 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator
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143 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
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144 and internal SRAM. 2 operating modes are available:
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145 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
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146 available when the main regulator or the low power regulator is used in Scale 3 or
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147 low voltage mode.
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148 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
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149 available when the main regulator or the low power regulator is in low voltage mode.
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150
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151 @endverbatim
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152 * @{
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153 */
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154
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155 /**
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156 * @brief Enables the Backup Regulator.
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157 * @retval HAL status
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158 */
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159 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
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160 {
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161 uint32_t tickstart = 0U;
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162
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163 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
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164
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165 /* Get tick */
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166 tickstart = HAL_GetTick();
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167
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168 /* Wait till Backup regulator ready flag is set */
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169 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
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170 {
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171 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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172 {
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173 return HAL_TIMEOUT;
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174 }
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175 }
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176 return HAL_OK;
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177 }
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178
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179 /**
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180 * @brief Disables the Backup Regulator.
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181 * @retval HAL status
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182 */
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183 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
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184 {
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185 uint32_t tickstart = 0U;
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186
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187 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
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188
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189 /* Get tick */
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190 tickstart = HAL_GetTick();
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191
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192 /* Wait till Backup regulator ready flag is set */
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193 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
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194 {
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195 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
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196 {
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197 return HAL_TIMEOUT;
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198 }
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199 }
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200 return HAL_OK;
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201 }
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202
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203 /**
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204 * @brief Enables the Flash Power Down in Stop mode.
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205 * @retval None
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206 */
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207 void HAL_PWREx_EnableFlashPowerDown(void)
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208 {
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209 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
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210 }
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211
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212 /**
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213 * @brief Disables the Flash Power Down in Stop mode.
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214 * @retval None
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215 */
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216 void HAL_PWREx_DisableFlashPowerDown(void)
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217 {
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218 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
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219 }
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220
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221 /**
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222 * @brief Return Voltage Scaling Range.
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223 * @retval The configured scale for the regulator voltage(VOS bit field).
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224 * The returned value can be one of the following:
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225 * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
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226 * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
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227 * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
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228 */
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229 uint32_t HAL_PWREx_GetVoltageRange(void)
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230 {
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231 return (PWR->CR & PWR_CR_VOS);
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232 }
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233
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234 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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235 /**
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236 * @brief Configures the main internal regulator output voltage.
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237 * @param VoltageScaling specifies the regulator output voltage to achieve
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238 * a tradeoff between performance and power consumption.
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239 * This parameter can be one of the following values:
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240 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
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241 * the maximum value of fHCLK = 168 MHz.
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242 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
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243 * the maximum value of fHCLK = 144 MHz.
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244 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
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245 * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
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246 * When moving from Range 2 to Range 1, the system frequency can be increased to
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247 * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
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248 * @retval HAL Status
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249 */
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250 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
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251 {
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252 uint32_t tickstart = 0U;
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253
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254 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
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255
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256 /* Enable PWR RCC Clock Peripheral */
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257 __HAL_RCC_PWR_CLK_ENABLE();
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258
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259 /* Set Range */
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260 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
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261
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262 /* Get Start Tick*/
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263 tickstart = HAL_GetTick();
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264 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
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265 {
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266 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
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267 {
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268 return HAL_TIMEOUT;
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269 }
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270 }
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271
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272 return HAL_OK;
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273 }
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274
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275 #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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276 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
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277 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
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278 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
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279 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
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280 /**
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281 * @brief Configures the main internal regulator output voltage.
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282 * @param VoltageScaling specifies the regulator output voltage to achieve
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283 * a tradeoff between performance and power consumption.
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284 * This parameter can be one of the following values:
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285 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
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286 * the maximum value of fHCLK is 168 MHz. It can be extended to
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287 * 180 MHz by activating the over-drive mode.
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288 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
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289 * the maximum value of fHCLK is 144 MHz. It can be extended to,
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290 * 168 MHz by activating the over-drive mode.
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291 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
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292 * the maximum value of fHCLK is 120 MHz.
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293 * @note To update the system clock frequency(SYSCLK):
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294 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
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295 * - Call the HAL_RCC_OscConfig() to configure the PLL.
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296 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
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297 * - Set the new system clock frequency using the HAL_RCC_ClockConfig().
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298 * @note The scale can be modified only when the HSI or HSE clock source is selected
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299 * as system clock source, otherwise the API returns HAL_ERROR.
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300 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
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301 * value in the PWR_CR1 register are not taken in account.
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302 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
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303 * @note The new voltage scale is active only when the PLL is ON.
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304 * @retval HAL Status
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305 */
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306 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
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307 {
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308 uint32_t tickstart = 0U;
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309
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310 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
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311
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312 /* Enable PWR RCC Clock Peripheral */
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313 __HAL_RCC_PWR_CLK_ENABLE();
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314
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315 /* Check if the PLL is used as system clock or not */
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316 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
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317 {
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318 /* Disable the main PLL */
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319 __HAL_RCC_PLL_DISABLE();
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320
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321 /* Get Start Tick */
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322 tickstart = HAL_GetTick();
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323 /* Wait till PLL is disabled */
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324 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
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325 {
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326 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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327 {
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328 return HAL_TIMEOUT;
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329 }
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330 }
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331
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332 /* Set Range */
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333 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
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334
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335 /* Enable the main PLL */
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336 __HAL_RCC_PLL_ENABLE();
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337
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338 /* Get Start Tick */
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339 tickstart = HAL_GetTick();
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340 /* Wait till PLL is ready */
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341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
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342 {
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343 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
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344 {
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345 return HAL_TIMEOUT;
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346 }
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347 }
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348
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349 /* Get Start Tick */
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350 tickstart = HAL_GetTick();
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351 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
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352 {
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353 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
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354 {
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355 return HAL_TIMEOUT;
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356 }
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357 }
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358 }
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359 else
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360 {
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361 return HAL_ERROR;
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362 }
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363
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364 return HAL_OK;
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365 }
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366 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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367
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368 #if defined(STM32F469xx) || defined(STM32F479xx)
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369 /**
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370 * @brief Enables Wakeup Pin Detection on high level (rising edge).
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371 * @retval None
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372 */
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373 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void)
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374 {
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375 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE;
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376 }
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377
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378 /**
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379 * @brief Enables Wakeup Pin Detection on low level (falling edge).
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380 * @retval None
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381 */
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382 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void)
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383 {
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384 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE;
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385 }
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386 #endif /* STM32F469xx || STM32F479xx */
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387
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388 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
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389 defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
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390 defined(STM32F413xx) || defined(STM32F423xx)
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391 /**
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392 * @brief Enables Main Regulator low voltage mode.
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393 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
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394 * STM32F413xx/STM32F423xx devices.
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395 * @retval None
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396 */
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397 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
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398 {
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399 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
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400 }
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401
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402 /**
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403 * @brief Disables Main Regulator low voltage mode.
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404 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
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405 * STM32F413xx/STM32F423xxdevices.
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406 * @retval None
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407 */
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408 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
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409 {
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410 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
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411 }
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412
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413 /**
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414 * @brief Enables Low Power Regulator low voltage mode.
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415 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
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416 * STM32F413xx/STM32F423xx devices.
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417 * @retval None
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418 */
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419 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
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420 {
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421 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
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422 }
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423
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424 /**
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425 * @brief Disables Low Power Regulator low voltage mode.
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426 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
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427 * STM32F413xx/STM32F423xx devices.
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428 * @retval None
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429 */
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430 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
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431 {
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432 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
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433 }
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434
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435 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
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436 STM32F413xx || STM32F423xx */
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437
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438 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
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439 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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440 /**
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441 * @brief Activates the Over-Drive mode.
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442 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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443 * This mode allows the CPU and the core logic to operate at a higher frequency
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444 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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445 * @note It is recommended to enter or exit Over-drive mode when the application is not running
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446 * critical tasks and when the system clock source is either HSI or HSE.
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447 * During the Over-drive switch activation, no peripheral clocks should be enabled.
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448 * The peripheral clocks must be enabled once the Over-drive mode is activated.
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449 * @retval HAL status
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450 */
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451 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
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452 {
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453 uint32_t tickstart = 0U;
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454
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455 __HAL_RCC_PWR_CLK_ENABLE();
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456
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457 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
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458 __HAL_PWR_OVERDRIVE_ENABLE();
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459
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parents:
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460 /* Get tick */
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461 tickstart = HAL_GetTick();
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462
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463 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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464 {
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465 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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466 {
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467 return HAL_TIMEOUT;
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468 }
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469 }
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470
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471 /* Enable the Over-drive switch */
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472 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
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473
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474 /* Get tick */
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475 tickstart = HAL_GetTick();
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476
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477 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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478 {
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479 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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480 {
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481 return HAL_TIMEOUT;
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482 }
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483 }
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484 return HAL_OK;
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485 }
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486
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487 /**
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488 * @brief Deactivates the Over-Drive mode.
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489 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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490 * This mode allows the CPU and the core logic to operate at a higher frequency
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491 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
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492 * @note It is recommended to enter or exit Over-drive mode when the application is not running
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493 * critical tasks and when the system clock source is either HSI or HSE.
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494 * During the Over-drive switch activation, no peripheral clocks should be enabled.
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495 * The peripheral clocks must be enabled once the Over-drive mode is activated.
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496 * @retval HAL status
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497 */
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498 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
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499 {
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500 uint32_t tickstart = 0U;
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501
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502 __HAL_RCC_PWR_CLK_ENABLE();
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503
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504 /* Disable the Over-drive switch */
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505 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
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506
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507 /* Get tick */
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508 tickstart = HAL_GetTick();
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509
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510 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
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511 {
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512 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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513 {
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514 return HAL_TIMEOUT;
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515 }
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516 }
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517
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518 /* Disable the Over-drive */
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519 __HAL_PWR_OVERDRIVE_DISABLE();
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520
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521 /* Get tick */
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522 tickstart = HAL_GetTick();
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523
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524 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
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525 {
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526 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
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527 {
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528 return HAL_TIMEOUT;
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529 }
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530 }
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531
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532 return HAL_OK;
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533 }
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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534
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535 /**
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536 * @brief Enters in Under-Drive STOP mode.
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537 *
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538 * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
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539 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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540 * @note This mode can be selected only when the Under-Drive is already active
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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541 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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542 * @note This mode is enabled only with STOP low power mode.
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543 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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544 * mode is only available when the main regulator or the low power regulator
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545 * is in low voltage mode
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546 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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547 * @note If the Under-drive mode was enabled, it is automatically disabled after
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548 * exiting Stop mode.
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549 * When the voltage regulator operates in Under-drive mode, an additional
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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550 * startup delay is induced when waking up from Stop mode.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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551 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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552 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
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553 *
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554 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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555 * the HSI RC oscillator is selected as system clock.
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556 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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557 * @note When the voltage regulator operates in low power mode, an additional
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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558 * startup delay is incurred when waking up from Stop mode.
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559 * By keeping the internal regulator ON during Stop mode, the consumption
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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560 * is higher although the startup time is reduced.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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561 *
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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562 * @param Regulator specifies the regulator state in STOP mode.
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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563 * This parameter can be one of the following values:
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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564 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
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565 * and Flash memory in power-down when the device is in Stop under-drive mode
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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566 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
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567 * and Flash memory in power-down when the device is in Stop under-drive mode
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568 * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
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569 * This parameter can be one of the following values:
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570 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
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571 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
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572 * @retval None
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573 */
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574 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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575 {
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576 uint32_t tmpreg1 = 0U;
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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577
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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578 /* Check the parameters */
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579 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
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580 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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581
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582 /* Enable Power ctrl clock */
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583 __HAL_RCC_PWR_CLK_ENABLE();
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584 /* Enable the Under-drive Mode ---------------------------------------------*/
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585 /* Clear Under-drive flag */
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586 __HAL_PWR_CLEAR_ODRUDR_FLAG();
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587
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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parents:
diff changeset
588 /* Enable the Under-drive */
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589 __HAL_PWR_UNDERDRIVE_ENABLE();
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590
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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591 /* Select the regulator state in STOP mode ---------------------------------*/
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592 tmpreg1 = PWR->CR;
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593 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
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594 tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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595
c78bcbd5deda Added current STM32 standandard libraries in version independend folder structure
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596 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
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597 tmpreg1 |= Regulator;
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598
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599 /* Store the new value */
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600 PWR->CR = tmpreg1;
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601
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602 /* Set SLEEPDEEP bit of Cortex System Control Register */
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603 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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604
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605 /* Select STOP mode entry --------------------------------------------------*/
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606 if(STOPEntry == PWR_SLEEPENTRY_WFI)
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607 {
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608 /* Request Wait For Interrupt */
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609 __WFI();
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610 }
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611 else
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612 {
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613 /* Request Wait For Event */
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614 __WFE();
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615 }
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616 /* Reset SLEEPDEEP bit of Cortex System Control Register */
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617 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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618
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619 return HAL_OK;
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620 }
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621
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622 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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623 /**
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624 * @}
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625 */
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626
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627 /**
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628 * @}
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629 */
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630
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631 #endif /* HAL_PWR_MODULE_ENABLED */
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632 /**
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633 * @}
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634 */
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635
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636 /**
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637 * @}
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638 */
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639
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640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/