annotate OtherSources/system_stm32f4xx.c @ 740:5078da3845c0

Added button lock after wakeup in surface mode: During setup of diveequipment the OSTC4 is sometimes operated unintended (e.g. while equipping the jaket). To avoid this it is now possible to activate a button lock in the button lock sensitivity menu. The OSTC4 will then wakeup as usuall but if the diver wants to oerate the menus he has to press the buttons in a certain order. The button to be pressed is indicated by a blue bar. The button lock is deactivated in dive mode.
author Ideenmodellierer
date Thu, 02 Feb 2023 17:35:38 +0100
parents 2de06b1abed3
children 4e10a3e087a1
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1 /**
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2 ******************************************************************************
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3 * @file system_stm32f4xx.c
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4 * @author MCD Application Team
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5 * @version V2.1.0
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6 * @date 19-June-2014
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7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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8 *
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9 * This file provides two functions and one global variable to be called from
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10 * user application:
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11 * - SystemInit(): This function is called at startup just after reset and
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12 * before branch to main program. This call is made inside
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13 * the "startup_stm32f4xx.s" file.
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14 *
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15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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16 * by the user application to setup the SysTick
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17 * timer or configure other parameters.
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18 *
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19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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20 * be called whenever the core clock is changed
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21 * during program execution.
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22 *
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23 *
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24 ******************************************************************************
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25 * @attention
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26 *
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27 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
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28 *
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29 * Redistribution and use in source and binary forms, with or without modification,
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30 * are permitted provided that the following conditions are met:
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31 * 1. Redistributions of source code must retain the above copyright notice,
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32 * this list of conditions and the following disclaimer.
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33 * 2. Redistributions in binary form must reproduce the above copyright notice,
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34 * this list of conditions and the following disclaimer in the documentation
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35 * and/or other materials provided with the distribution.
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36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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37 * may be used to endorse or promote products derived from this software
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38 * without specific prior written permission.
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39 *
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40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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50 *
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51 ******************************************************************************
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52 */
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53
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54 /** @addtogroup CMSIS
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55 * @{
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56 */
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57
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58 /** @addtogroup stm32f4xx_system
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59 * @{
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60 */
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61
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62 /** @addtogroup STM32F4xx_System_Private_Includes
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63 * @{
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64 */
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65
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66
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67 #include "stm32f4xx.h"
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68
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69 #if !defined (HSE_VALUE)
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70 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
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71 #endif /* HSE_VALUE */
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72
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73 #if !defined (HSI_VALUE)
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74 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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75 #endif /* HSI_VALUE */
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76
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77 /**
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78 * @}
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79 */
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80
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81 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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82 * @{
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83 */
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84
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85 /**
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86 * @}
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87 */
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88
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89 /** @addtogroup STM32F4xx_System_Private_Defines
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90 * @{
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91 */
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92
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93 /************************* Miscellaneous Configuration ************************/
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94 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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95 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
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96 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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97 /* #define DATA_IN_ExtSRAM */
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98 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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99
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100 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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101 /* #define DATA_IN_ExtSDRAM */
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102 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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103
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104 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
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105 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
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106 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
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107
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108 /*!< Uncomment the following line if you need to relocate your vector Table in
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109 Internal SRAM. */
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110 /* #define VECT_TAB_SRAM */
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111 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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112 This value must be a multiple of 0x200. */
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113 /******************************************************************************/
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114
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115 /**
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116 * @}
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117 */
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118
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119 /** @addtogroup STM32F4xx_System_Private_Macros
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120 * @{
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121 */
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122
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123 /**
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124 * @}
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125 */
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126
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127 /** @addtogroup STM32F4xx_System_Private_Variables
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128 * @{
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129 */
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130 /* This variable is updated in three ways:
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131 1) by calling CMSIS function SystemCoreClockUpdate()
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132 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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133 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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134 Note: If you use this function to configure the system clock; then there
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135 is no need to call the 2 first functions listed above, since SystemCoreClock
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136 variable is updated automatically.
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137 */
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138 uint32_t SystemCoreClock = 16000000;
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139 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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140
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141 /**
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142 * @}
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143 */
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144
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145 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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146 * @{
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147 */
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148
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149 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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150 static void SystemInit_ExtMemCtl(void);
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151 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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152
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153 /**
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154 * @}
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155 */
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156
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157 /** @addtogroup STM32F4xx_System_Private_Functions
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158 * @{
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159 */
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160
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161 /**
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162 * @brief Setup the microcontroller system
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163 * Initialize the FPU setting, vector table location and External memory
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164 * configuration.
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165 * @param None
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166 * @retval None
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167 */
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168 void SystemInit(void)
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169 {
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170 /* FPU settings ------------------------------------------------------------*/
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171 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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172 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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173 #endif
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174 /* Reset the RCC clock configuration to the default reset state ------------*/
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175 /* Set HSION bit */
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176 RCC->CR |= (uint32_t)0x00000001;
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177
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178 /* Reset CFGR register */
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179 RCC->CFGR = 0x00000000;
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180
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181 /* Reset HSEON, CSSON and PLLON bits */
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182 RCC->CR &= (uint32_t)0xFEF6FFFF;
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183
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184 /* Reset PLLCFGR register */
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185 RCC->PLLCFGR = 0x24003010;
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186
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187 /* Reset HSEBYP bit */
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188 RCC->CR &= (uint32_t)0xFFFBFFFF;
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189
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190 /* Disable all interrupts */
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191 RCC->CIR = 0x00000000;
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192
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193 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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194 SystemInit_ExtMemCtl();
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195 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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196
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197 /* Configure the Vector Table location add offset address ------------------*/
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198 #ifdef VECT_TAB_SRAM
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199 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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200 #else
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201 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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202 #endif
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203 }
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204
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205 /**
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206 * @brief Update SystemCoreClock variable according to Clock Register Values.
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207 * The SystemCoreClock variable contains the core clock (HCLK), it can
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208 * be used by the user application to setup the SysTick timer or configure
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209 * other parameters.
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210 *
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211 * @note Each time the core clock (HCLK) changes, this function must be called
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212 * to update SystemCoreClock variable value. Otherwise, any configuration
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213 * based on this variable will be incorrect.
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214 *
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215 * @note - The system frequency computed by this function is not the real
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216 * frequency in the chip. It is calculated based on the predefined
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217 * constant and the selected clock source:
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218 *
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219 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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220 *
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221 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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222 *
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223 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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224 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
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225 *
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226 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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227 * 16 MHz) but the real value may vary depending on the variations
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228 * in voltage and temperature.
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229 *
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230 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
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231 * depends on the application requirements), user has to ensure that HSE_VALUE
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232 * is same as the real frequency of the crystal used. Otherwise, this function
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233 * may have wrong result.
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234 *
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235 * - The result of this function could be not correct when using fractional
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236 * value for HSE crystal.
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237 *
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238 * @param None
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239 * @retval None
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240 */
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241 void SystemCoreClockUpdate(void)
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242 {
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243 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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244
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245 /* Get SYSCLK source -------------------------------------------------------*/
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246 tmp = RCC->CFGR & RCC_CFGR_SWS;
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247
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248 switch (tmp)
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249 {
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250 case 0x00: /* HSI used as system clock source */
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251 SystemCoreClock = HSI_VALUE;
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252 break;
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253 case 0x04: /* HSE used as system clock source */
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254 SystemCoreClock = HSE_VALUE;
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255 break;
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256 case 0x08: /* PLL used as system clock source */
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257
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258 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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259 SYSCLK = PLL_VCO / PLL_P
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260 */
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261 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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262 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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263
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264 if (pllsource != 0)
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265 {
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266 /* HSE used as PLL clock source */
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267 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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268 }
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269 else
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270 {
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271 /* HSI used as PLL clock source */
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272 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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273 }
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274
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275 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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276 SystemCoreClock = pllvco/pllp;
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277 break;
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278 default:
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279 SystemCoreClock = HSI_VALUE;
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280 break;
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281 }
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282 /* Compute HCLK frequency --------------------------------------------------*/
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283 /* Get HCLK prescaler */
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284 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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285 /* HCLK frequency */
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286 SystemCoreClock >>= tmp;
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287 }
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288
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289 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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290 /**
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291 * @brief Setup the external memory controller.
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292 * Called in startup_stm32f4xx.s before jump to main.
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293 * This function configures the external memories (SRAM/SDRAM)
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294 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
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295 * @param None
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296 * @retval None
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297 */
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298 void SystemInit_ExtMemCtl(void)
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299 {
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300 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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301 #if defined (DATA_IN_ExtSDRAM)
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302 register uint32_t tmpreg = 0, timeout = 0xFFFF;
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303 register uint32_t index;
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304
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305 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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306 clock */
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307 RCC->AHB1ENR |= 0x000001F8;
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308
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309 /* Connect PDx pins to FMC Alternate function */
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310 GPIOD->AFR[0] = 0x000000CC;
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311 GPIOD->AFR[1] = 0xCC000CCC;
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312 /* Configure PDx pins in Alternate function mode */
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313 GPIOD->MODER = 0xA02A000A;
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314 /* Configure PDx pins speed to 50 MHz */
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315 GPIOD->OSPEEDR = 0xA02A000A;
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316 /* Configure PDx pins Output type to push-pull */
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317 GPIOD->OTYPER = 0x00000000;
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318 /* No pull-up, pull-down for PDx pins */
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319 GPIOD->PUPDR = 0x00000000;
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320
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321 /* Connect PEx pins to FMC Alternate function */
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322 GPIOE->AFR[0] = 0xC00000CC;
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323 GPIOE->AFR[1] = 0xCCCCCCCC;
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324 /* Configure PEx pins in Alternate function mode */
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325 GPIOE->MODER = 0xAAAA800A;
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326 /* Configure PEx pins speed to 50 MHz */
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327 GPIOE->OSPEEDR = 0xAAAA800A;
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328 /* Configure PEx pins Output type to push-pull */
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329 GPIOE->OTYPER = 0x00000000;
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330 /* No pull-up, pull-down for PEx pins */
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331 GPIOE->PUPDR = 0x00000000;
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332
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333 /* Connect PFx pins to FMC Alternate function */
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334 GPIOF->AFR[0] = 0xCCCCCCCC;
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335 GPIOF->AFR[1] = 0xCCCCCCCC;
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336 /* Configure PFx pins in Alternate function mode */
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337 GPIOF->MODER = 0xAA800AAA;
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338 /* Configure PFx pins speed to 50 MHz */
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339 GPIOF->OSPEEDR = 0xAA800AAA;
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340 /* Configure PFx pins Output type to push-pull */
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341 GPIOF->OTYPER = 0x00000000;
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342 /* No pull-up, pull-down for PFx pins */
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343 GPIOF->PUPDR = 0x00000000;
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344
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345 /* Connect PGx pins to FMC Alternate function */
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346 GPIOG->AFR[0] = 0xCCCCCCCC;
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347 GPIOG->AFR[1] = 0xCCCCCCCC;
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parents:
diff changeset
348 /* Configure PGx pins in Alternate function mode */
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jDG
parents:
diff changeset
349 GPIOG->MODER = 0xAAAAAAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
350 /* Configure PGx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
351 GPIOG->OSPEEDR = 0xAAAAAAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
352 /* Configure PGx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
353 GPIOG->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
354 /* No pull-up, pull-down for PGx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
355 GPIOG->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
356
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
357 /* Connect PHx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
358 GPIOH->AFR[0] = 0x00C0CC00;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
359 GPIOH->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
360 /* Configure PHx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
361 GPIOH->MODER = 0xAAAA08A0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
362 /* Configure PHx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
363 GPIOH->OSPEEDR = 0xAAAA08A0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
364 /* Configure PHx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
365 GPIOH->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
366 /* No pull-up, pull-down for PHx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
367 GPIOH->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
368
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
369 /* Connect PIx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
370 GPIOI->AFR[0] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
371 GPIOI->AFR[1] = 0x00000CC0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
372 /* Configure PIx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
373 GPIOI->MODER = 0x0028AAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
374 /* Configure PIx pins speed to 50 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
375 GPIOI->OSPEEDR = 0x0028AAAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
376 /* Configure PIx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
377 GPIOI->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
378 /* No pull-up, pull-down for PIx pins */
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jDG
parents:
diff changeset
379 GPIOI->PUPDR = 0x00000000;
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jDG
parents:
diff changeset
380
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jDG
parents:
diff changeset
381 /*-- FMC Configuration ------------------------------------------------------*/
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jDG
parents:
diff changeset
382 /* Enable the FMC interface clock */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
383 RCC->AHB3ENR |= 0x00000001;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
384
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jDG
parents:
diff changeset
385 /* Configure and enable SDRAM bank1 */
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jDG
parents:
diff changeset
386 FMC_Bank5_6->SDCR[0] = 0x000019E0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
387 FMC_Bank5_6->SDTR[0] = 0x01115351;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
388
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jDG
parents:
diff changeset
389 /* SDRAM initialization sequence */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
390 /* Clock enable command */
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jDG
parents:
diff changeset
391 FMC_Bank5_6->SDCMR = 0x00000011;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
392 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
393 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
394 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
395 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
396 }
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jDG
parents:
diff changeset
397
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
398 /* Delay */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
399 for (index = 0; index<1000; index++);
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
400
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
401 /* PALL command */
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jDG
parents:
diff changeset
402 FMC_Bank5_6->SDCMR = 0x00000012;
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jDG
parents:
diff changeset
403 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
404 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
405 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
406 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
407 }
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
408
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
409 /* Auto refresh command */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
410 FMC_Bank5_6->SDCMR = 0x00000073;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
411 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
412 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
413 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
414 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
415 }
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jDG
parents:
diff changeset
416
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
417 /* MRD register program */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
418 FMC_Bank5_6->SDCMR = 0x00046014;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
419 timeout = 0xFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
420 while((tmpreg != 0) && (timeout-- > 0))
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
421 {
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
422 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
423 }
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
424
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
425 /* Set refresh count */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
426 tmpreg = FMC_Bank5_6->SDRTR;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
427 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
428
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
429 /* Disable write protection */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
430 tmpreg = FMC_Bank5_6->SDCR[0];
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
431 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
432 #endif /* DATA_IN_ExtSDRAM */
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jDG
parents:
diff changeset
433 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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jDG
parents:
diff changeset
434
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
435 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
436 #if defined(DATA_IN_ExtSRAM)
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jDG
parents:
diff changeset
437 /*-- GPIOs Configuration -----------------------------------------------------*/
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
438 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
439 RCC->AHB1ENR |= 0x00000078;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
440
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
441 /* Connect PDx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
442 GPIOD->AFR[0] = 0x00CCC0CC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
443 GPIOD->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
444 /* Configure PDx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
445 GPIOD->MODER = 0xAAAA0A8A;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
446 /* Configure PDx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
447 GPIOD->OSPEEDR = 0xFFFF0FCF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
448 /* Configure PDx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
449 GPIOD->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
450 /* No pull-up, pull-down for PDx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
451 GPIOD->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
452
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
453 /* Connect PEx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
454 GPIOE->AFR[0] = 0xC00CC0CC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
455 GPIOE->AFR[1] = 0xCCCCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
456 /* Configure PEx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
457 GPIOE->MODER = 0xAAAA828A;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
458 /* Configure PEx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
459 GPIOE->OSPEEDR = 0xFFFFC3CF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
460 /* Configure PEx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
461 GPIOE->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
462 /* No pull-up, pull-down for PEx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
463 GPIOE->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
464
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
465 /* Connect PFx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
466 GPIOF->AFR[0] = 0x00CCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
467 GPIOF->AFR[1] = 0xCCCC0000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
468 /* Configure PFx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
469 GPIOF->MODER = 0xAA000AAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
470 /* Configure PFx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
471 GPIOF->OSPEEDR = 0xFF000FFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
472 /* Configure PFx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
473 GPIOF->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
474 /* No pull-up, pull-down for PFx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
475 GPIOF->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
476
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
477 /* Connect PGx pins to FMC Alternate function */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
478 GPIOG->AFR[0] = 0x00CCCCCC;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
479 GPIOG->AFR[1] = 0x000000C0;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
480 /* Configure PGx pins in Alternate function mode */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
481 GPIOG->MODER = 0x00085AAA;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
482 /* Configure PGx pins speed to 100 MHz */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
483 GPIOG->OSPEEDR = 0x000CAFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
484 /* Configure PGx pins Output type to push-pull */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
485 GPIOG->OTYPER = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
486 /* No pull-up, pull-down for PGx pins */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
487 GPIOG->PUPDR = 0x00000000;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
488
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
489 /*-- FMC/FSMC Configuration --------------------------------------------------*/
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
490 /* Enable the FMC/FSMC interface clock */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
491 RCC->AHB3ENR |= 0x00000001;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
492
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
493 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
494 /* Configure and enable Bank1_SRAM2 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
495 FMC_Bank1->BTCR[2] = 0x00001011;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
496 FMC_Bank1->BTCR[3] = 0x00000201;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
497 FMC_Bank1E->BWTR[2] = 0x0fffffff;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
498 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
499
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
500 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
501 /* Configure and enable Bank1_SRAM2 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
502 FSMC_Bank1->BTCR[2] = 0x00001011;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
503 FSMC_Bank1->BTCR[3] = 0x00000201;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
504 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
505 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
506
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
507 #endif /* DATA_IN_ExtSRAM */
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jDG
parents:
diff changeset
508 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
509 }
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
510 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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jDG
parents:
diff changeset
511 /**
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
512 * @}
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
513 */
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
514
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
diff changeset
515 /**
2de06b1abed3 CLEAN retrieve original startup code. reset linker script.
jDG
parents:
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516 * @}
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517 */
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518
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519 /**
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520 * @}
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521 */
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522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/