Mercurial > public > ostc4
annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_qspi.h @ 638:4532953ac1a0
Added last measured PPO2 value to sensor selection dialog:
In the divemenu => setpoint => UseSensor menu just the number of the sensor was as label. To have a better base for the selection decision the last measured value is now added to the label.
author | Ideenmodellierer |
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date | Wed, 24 Feb 2021 21:45:35 +0100 |
parents | c78bcbd5deda |
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rev | line source |
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1 /** |
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2 ****************************************************************************** |
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3 * @file stm32f4xx_hal_qspi.h |
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4 * @author MCD Application Team |
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5 * @brief Header file of QSPI HAL module. |
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6 ****************************************************************************** |
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7 * @attention |
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8 * |
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9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
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10 * |
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11 * Redistribution and use in source and binary forms, with or without modification, |
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12 * are permitted provided that the following conditions are met: |
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13 * 1. Redistributions of source code must retain the above copyright notice, |
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14 * this list of conditions and the following disclaimer. |
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15 * 2. Redistributions in binary form must reproduce the above copyright notice, |
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16 * this list of conditions and the following disclaimer in the documentation |
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17 * and/or other materials provided with the distribution. |
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors |
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19 * may be used to endorse or promote products derived from this software |
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20 * without specific prior written permission. |
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21 * |
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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32 * |
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33 ****************************************************************************** |
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34 */ |
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35 |
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36 /* Define to prevent recursive inclusion -------------------------------------*/ |
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37 #ifndef __STM32F4xx_HAL_QSPI_H |
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38 #define __STM32F4xx_HAL_QSPI_H |
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39 |
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40 #ifdef __cplusplus |
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41 extern "C" { |
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42 #endif |
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43 |
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44 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ |
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45 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) |
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46 /* Includes ------------------------------------------------------------------*/ |
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47 #include "stm32f4xx_hal_def.h" |
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48 |
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49 /** @addtogroup STM32F4xx_HAL_Driver |
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50 * @{ |
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51 */ |
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52 |
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53 /** @addtogroup QSPI |
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54 * @{ |
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55 */ |
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56 |
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57 /* Exported types ------------------------------------------------------------*/ |
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58 /** @defgroup QSPI_Exported_Types QSPI Exported Types |
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59 * @{ |
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60 */ |
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61 |
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62 /** |
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63 * @brief QSPI Init structure definition |
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64 */ |
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65 |
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66 typedef struct |
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67 { |
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68 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. |
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69 This parameter can be a number between 0 and 255 */ |
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70 |
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71 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) |
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72 This parameter can be a value between 1 and 32 */ |
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73 |
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74 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to |
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75 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
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76 This parameter can be a value of @ref QSPI_SampleShifting */ |
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77 |
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78 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits |
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79 required to address the flash memory. The flash capacity can be up to 4GB |
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80 (addressed using 32 bits) in indirect mode, but the addressable space in |
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81 memory-mapped mode is limited to 256MB |
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82 This parameter can be a number between 0 and 31 */ |
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83 |
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84 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number |
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85 of clock cycles which the chip select must remain high between commands. |
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86 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
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87 |
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88 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. |
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89 This parameter can be a value of @ref QSPI_ClockMode */ |
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90 |
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91 uint32_t FlashID; /* Specifies the Flash which will be used, |
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92 This parameter can be a value of @ref QSPI_Flash_Select */ |
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93 |
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94 uint32_t DualFlash; /* Specifies the Dual Flash Mode State |
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95 This parameter can be a value of @ref QSPI_DualFlash_Mode */ |
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96 }QSPI_InitTypeDef; |
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97 |
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98 /** |
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99 * @brief HAL QSPI State structures definition |
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100 */ |
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101 typedef enum |
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102 { |
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103 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ |
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104 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ |
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105 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ |
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106 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ |
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107 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ |
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108 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ |
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109 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ |
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110 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ |
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111 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ |
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112 }HAL_QSPI_StateTypeDef; |
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113 |
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114 /** |
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115 * @brief QSPI Handle Structure definition |
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116 */ |
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117 typedef struct |
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118 { |
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119 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
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120 QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
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121 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
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122 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ |
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123 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ |
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124 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
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125 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ |
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126 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ |
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127 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
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128 __IO HAL_LockTypeDef Lock; /* Locking object */ |
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129 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
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130 __IO uint32_t ErrorCode; /* QSPI Error code */ |
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131 uint32_t Timeout; /* Timeout for the QSPI memory access */ |
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132 }QSPI_HandleTypeDef; |
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133 |
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134 /** |
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135 * @brief QSPI Command structure definition |
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136 */ |
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137 typedef struct |
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138 { |
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139 uint32_t Instruction; /* Specifies the Instruction to be sent |
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140 This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
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141 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) |
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142 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ |
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143 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) |
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144 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFFU */ |
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145 uint32_t AddressSize; /* Specifies the Address Size |
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146 This parameter can be a value of @ref QSPI_AddressSize */ |
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147 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size |
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148 This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
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149 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. |
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150 This parameter can be a number between 0 and 31 */ |
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151 uint32_t InstructionMode; /* Specifies the Instruction Mode |
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152 This parameter can be a value of @ref QSPI_InstructionMode */ |
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153 uint32_t AddressMode; /* Specifies the Address Mode |
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154 This parameter can be a value of @ref QSPI_AddressMode */ |
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155 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode |
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156 This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
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157 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) |
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158 This parameter can be a value of @ref QSPI_DataMode */ |
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159 uint32_t NbData; /* Specifies the number of data to transfer. |
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160 This parameter can be any value between 0 and 0xFFFFFFFFU (0 means undefined length |
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161 until end of memory)*/ |
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162 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase |
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163 This parameter can be a value of @ref QSPI_DdrMode */ |
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164 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of |
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165 system clock in DDR mode. |
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166 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
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167 uint32_t SIOOMode; /* Specifies the send instruction only once mode |
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168 This parameter can be a value of @ref QSPI_SIOOMode */ |
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169 }QSPI_CommandTypeDef; |
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170 |
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171 /** |
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172 * @brief QSPI Auto Polling mode configuration structure definition |
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173 */ |
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174 typedef struct |
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175 { |
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176 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. |
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177 This parameter can be any value between 0 and 0xFFFFFFFFU */ |
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178 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. |
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179 This parameter can be any value between 0 and 0xFFFFFFFFU */ |
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180 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. |
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181 This parameter can be any value between 0 and 0xFFFFU */ |
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182 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. |
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183 This parameter can be any value between 1 and 4 */ |
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184 uint32_t MatchMode; /* Specifies the method used for determining a match. |
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185 This parameter can be a value of @ref QSPI_MatchMode */ |
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186 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. |
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187 This parameter can be a value of @ref QSPI_AutomaticStop */ |
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188 }QSPI_AutoPollingTypeDef; |
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189 |
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190 /** |
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191 * @brief QSPI Memory Mapped mode configuration structure definition |
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192 */ |
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193 typedef struct |
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194 { |
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195 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. |
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196 This parameter can be any value between 0 and 0xFFFFU */ |
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197 uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. |
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198 This parameter can be a value of @ref QSPI_TimeOutActivation */ |
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199 }QSPI_MemoryMappedTypeDef; |
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200 /** |
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201 * @} |
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202 */ |
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203 |
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204 /* Exported constants --------------------------------------------------------*/ |
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205 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants |
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206 * @{ |
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207 */ |
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208 /** @defgroup QSPI_ErrorCode QSPI Error Code |
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209 * @{ |
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210 */ |
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211 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ |
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212 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ |
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213 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ |
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214 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ |
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215 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ |
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216 /** |
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217 * @} |
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218 */ |
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219 |
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220 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting |
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221 * @{ |
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222 */ |
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223 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ |
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224 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
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225 /** |
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226 * @} |
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227 */ |
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228 |
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229 /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time |
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230 * @{ |
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231 */ |
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232 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ |
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233 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
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234 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
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235 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
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236 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
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237 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
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238 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
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239 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
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240 /** |
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241 * @} |
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242 */ |
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243 |
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244 /** @defgroup QSPI_ClockMode QSPI Clock Mode |
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245 * @{ |
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246 */ |
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247 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ |
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248 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
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249 /** |
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250 * @} |
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251 */ |
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252 |
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253 /** @defgroup QSPI_Flash_Select QSPI Flash Select |
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254 * @{ |
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255 */ |
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256 #define QSPI_FLASH_ID_1 0x00000000U |
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257 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) |
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258 /** |
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259 * @} |
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260 */ |
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261 |
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262 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode |
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263 * @{ |
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264 */ |
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265 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) |
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266 #define QSPI_DUALFLASH_DISABLE 0x00000000U |
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267 /** |
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268 * @} |
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269 */ |
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270 |
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271 /** @defgroup QSPI_AddressSize QSPI Address Size |
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272 * @{ |
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273 */ |
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274 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ |
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275 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
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276 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
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277 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
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278 /** |
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279 * @} |
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280 */ |
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281 |
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282 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size |
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283 * @{ |
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284 */ |
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285 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ |
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286 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
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287 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
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288 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
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289 /** |
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290 * @} |
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291 */ |
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292 |
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293 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode |
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294 * @{ |
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295 */ |
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296 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ |
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297 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
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298 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
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299 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
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300 /** |
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301 * @} |
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302 */ |
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303 |
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304 /** @defgroup QSPI_AddressMode QSPI Address Mode |
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305 * @{ |
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306 */ |
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307 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ |
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308 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
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309 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
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310 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
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311 /** |
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312 * @} |
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313 */ |
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314 |
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315 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode |
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316 * @{ |
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317 */ |
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318 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ |
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319 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
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320 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
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321 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
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322 /** |
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323 * @} |
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324 */ |
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325 |
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326 /** @defgroup QSPI_DataMode QSPI Data Mode |
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327 * @{ |
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328 */ |
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329 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ |
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330 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
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331 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
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332 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
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333 /** |
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334 * @} |
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335 */ |
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336 |
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337 /** @defgroup QSPI_DdrMode QSPI Ddr Mode |
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338 * @{ |
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339 */ |
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340 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ |
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341 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
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342 /** |
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343 * @} |
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344 */ |
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345 |
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346 /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle |
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347 * @{ |
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348 */ |
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349 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ |
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350 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ |
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351 /** |
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352 * @} |
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353 */ |
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354 |
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355 /** @defgroup QSPI_SIOOMode QSPI SIOO Mode |
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356 * @{ |
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357 */ |
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358 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ |
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359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
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360 /** |
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361 * @} |
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362 */ |
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363 |
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364 /** @defgroup QSPI_MatchMode QSPI Match Mode |
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365 * @{ |
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366 */ |
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367 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ |
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368 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
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369 /** |
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370 * @} |
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371 */ |
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372 |
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373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop |
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374 * @{ |
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375 */ |
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376 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ |
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377 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
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378 /** |
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379 * @} |
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380 */ |
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381 |
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382 /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation |
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383 * @{ |
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384 */ |
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385 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ |
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386 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
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387 /** |
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388 * @} |
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389 */ |
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390 |
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391 /** @defgroup QSPI_Flags QSPI Flags |
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392 * @{ |
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393 */ |
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394 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
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395 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
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396 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
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397 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
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398 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
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399 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
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400 /** |
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401 * @} |
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402 */ |
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403 |
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404 /** @defgroup QSPI_Interrupts QSPI Interrupts |
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405 * @{ |
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406 */ |
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407 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
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408 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
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409 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
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410 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
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411 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
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412 /** |
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413 * @} |
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414 */ |
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415 |
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416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition |
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417 * @{ |
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418 */ |
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419 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ |
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420 /** |
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421 * @} |
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422 */ |
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423 |
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424 /** |
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425 * @} |
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426 */ |
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427 |
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428 /* Exported macros -----------------------------------------------------------*/ |
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429 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros |
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430 * @{ |
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431 */ |
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432 |
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433 /** @brief Reset QSPI handle state |
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434 * @param __HANDLE__ QSPI handle. |
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435 * @retval None |
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436 */ |
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437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
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438 |
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439 /** @brief Enable QSPI |
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440 * @param __HANDLE__ specifies the QSPI Handle. |
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441 * @retval None |
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442 */ |
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443 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
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444 |
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445 /** @brief Disable QSPI |
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446 * @param __HANDLE__ specifies the QSPI Handle. |
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447 * @retval None |
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448 */ |
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449 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
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450 |
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451 /** @brief Enables the specified QSPI interrupt. |
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452 * @param __HANDLE__ specifies the QSPI Handle. |
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453 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. |
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454 * This parameter can be one of the following values: |
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455 * @arg QSPI_IT_TO: QSPI Time out interrupt |
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456 * @arg QSPI_IT_SM: QSPI Status match interrupt |
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457 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
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458 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
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459 * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
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460 * @retval None |
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461 */ |
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462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
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463 |
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464 |
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465 /** @brief Disables the specified QSPI interrupt. |
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466 * @param __HANDLE__ specifies the QSPI Handle. |
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467 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. |
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468 * This parameter can be one of the following values: |
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469 * @arg QSPI_IT_TO: QSPI Timeout interrupt |
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470 * @arg QSPI_IT_SM: QSPI Status match interrupt |
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471 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
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472 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
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473 * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
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474 * @retval None |
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475 */ |
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476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
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477 |
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478 /** @brief Checks whether the specified QSPI interrupt source is enabled. |
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479 * @param __HANDLE__ specifies the QSPI Handle. |
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480 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. |
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481 * This parameter can be one of the following values: |
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482 * @arg QSPI_IT_TO: QSPI Time out interrupt |
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483 * @arg QSPI_IT_SM: QSPI Status match interrupt |
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484 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
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485 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
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486 * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
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487 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
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488 */ |
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489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
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490 |
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491 /** |
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492 * @brief Get the selected QSPI's flag status. |
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493 * @param __HANDLE__ specifies the QSPI Handle. |
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494 * @param __FLAG__ specifies the QSPI flag to check. |
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495 * This parameter can be one of the following values: |
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496 * @arg QSPI_FLAG_BUSY: QSPI Busy flag |
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497 * @arg QSPI_FLAG_TO: QSPI Time out flag |
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498 * @arg QSPI_FLAG_SM: QSPI Status match flag |
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499 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
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500 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
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501 * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
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502 * @retval None |
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503 */ |
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504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) |
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505 |
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506 /** @brief Clears the specified QSPI's flag status. |
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507 * @param __HANDLE__ specifies the QSPI Handle. |
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508 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set |
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509 * This parameter can be one of the following values: |
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510 * @arg QSPI_FLAG_TO: QSPI Time out flag |
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511 * @arg QSPI_FLAG_SM: QSPI Status match flag |
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512 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
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513 * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
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514 * @retval None |
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515 */ |
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516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
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517 /** |
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518 * @} |
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519 */ |
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520 |
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521 /* Exported functions --------------------------------------------------------*/ |
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522 /** @addtogroup QSPI_Exported_Functions |
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523 * @{ |
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524 */ |
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525 |
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526 /** @addtogroup QSPI_Exported_Functions_Group1 |
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527 * @{ |
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528 */ |
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529 /* Initialization/de-initialization functions ********************************/ |
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530 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
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531 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
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532 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
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533 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
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534 /** |
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535 * @} |
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536 */ |
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537 |
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538 /** @addtogroup QSPI_Exported_Functions_Group2 |
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539 * @{ |
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540 */ |
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541 /* IO operation functions *****************************************************/ |
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542 /* QSPI IRQ handler method */ |
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543 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
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544 |
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545 /* QSPI indirect mode */ |
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546 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
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547 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
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548 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
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549 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
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550 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
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551 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
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552 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
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553 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
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554 |
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555 /* QSPI status flag polling mode */ |
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556 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
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557 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
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558 |
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559 /* QSPI memory-mapped mode */ |
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560 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
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561 /** |
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562 * @} |
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563 */ |
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564 |
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565 /** @addtogroup QSPI_Exported_Functions_Group3 |
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566 * @{ |
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567 */ |
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568 /* Callback functions in non-blocking modes ***********************************/ |
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569 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
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570 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); |
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571 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
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572 |
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573 /* QSPI indirect mode */ |
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574 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
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575 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
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576 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
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577 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
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578 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
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579 |
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580 /* QSPI status flag polling mode */ |
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581 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
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582 |
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583 /* QSPI memory-mapped mode */ |
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584 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
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585 /** |
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586 * @} |
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587 */ |
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588 |
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589 /** @addtogroup QSPI_Exported_Functions_Group4 |
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590 * @{ |
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591 */ |
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592 /* Peripheral Control and State functions ************************************/ |
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593 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
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594 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
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595 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
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596 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); |
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597 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
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598 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); |
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599 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); |
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600 /** |
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601 * @} |
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602 */ |
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603 |
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604 /* Private macros ------------------------------------------------------------*/ |
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605 /** @defgroup QSPI_Private_Macros QSPI Private Macros |
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606 * @{ |
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607 */ |
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608 /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler |
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609 * @{ |
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610 */ |
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611 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) |
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612 /** |
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613 * @} |
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614 */ |
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615 |
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616 /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold |
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617 * @{ |
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618 */ |
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619 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) |
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620 /** |
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621 * @} |
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622 */ |
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623 |
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624 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
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625 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
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626 |
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627 /** @defgroup QSPI_FlashSize QSPI Flash Size |
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628 * @{ |
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629 */ |
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630 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) |
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631 /** |
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632 * @} |
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633 */ |
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634 |
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635 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
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636 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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637 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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638 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
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|
639 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
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640 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
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641 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
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642 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
c78bcbd5deda
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|
643 |
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|
644 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
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645 ((CLKMODE) == QSPI_CLOCK_MODE_3)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
646 |
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|
647 #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
648 ((FLA) == QSPI_FLASH_ID_2)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
649 |
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Added current STM32 standandard libraries in version independend folder structure
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|
650 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ |
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|
651 ((MODE) == QSPI_DUALFLASH_DISABLE)) |
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|
652 |
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|
653 |
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changeset
|
654 /** @defgroup QSPI_Instruction QSPI Instruction |
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|
655 * @{ |
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|
656 */ |
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657 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) |
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658 /** |
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|
659 * @} |
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Added current STM32 standandard libraries in version independend folder structure
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|
660 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
661 |
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662 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
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|
663 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
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664 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
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665 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
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|
666 |
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|
667 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
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|
668 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
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669 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
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670 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
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|
671 |
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|
672 |
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|
673 /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles |
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|
674 * @{ |
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|
675 */ |
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|
676 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) |
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|
677 /** |
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|
678 * @} |
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|
679 */ |
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|
680 |
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|
681 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
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|
682 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
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|
683 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
684 ((MODE) == QSPI_INSTRUCTION_4_LINES)) |
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|
685 |
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Ideenmodellierer
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diff
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|
686 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
687 ((MODE) == QSPI_ADDRESS_1_LINE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
688 ((MODE) == QSPI_ADDRESS_2_LINES) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
689 ((MODE) == QSPI_ADDRESS_4_LINES)) |
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Added current STM32 standandard libraries in version independend folder structure
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|
690 |
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|
691 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
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|
692 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
693 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
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|
694 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
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|
695 |
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|
696 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
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|
697 ((MODE) == QSPI_DATA_1_LINE) || \ |
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|
698 ((MODE) == QSPI_DATA_2_LINES) || \ |
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|
699 ((MODE) == QSPI_DATA_4_LINES)) |
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|
700 |
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|
701 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
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Added current STM32 standandard libraries in version independend folder structure
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|
702 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
c78bcbd5deda
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|
703 |
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Ideenmodellierer
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diff
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|
704 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ |
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Ideenmodellierer
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|
705 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) |
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Added current STM32 standandard libraries in version independend folder structure
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parents:
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|
706 |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
707 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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|
708 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
709 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
710 /** @defgroup QSPI_Interval QSPI Interval |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
711 * @{ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
712 */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
713 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
714 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
715 * @} |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
716 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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changeset
|
717 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
718 /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
719 * @{ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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|
720 */ |
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Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
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|
721 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
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|
722 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
723 * @} |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
724 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
725 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
726 ((MODE) == QSPI_MATCH_MODE_OR)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
727 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
728 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
729 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
730 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
731 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
732 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
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changeset
|
733 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
734 /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
735 * @{ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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changeset
|
736 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
737 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
738 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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changeset
|
739 * @} |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
740 */ |
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Added current STM32 standandard libraries in version independend folder structure
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|
741 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
742 #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
743 ((FLAG) == QSPI_FLAG_TO) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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changeset
|
744 ((FLAG) == QSPI_FLAG_SM) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
745 ((FLAG) == QSPI_FLAG_FT) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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changeset
|
746 ((FLAG) == QSPI_FLAG_TC) || \ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
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|
747 ((FLAG) == QSPI_FLAG_TE)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
748 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
749 #define IS_QSPI_IT(IT) ((((IT) & 0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
750 /** |
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Added current STM32 standandard libraries in version independend folder structure
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changeset
|
751 * @} |
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Added current STM32 standandard libraries in version independend folder structure
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changeset
|
752 */ |
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Added current STM32 standandard libraries in version independend folder structure
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changeset
|
753 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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changeset
|
754 /* Private functions ---------------------------------------------------------*/ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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|
755 /** @defgroup QSPI_Private_Functions QSPI Private Functions |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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changeset
|
756 * @{ |
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Added current STM32 standandard libraries in version independend folder structure
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changeset
|
757 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
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diff
changeset
|
758 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
759 /** |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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changeset
|
760 * @} |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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changeset
|
761 */ |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
parents:
diff
changeset
|
762 |
c78bcbd5deda
Added current STM32 standandard libraries in version independend folder structure
Ideenmodellierer
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diff
changeset
|
763 /** |
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764 * @} |
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765 */ |
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766 |
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767 /** |
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768 * @} |
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769 */ |
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770 |
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771 /** |
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772 * @} |
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773 */ |
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774 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || |
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775 STM32F413xx || STM32F423xx */ |
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776 |
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777 #ifdef __cplusplus |
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778 } |
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779 #endif |
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780 |
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781 #endif /* __STM32F4xx_HAL_QSPI_H */ |
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782 |
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783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |