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annotate Documentations/OSTC4_CPU1_F429.ioc @ 944:44599695df41 Evo_2_23

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Restructure Date/Time menu: To have more space for upcoming optins the selection of the date format (DDMMYY) has been moved into a submenu. In addition the function was upgraded to support multi language handling.
author Ideenmodellierer
date Thu, 19 Dec 2024 18:58:18 +0100
parents 7d1b61176708
children
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1
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1 #MicroXplorer Configuration settings - do not modify
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2 #Fri May 22 13:40:39 CEST 2015
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3 File.Version=5
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4 KeepUserPlacement=false
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5 Mcu.Family=STM32F4
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6 Mcu.IP0=DMA2D
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7 Mcu.IP1=FMC
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8 Mcu.IP10=SPI5
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9 Mcu.IP11=SYS
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10 Mcu.IP12=USART1
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11 Mcu.IP2=I2C1
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12 Mcu.IP3=LTDC
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13 Mcu.IP4=NVIC
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14 Mcu.IP5=RCC
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15 Mcu.IP6=RTC
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16 Mcu.IP7=SPI1
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17 Mcu.IP8=SPI2
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18 Mcu.IP9=SPI3
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19 Mcu.IPNb=13
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20 Mcu.Name=STM32F429I(E-G-I)Tx
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21 Mcu.Package=LQFP176
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22 Mcu.Pin0=PE4
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23 Mcu.Pin1=PE5
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24 Mcu.Pin10=PF3
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25 Mcu.Pin11=PF4
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26 Mcu.Pin12=PF5
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27 Mcu.Pin13=PF6
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28 Mcu.Pin14=PF7
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29 Mcu.Pin15=PF8
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30 Mcu.Pin16=PF9
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31 Mcu.Pin17=PF10
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32 Mcu.Pin18=PH0/OSC_IN
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33 Mcu.Pin19=PH1/OSC_OUT
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34 Mcu.Pin2=PE6
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35 Mcu.Pin20=PC0
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36 Mcu.Pin21=PC2
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37 Mcu.Pin22=PC3
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38 Mcu.Pin23=PA0/WKUP
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39 Mcu.Pin24=PH2
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40 Mcu.Pin25=PH3
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41 Mcu.Pin26=PA3
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42 Mcu.Pin27=PA4
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43 Mcu.Pin28=PA5
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44 Mcu.Pin29=PA6
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45 Mcu.Pin3=PC14/OSC32_IN
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46 Mcu.Pin30=PA7
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47 Mcu.Pin31=PB0
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48 Mcu.Pin32=PB1
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49 Mcu.Pin33=PF11
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50 Mcu.Pin34=PF12
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51 Mcu.Pin35=PF13
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52 Mcu.Pin36=PF14
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53 Mcu.Pin37=PF15
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54 Mcu.Pin38=PG0
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55 Mcu.Pin39=PG1
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56 Mcu.Pin4=PC15/OSC32_OUT
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57 Mcu.Pin40=PE7
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58 Mcu.Pin41=PE8
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59 Mcu.Pin42=PE9
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60 Mcu.Pin43=PE10
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61 Mcu.Pin44=PE11
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62 Mcu.Pin45=PE12
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63 Mcu.Pin46=PE13
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64 Mcu.Pin47=PE14
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65 Mcu.Pin48=PE15
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66 Mcu.Pin49=PB10
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67 Mcu.Pin5=PI9
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68 Mcu.Pin50=PB11
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69 Mcu.Pin51=PH8
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70 Mcu.Pin52=PH10
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71 Mcu.Pin53=PH11
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72 Mcu.Pin54=PB12
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73 Mcu.Pin55=PB15
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74 Mcu.Pin56=PD8
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75 Mcu.Pin57=PD9
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76 Mcu.Pin58=PD10
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77 Mcu.Pin59=PD14
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78 Mcu.Pin6=PI10
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79 Mcu.Pin60=PD15
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80 Mcu.Pin61=PG4
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81 Mcu.Pin62=PG5
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82 Mcu.Pin63=PG6
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83 Mcu.Pin64=PG7
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84 Mcu.Pin65=PG8
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85 Mcu.Pin66=PC7
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86 Mcu.Pin67=PA10
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87 Mcu.Pin68=PA13
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88 Mcu.Pin69=PH13
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89 Mcu.Pin7=PF0
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90 Mcu.Pin70=PH14
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91 Mcu.Pin71=PH15
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92 Mcu.Pin72=PI2
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93 Mcu.Pin73=PI3
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94 Mcu.Pin74=PA14
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95 Mcu.Pin75=PA15
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96 Mcu.Pin76=PC10
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97 Mcu.Pin77=PC11
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98 Mcu.Pin78=PC12
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99 Mcu.Pin79=PD0
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100 Mcu.Pin8=PF1
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101 Mcu.Pin80=PD1
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102 Mcu.Pin81=PD3
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103 Mcu.Pin82=PD6
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104 Mcu.Pin83=PG11
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105 Mcu.Pin84=PG12
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106 Mcu.Pin85=PG15
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107 Mcu.Pin86=PB3
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108 Mcu.Pin87=PB6
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109 Mcu.Pin88=PB7
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110 Mcu.Pin89=PB8
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111 Mcu.Pin9=PF2
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112 Mcu.Pin90=PB9
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113 Mcu.Pin91=PE0
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114 Mcu.Pin92=PE1
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115 Mcu.Pin93=PI4
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116 Mcu.Pin94=PI6
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117 Mcu.Pin95=VP_DMA2D_VS_DMA2D
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118 Mcu.Pin96=VP_RTC_VS_RTC_Alarm_A_Intern
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119 Mcu.PinsNb=97
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120 Mcu.UserName=STM32F429IITx
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121 MxCube.Version=4.7.1
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122 MxDb.Version=DB.4.0.71
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123 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_2
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124 NVIC.SysTick_IRQn=true\:0\:0\:true
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125 PA0/WKUP.Mode=SYS-WakeUp
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126 PA0/WKUP.Signal=SYS_WKUP
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127 PA10.Mode=Asynchronous
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128 PA10.Signal=USART1_RX
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129 PA13.Mode=Trace-Asynchronous_SW
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130 PA13.Signal=SYS_JTMS-SWDIO
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131 PA14.Mode=Trace-Asynchronous_SW
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132 PA14.Signal=SYS_JTCK-SWCLK
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133 PA15.Mode=NSS_Signal_Hard
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134 PA15.Signal=SPI3_NSS
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135 PA3.Mode=RGB888
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136 PA3.Signal=LTDC_B5
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137 PA4.Mode=NSS_Signal_Hard
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138 PA4.Signal=SPI1_NSS
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139 PA5.Mode=Full_Duplex_Master
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140 PA5.Signal=SPI1_SCK
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141 PA6.Mode=Full_Duplex_Master
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142 PA6.Signal=SPI1_MISO
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143 PA7.Mode=Full_Duplex_Master
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144 PA7.Signal=SPI1_MOSI
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145 PB0.Mode=RGB888
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146 PB0.Signal=LTDC_R3
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147 PB1.Mode=RGB888
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148 PB1.Signal=LTDC_R6
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149 PB10.Mode=Full_Duplex_Master
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150 PB10.Signal=SPI2_SCK
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151 PB11.Mode=RGB888
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152 PB11.Signal=LTDC_G5
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153 PB12.Mode=NSS_Signal_Hard
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154 PB12.Signal=SPI2_NSS
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155 PB15.GPIOParameters=GPIO_Label
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156 PB15.GPIO_Label=ALLES_OK_OUTPUT
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157 PB15.Locked=true
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158 PB15.Signal=GPIO_Output
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159 PB3.Mode=Trace-Asynchronous_SW
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160 PB3.Signal=SYS_JTDO-SWO
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161 PB6.Mode=Asynchronous
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162 PB6.Signal=USART1_TX
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163 PB7.Mode=I2C
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164 PB7.Signal=I2C1_SDA
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165 PB8.Mode=I2C
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166 PB8.Signal=I2C1_SCL
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167 PB9.Mode=RGB888
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168 PB9.Signal=LTDC_B7
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169 PC0.Signal=FMC_SDNWE
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170 PC10.Mode=Full_Duplex_Master
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171 PC10.Signal=SPI3_SCK
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172 PC11.Mode=Full_Duplex_Master
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173 PC11.Signal=SPI3_MISO
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174 PC12.Mode=Full_Duplex_Master
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175 PC12.Signal=SPI3_MOSI
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176 PC14/OSC32_IN.Mode=LSE-External-Oscillator
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177 PC14/OSC32_IN.Signal=RCC_OSC32_IN
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178 PC15/OSC32_OUT.Mode=LSE-External-Oscillator
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179 PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
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180 PC2.Mode=SdramChipSelect1_2
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181 PC2.Signal=FMC_SDNE0
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182 PC3.Mode=SdramChipSelect1_2
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183 PC3.Signal=FMC_SDCKE0
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184 PC7.Mode=RGB888
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185 PC7.Signal=LTDC_G6
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186 PCC.Checker=false
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187 PCC.Family=STM32F4
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188 PCC.MCU=STM32F429I(E-G-I)Tx
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189 PCC.MXVersion=4.7.1
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190 PCC.PartNumber=STM32F429IITx
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191 PCC.Seq0=0
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192 PCC.SubFamily=STM32F429/439
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193 PCC.Temperature=25
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194 PCC.Vdd=1.8
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195 PD0.Signal=FMC_D2_DA2
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196 PD1.Signal=FMC_D3_DA3
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197 PD10.Signal=FMC_D15_DA15
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198 PD14.Signal=FMC_D0_DA0
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199 PD15.Signal=FMC_D1_DA1
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200 PD3.Mode=RGB888
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201 PD3.Signal=LTDC_G7
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202 PD6.Mode=RGB888
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203 PD6.Signal=LTDC_B2
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204 PD8.Signal=FMC_D13_DA13
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205 PD9.Signal=FMC_D14_DA14
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206 PE0.Signal=FMC_NBL0
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diff changeset
207 PE1.Signal=FMC_NBL1
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jDG
parents:
diff changeset
208 PE10.Signal=FMC_D7_DA7
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jDG
parents:
diff changeset
209 PE11.Signal=FMC_D8_DA8
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jDG
parents:
diff changeset
210 PE12.Signal=FMC_D9_DA9
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jDG
parents:
diff changeset
211 PE13.Signal=FMC_D10_DA10
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jDG
parents:
diff changeset
212 PE14.Signal=FMC_D11_DA11
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jDG
parents:
diff changeset
213 PE15.Signal=FMC_D12_DA12
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jDG
parents:
diff changeset
214 PE4.Mode=RGB888
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jDG
parents:
diff changeset
215 PE4.Signal=LTDC_B0
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jDG
parents:
diff changeset
216 PE5.Mode=RGB888
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jDG
parents:
diff changeset
217 PE5.Signal=LTDC_G0
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jDG
parents:
diff changeset
218 PE6.Mode=RGB888
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jDG
parents:
diff changeset
219 PE6.Signal=LTDC_G1
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jDG
parents:
diff changeset
220 PE7.Signal=FMC_D4_DA4
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jDG
parents:
diff changeset
221 PE8.Signal=FMC_D5_DA5
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jDG
parents:
diff changeset
222 PE9.Signal=FMC_D6_DA6
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jDG
parents:
diff changeset
223 PF0.Signal=FMC_A0
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jDG
parents:
diff changeset
224 PF1.Signal=FMC_A1
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jDG
parents:
diff changeset
225 PF10.Mode=RGB888
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jDG
parents:
diff changeset
226 PF10.Signal=LTDC_DE
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jDG
parents:
diff changeset
227 PF11.Signal=FMC_SDNRAS
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jDG
parents:
diff changeset
228 PF12.Signal=FMC_A6
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jDG
parents:
diff changeset
229 PF13.Signal=FMC_A7
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jDG
parents:
diff changeset
230 PF14.Signal=FMC_A8
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jDG
parents:
diff changeset
231 PF15.Signal=FMC_A9
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jDG
parents:
diff changeset
232 PF2.Signal=FMC_A2
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jDG
parents:
diff changeset
233 PF3.Signal=FMC_A3
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jDG
parents:
diff changeset
234 PF4.Signal=FMC_A4
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jDG
parents:
diff changeset
235 PF5.Signal=FMC_A5
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jDG
parents:
diff changeset
236 PF6.Mode=NSS_Signal_Hard
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jDG
parents:
diff changeset
237 PF6.Signal=SPI5_NSS
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jDG
parents:
diff changeset
238 PF7.Mode=Full_Duplex_Master
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jDG
parents:
diff changeset
239 PF7.Signal=SPI5_SCK
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jDG
parents:
diff changeset
240 PF8.Mode=Full_Duplex_Master
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jDG
parents:
diff changeset
241 PF8.Signal=SPI5_MISO
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jDG
parents:
diff changeset
242 PF9.Mode=Full_Duplex_Master
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jDG
parents:
diff changeset
243 PF9.Signal=SPI5_MOSI
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jDG
parents:
diff changeset
244 PG0.Signal=FMC_A10
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jDG
parents:
diff changeset
245 PG1.Signal=FMC_A11
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jDG
parents:
diff changeset
246 PG11.Mode=RGB888
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jDG
parents:
diff changeset
247 PG11.Signal=LTDC_B3
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jDG
parents:
diff changeset
248 PG12.Mode=RGB888
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jDG
parents:
diff changeset
249 PG12.Signal=LTDC_B1
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jDG
parents:
diff changeset
250 PG15.Signal=FMC_SDNCAS
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jDG
parents:
diff changeset
251 PG4.Signal=FMC_A14_BA0
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jDG
parents:
diff changeset
252 PG5.Signal=FMC_A15_BA1
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jDG
parents:
diff changeset
253 PG6.Mode=RGB888
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jDG
parents:
diff changeset
254 PG6.Signal=LTDC_R7
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jDG
parents:
diff changeset
255 PG7.Mode=RGB888
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jDG
parents:
diff changeset
256 PG7.Signal=LTDC_CLK
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jDG
parents:
diff changeset
257 PG8.Signal=FMC_SDCLK
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jDG
parents:
diff changeset
258 PH0/OSC_IN.Mode=HSE-External-Oscillator
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jDG
parents:
diff changeset
259 PH0/OSC_IN.Signal=RCC_OSC_IN
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jDG
parents:
diff changeset
260 PH1/OSC_OUT.Mode=HSE-External-Oscillator
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jDG
parents:
diff changeset
261 PH1/OSC_OUT.Signal=RCC_OSC_OUT
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jDG
parents:
diff changeset
262 PH10.Mode=RGB888
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jDG
parents:
diff changeset
263 PH10.Signal=LTDC_R4
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jDG
parents:
diff changeset
264 PH11.Mode=RGB888
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jDG
parents:
diff changeset
265 PH11.Signal=LTDC_R5
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jDG
parents:
diff changeset
266 PH13.Mode=RGB888
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jDG
parents:
diff changeset
267 PH13.Signal=LTDC_G2
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jDG
parents:
diff changeset
268 PH14.Mode=RGB888
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jDG
parents:
diff changeset
269 PH14.Signal=LTDC_G3
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jDG
parents:
diff changeset
270 PH15.Mode=RGB888
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jDG
parents:
diff changeset
271 PH15.Signal=LTDC_G4
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jDG
parents:
diff changeset
272 PH2.Mode=RGB888
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jDG
parents:
diff changeset
273 PH2.Signal=LTDC_R0
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jDG
parents:
diff changeset
274 PH3.Mode=RGB888
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jDG
parents:
diff changeset
275 PH3.Signal=LTDC_R1
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jDG
parents:
diff changeset
276 PH8.Mode=RGB888
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jDG
parents:
diff changeset
277 PH8.Signal=LTDC_R2
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jDG
parents:
diff changeset
278 PI10.Mode=RGB888
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jDG
parents:
diff changeset
279 PI10.Signal=LTDC_HSYNC
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jDG
parents:
diff changeset
280 PI2.Mode=Full_Duplex_Master
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jDG
parents:
diff changeset
281 PI2.Signal=SPI2_MISO
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jDG
parents:
diff changeset
282 PI3.Mode=Full_Duplex_Master
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jDG
parents:
diff changeset
283 PI3.Signal=SPI2_MOSI
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jDG
parents:
diff changeset
284 PI4.Mode=RGB888
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jDG
parents:
diff changeset
285 PI4.Signal=LTDC_B4
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jDG
parents:
diff changeset
286 PI6.Mode=RGB888
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jDG
parents:
diff changeset
287 PI6.Signal=LTDC_B6
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jDG
parents:
diff changeset
288 PI9.Mode=RGB888
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jDG
parents:
diff changeset
289 PI9.Signal=LTDC_VSYNC
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jDG
parents:
diff changeset
290 ProjectManager.AskForMigrate=true
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jDG
parents:
diff changeset
291 ProjectManager.BackupPrevious=false
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jDG
parents:
diff changeset
292 ProjectManager.CompilerOptimize=2
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jDG
parents:
diff changeset
293 ProjectManager.ComputerToolchain=false
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jDG
parents:
diff changeset
294 ProjectManager.CoupleFile=false
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jDG
parents:
diff changeset
295 ProjectManager.DeletePrevious=false
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jDG
parents:
diff changeset
296 ProjectManager.DeviceId=STM32F429IITx
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jDG
parents:
diff changeset
297 ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.5.0
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jDG
parents:
diff changeset
298 ProjectManager.FreePins=true
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jDG
parents:
diff changeset
299 ProjectManager.HalAssertFull=false
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jDG
parents:
diff changeset
300 ProjectManager.KeepUserCode=false
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jDG
parents:
diff changeset
301 ProjectManager.LastFirmware=true
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jDG
parents:
diff changeset
302 ProjectManager.LibraryCopy=0
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jDG
parents:
diff changeset
303 ProjectManager.ProjectBuild=false
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jDG
parents:
diff changeset
304 ProjectManager.ProjectFileName=OSTC4.ioc
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jDG
parents:
diff changeset
305 ProjectManager.ProjectName=OSTC4
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jDG
parents:
diff changeset
306 ProjectManager.TargetToolchain=MDK-ARM 4.73
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jDG
parents:
diff changeset
307 ProjectManager.ToolChainLocation=
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jDG
parents:
diff changeset
308 RCC.48MHZClocksFreq_Value=48000000
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jDG
parents:
diff changeset
309 RCC.AHBFreq_Value=168000000
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jDG
parents:
diff changeset
310 RCC.APB1CLKDivider=RCC_HCLK_DIV4
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jDG
parents:
diff changeset
311 RCC.APB1Freq_Value=42000000
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jDG
parents:
diff changeset
312 RCC.APB1TimFreq_Value=84000000
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jDG
parents:
diff changeset
313 RCC.APB2CLKDivider=RCC_HCLK_DIV2
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jDG
parents:
diff changeset
314 RCC.APB2Freq_Value=84000000
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jDG
parents:
diff changeset
315 RCC.APB2TimFreq_Value=168000000
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jDG
parents:
diff changeset
316 RCC.CortexFreq_Value=21000000
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jDG
parents:
diff changeset
317 RCC.EthernetFreq_Value=168000000
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jDG
parents:
diff changeset
318 RCC.FCLKCortexFreq_Value=168000000
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jDG
parents:
diff changeset
319 RCC.FamilyName=M
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jDG
parents:
diff changeset
320 RCC.HCLKFreq_Value=168000000
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jDG
parents:
diff changeset
321 RCC.HSE_VALUE=8000000
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jDG
parents:
diff changeset
322 RCC.HSI_VALUE=16000000
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jDG
parents:
diff changeset
323 RCC.I2SClocksFreq_Value=153600000
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jDG
parents:
diff changeset
324 RCC.IPParameters=PLLSource,LSI_VALUE,APB1TimFreq_Value,VcooutputI2SQ,SAI_AClocksFreq_Value,APB2Freq_Value,MCO2PinFreq_Value,APB1CLKDivider,PLLSourceVirtualString,FCLKCortexFreq_Value,RCC_RTC_Clock_SourceVirtual,48MHZClocksFreq_Value,AHBFreq_Value,VCOInputFreq_Value,PLLSourceVirtual,I2SClocksFreq_Value,VCOSAIOutputFreq_Value,SYSCLKFreq_VALUE,PLLQ,SYSCLKSource,LSE_VALUE,HSE_VALUE,HSI_VALUE,LCDTFTFreq_Value,VCOSAIOutputFreq_ValueQ,VCOI2SOutputFreq_Value,VCOSAIOutputFreq_ValueR,PLLCLKFreq_Value,PLLSAIN,RTCFreq_Value,VDD_VALUE,FamilyName,HCLKFreq_Value,EthernetFreq_Value,APB2CLKDivider,PLLM,PLLN,VCOOutputFreq_Value,SAI_BClocksFreq_Value,VcooutputI2S,CortexFreq_Value,APB1Freq_Value,RCC_RTC_Clock_Source_FROM_HSE,RTCHSEDivFreq_Value,APB2TimFreq_Value
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jDG
parents:
diff changeset
325 RCC.LCDTFTFreq_Value=30800000
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jDG
parents:
diff changeset
326 RCC.LSE_VALUE=32768
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jDG
parents:
diff changeset
327 RCC.LSI_VALUE=32000
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jDG
parents:
diff changeset
328 RCC.MCO2PinFreq_Value=168000000
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jDG
parents:
diff changeset
329 RCC.PLLCLKFreq_Value=168000000
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jDG
parents:
diff changeset
330 RCC.PLLM=5
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jDG
parents:
diff changeset
331 RCC.PLLN=210
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jDG
parents:
diff changeset
332 RCC.PLLQ=7
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jDG
parents:
diff changeset
333 RCC.PLLSAIN=77
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jDG
parents:
diff changeset
334 RCC.PLLSource=RCC_PLLSOURCE_HSE
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jDG
parents:
diff changeset
335 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
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jDG
parents:
diff changeset
336 RCC.PLLSourceVirtualString=RCC_PLLSOURCE_HSE
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jDG
parents:
diff changeset
337 RCC.RCC_RTC_Clock_SourceVirtual=RCC_RTCCLKSOURCE_LSE
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jDG
parents:
diff changeset
338 RCC.RCC_RTC_Clock_Source_FROM_HSE=RCC_RTCCLKSOURCE_HSE_DIV25
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jDG
parents:
diff changeset
339 RCC.RTCFreq_Value=32768
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jDG
parents:
diff changeset
340 RCC.RTCHSEDivFreq_Value=320000
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jDG
parents:
diff changeset
341 RCC.SAI_AClocksFreq_Value=30800000
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jDG
parents:
diff changeset
342 RCC.SAI_BClocksFreq_Value=30800000
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jDG
parents:
diff changeset
343 RCC.SYSCLKFreq_VALUE=168000000
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jDG
parents:
diff changeset
344 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
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jDG
parents:
diff changeset
345 RCC.VCOI2SOutputFreq_Value=307200000
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jDG
parents:
diff changeset
346 RCC.VCOInputFreq_Value=1600000
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jDG
parents:
diff changeset
347 RCC.VCOOutputFreq_Value=336000000
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jDG
parents:
diff changeset
348 RCC.VCOSAIOutputFreq_Value=123200000
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jDG
parents:
diff changeset
349 RCC.VCOSAIOutputFreq_ValueQ=30800000
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jDG
parents:
diff changeset
350 RCC.VCOSAIOutputFreq_ValueR=61600000
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jDG
parents:
diff changeset
351 RCC.VDD_VALUE=1.8
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jDG
parents:
diff changeset
352 RCC.VcooutputI2S=153600000
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jDG
parents:
diff changeset
353 RCC.VcooutputI2SQ=153600000
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jDG
parents:
diff changeset
354 SH.FMC_A0.0=FMC_A0,12b-sda2
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jDG
parents:
diff changeset
355 SH.FMC_A0.ConfNb=1
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jDG
parents:
diff changeset
356 SH.FMC_A1.0=FMC_A1,12b-sda2
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jDG
parents:
diff changeset
357 SH.FMC_A1.ConfNb=1
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jDG
parents:
diff changeset
358 SH.FMC_A10.0=FMC_A10,12b-sda2
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jDG
parents:
diff changeset
359 SH.FMC_A10.ConfNb=1
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jDG
parents:
diff changeset
360 SH.FMC_A11.0=FMC_A11,12b-sda2
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jDG
parents:
diff changeset
361 SH.FMC_A11.ConfNb=1
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jDG
parents:
diff changeset
362 SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks2
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jDG
parents:
diff changeset
363 SH.FMC_A14_BA0.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
364 SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
365 SH.FMC_A15_BA1.ConfNb=1
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jDG
parents:
diff changeset
366 SH.FMC_A2.0=FMC_A2,12b-sda2
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jDG
parents:
diff changeset
367 SH.FMC_A2.ConfNb=1
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jDG
parents:
diff changeset
368 SH.FMC_A3.0=FMC_A3,12b-sda2
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jDG
parents:
diff changeset
369 SH.FMC_A3.ConfNb=1
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jDG
parents:
diff changeset
370 SH.FMC_A4.0=FMC_A4,12b-sda2
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jDG
parents:
diff changeset
371 SH.FMC_A4.ConfNb=1
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jDG
parents:
diff changeset
372 SH.FMC_A5.0=FMC_A5,12b-sda2
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jDG
parents:
diff changeset
373 SH.FMC_A5.ConfNb=1
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jDG
parents:
diff changeset
374 SH.FMC_A6.0=FMC_A6,12b-sda2
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jDG
parents:
diff changeset
375 SH.FMC_A6.ConfNb=1
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jDG
parents:
diff changeset
376 SH.FMC_A7.0=FMC_A7,12b-sda2
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jDG
parents:
diff changeset
377 SH.FMC_A7.ConfNb=1
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jDG
parents:
diff changeset
378 SH.FMC_A8.0=FMC_A8,12b-sda2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
379 SH.FMC_A8.ConfNb=1
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jDG
parents:
diff changeset
380 SH.FMC_A9.0=FMC_A9,12b-sda2
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jDG
parents:
diff changeset
381 SH.FMC_A9.ConfNb=1
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jDG
parents:
diff changeset
382 SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d2
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jDG
parents:
diff changeset
383 SH.FMC_D0_DA0.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
384 SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
385 SH.FMC_D10_DA10.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
386 SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
387 SH.FMC_D11_DA11.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
388 SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
389 SH.FMC_D12_DA12.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
390 SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
391 SH.FMC_D13_DA13.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
392 SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
393 SH.FMC_D14_DA14.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
394 SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d2
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
395 SH.FMC_D15_DA15.ConfNb=1
7d1b61176708 Add chip documentations
jDG
parents:
diff changeset
396 SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d2
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397 SH.FMC_D1_DA1.ConfNb=1
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398 SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d2
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399 SH.FMC_D2_DA2.ConfNb=1
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400 SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d2
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401 SH.FMC_D3_DA3.ConfNb=1
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402 SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d2
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403 SH.FMC_D4_DA4.ConfNb=1
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404 SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d2
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405 SH.FMC_D5_DA5.ConfNb=1
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406 SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d2
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407 SH.FMC_D6_DA6.ConfNb=1
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408 SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d2
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409 SH.FMC_D7_DA7.ConfNb=1
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410 SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d2
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411 SH.FMC_D8_DA8.ConfNb=1
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412 SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d2
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413 SH.FMC_D9_DA9.ConfNb=1
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414 SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable2
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415 SH.FMC_NBL0.ConfNb=1
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416 SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable2
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417 SH.FMC_NBL1.ConfNb=1
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418 SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda2
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419 SH.FMC_SDCLK.ConfNb=1
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420 SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda2
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421 SH.FMC_SDNCAS.ConfNb=1
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422 SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda2
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423 SH.FMC_SDNRAS.ConfNb=1
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424 SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda2
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425 SH.FMC_SDNWE.ConfNb=1
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426 SPI1.CalculateBaudRate=42.0 MBits/s
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427 SPI1.IPParameters=VirtualNSS,Mode,CalculateBaudRate
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428 SPI1.Mode=SPI_MODE_MASTER
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429 SPI1.VirtualNSS=VM_NSSHARD
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430 SPI2.CalculateBaudRate=21.0 MBits/s
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431 SPI2.IPParameters=VirtualNSS,Mode,CalculateBaudRate
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432 SPI2.Mode=SPI_MODE_MASTER
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433 SPI2.VirtualNSS=VM_NSSHARD
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434 SPI3.CalculateBaudRate=21.0 MBits/s
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435 SPI3.IPParameters=VirtualNSS,Mode,CalculateBaudRate
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436 SPI3.Mode=SPI_MODE_MASTER
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437 SPI3.VirtualNSS=VM_NSSHARD
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438 SPI5.CalculateBaudRate=42.0 MBits/s
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439 SPI5.IPParameters=VirtualNSS,Mode,CalculateBaudRate
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440 SPI5.Mode=SPI_MODE_MASTER
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441 SPI5.VirtualNSS=VM_NSSHARD
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442 VP_DMA2D_VS_DMA2D.Mode=DMA2D_Activate
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443 VP_DMA2D_VS_DMA2D.Signal=DMA2D_VS_DMA2D
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444 VP_RTC_VS_RTC_Alarm_A_Intern.Mode=Alarm A
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445 VP_RTC_VS_RTC_Alarm_A_Intern.Signal=RTC_VS_RTC_Alarm_A_Intern