7
+ − 1 /**
+ − 2 ******************************************************************************
+ − 3 * @file system_stm32f4xx.c
+ − 4 * @author MCD Application Team
+ − 5 * @version V2.1.0
+ − 6 * @date 19-June-2014
+ − 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ − 8 *
+ − 9 * This file provides two functions and one global variable to be called from
+ − 10 * user application:
+ − 11 * - SystemInit(): This function is called at startup just after reset and
+ − 12 * before branch to main program. This call is made inside
+ − 13 * the "startup_stm32f4xx.s" file.
+ − 14 *
+ − 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ − 16 * by the user application to setup the SysTick
+ − 17 * timer or configure other parameters.
+ − 18 *
+ − 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ − 20 * be called whenever the core clock is changed
+ − 21 * during program execution.
+ − 22 *
+ − 23 *
+ − 24 ******************************************************************************
+ − 25 * @attention
+ − 26 *
+ − 27 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ − 28 *
+ − 29 * Redistribution and use in source and binary forms, with or without modification,
+ − 30 * are permitted provided that the following conditions are met:
+ − 31 * 1. Redistributions of source code must retain the above copyright notice,
+ − 32 * this list of conditions and the following disclaimer.
+ − 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
+ − 34 * this list of conditions and the following disclaimer in the documentation
+ − 35 * and/or other materials provided with the distribution.
+ − 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ − 37 * may be used to endorse or promote products derived from this software
+ − 38 * without specific prior written permission.
+ − 39 *
+ − 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ − 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ − 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ − 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ − 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ − 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ − 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ − 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ − 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ − 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ − 50 *
+ − 51 ******************************************************************************
+ − 52 */
+ − 53
+ − 54 /** @addtogroup CMSIS
+ − 55 * @{
+ − 56 */
+ − 57
+ − 58 /** @addtogroup stm32f4xx_system
+ − 59 * @{
+ − 60 */
+ − 61
+ − 62 /** @addtogroup STM32F4xx_System_Private_Includes
+ − 63 * @{
+ − 64 */
+ − 65
+ − 66
+ − 67 #include "stm32f4xx.h"
+ − 68
+ − 69 #if !defined (HSE_VALUE)
+ − 70 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+ − 71 #endif /* HSE_VALUE */
+ − 72
+ − 73 #if !defined (HSI_VALUE)
+ − 74 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+ − 75 #endif /* HSI_VALUE */
+ − 76
869
+ − 77
+ − 78 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
7
+ − 79 /**
+ − 80 * @}
+ − 81 */
+ − 82
+ − 83 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ − 84 * @{
+ − 85 */
+ − 86
+ − 87 /**
+ − 88 * @}
+ − 89 */
+ − 90
+ − 91 /** @addtogroup STM32F4xx_System_Private_Defines
+ − 92 * @{
+ − 93 */
+ − 94
+ − 95 /************************* Miscellaneous Configuration ************************/
+ − 96 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ − 97 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
+ − 98 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ − 99 /* #define DATA_IN_ExtSRAM */
+ − 100 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ − 101
+ − 102 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ − 103 /* #define DATA_IN_ExtSDRAM */
+ − 104 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ − 105
+ − 106 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ − 107 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
+ − 108 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+ − 109
+ − 110 /*!< Uncomment the following line if you need to relocate your vector Table in
+ − 111 Internal SRAM. */
+ − 112 /* #define VECT_TAB_SRAM */
+ − 113 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ − 114 This value must be a multiple of 0x200. */
+ − 115 /******************************************************************************/
+ − 116
+ − 117 /**
+ − 118 * @}
+ − 119 */
+ − 120
+ − 121 /** @addtogroup STM32F4xx_System_Private_Macros
+ − 122 * @{
+ − 123 */
+ − 124
+ − 125 /**
+ − 126 * @}
+ − 127 */
+ − 128
+ − 129 /** @addtogroup STM32F4xx_System_Private_Variables
+ − 130 * @{
+ − 131 */
+ − 132 /* This variable is updated in three ways:
+ − 133 1) by calling CMSIS function SystemCoreClockUpdate()
+ − 134 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ − 135 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ − 136 Note: If you use this function to configure the system clock; then there
+ − 137 is no need to call the 2 first functions listed above, since SystemCoreClock
+ − 138 variable is updated automatically.
+ − 139 */
+ − 140 uint32_t SystemCoreClock = 16000000;
+ − 141 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ − 142
+ − 143 /**
+ − 144 * @}
+ − 145 */
+ − 146
+ − 147 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ − 148 * @{
+ − 149 */
+ − 150
+ − 151 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ − 152 static void SystemInit_ExtMemCtl(void);
+ − 153 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+ − 154
+ − 155 /**
+ − 156 * @}
+ − 157 */
+ − 158
+ − 159 /** @addtogroup STM32F4xx_System_Private_Functions
+ − 160 * @{
+ − 161 */
+ − 162
+ − 163 /**
+ − 164 * @brief Setup the microcontroller system
+ − 165 * Initialize the FPU setting, vector table location and External memory
+ − 166 * configuration.
+ − 167 * @param None
+ − 168 * @retval None
+ − 169 */
+ − 170 void SystemInit(void)
+ − 171 {
+ − 172 /* FPU settings ------------------------------------------------------------*/
+ − 173 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ − 174 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ − 175 #endif
+ − 176 /* Reset the RCC clock configuration to the default reset state ------------*/
+ − 177 /* Set HSION bit */
+ − 178 RCC->CR |= (uint32_t)0x00000001;
+ − 179
+ − 180 /* Reset CFGR register */
+ − 181 RCC->CFGR = 0x00000000;
+ − 182
+ − 183 /* Reset HSEON, CSSON and PLLON bits */
+ − 184 RCC->CR &= (uint32_t)0xFEF6FFFF;
+ − 185
+ − 186 /* Reset PLLCFGR register */
+ − 187 RCC->PLLCFGR = 0x24003010;
+ − 188
+ − 189 /* Reset HSEBYP bit */
+ − 190 RCC->CR &= (uint32_t)0xFFFBFFFF;
+ − 191
+ − 192 /* Disable all interrupts */
+ − 193 RCC->CIR = 0x00000000;
+ − 194
+ − 195 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ − 196 SystemInit_ExtMemCtl();
+ − 197 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+ − 198
+ − 199 /* Configure the Vector Table location add offset address ------------------*/
+ − 200 #ifdef VECT_TAB_SRAM
+ − 201 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+ − 202 #else
+ − 203 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ − 204 #endif
+ − 205 }
+ − 206
+ − 207 /**
+ − 208 * @brief Update SystemCoreClock variable according to Clock Register Values.
+ − 209 * The SystemCoreClock variable contains the core clock (HCLK), it can
+ − 210 * be used by the user application to setup the SysTick timer or configure
+ − 211 * other parameters.
+ − 212 *
+ − 213 * @note Each time the core clock (HCLK) changes, this function must be called
+ − 214 * to update SystemCoreClock variable value. Otherwise, any configuration
+ − 215 * based on this variable will be incorrect.
+ − 216 *
+ − 217 * @note - The system frequency computed by this function is not the real
+ − 218 * frequency in the chip. It is calculated based on the predefined
+ − 219 * constant and the selected clock source:
+ − 220 *
+ − 221 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ − 222 *
+ − 223 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ − 224 *
+ − 225 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ − 226 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ − 227 *
+ − 228 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ − 229 * 16 MHz) but the real value may vary depending on the variations
+ − 230 * in voltage and temperature.
+ − 231 *
+ − 232 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ − 233 * depends on the application requirements), user has to ensure that HSE_VALUE
+ − 234 * is same as the real frequency of the crystal used. Otherwise, this function
+ − 235 * may have wrong result.
+ − 236 *
+ − 237 * - The result of this function could be not correct when using fractional
+ − 238 * value for HSE crystal.
+ − 239 *
+ − 240 * @param None
+ − 241 * @retval None
+ − 242 */
+ − 243 void SystemCoreClockUpdate(void)
+ − 244 {
+ − 245 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+ − 246
+ − 247 /* Get SYSCLK source -------------------------------------------------------*/
+ − 248 tmp = RCC->CFGR & RCC_CFGR_SWS;
+ − 249
+ − 250 switch (tmp)
+ − 251 {
+ − 252 case 0x00: /* HSI used as system clock source */
+ − 253 SystemCoreClock = HSI_VALUE;
+ − 254 break;
+ − 255 case 0x04: /* HSE used as system clock source */
+ − 256 SystemCoreClock = HSE_VALUE;
+ − 257 break;
+ − 258 case 0x08: /* PLL used as system clock source */
+ − 259
+ − 260 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ − 261 SYSCLK = PLL_VCO / PLL_P
+ − 262 */
+ − 263 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ − 264 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ − 265
+ − 266 if (pllsource != 0)
+ − 267 {
+ − 268 /* HSE used as PLL clock source */
+ − 269 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ − 270 }
+ − 271 else
+ − 272 {
+ − 273 /* HSI used as PLL clock source */
+ − 274 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ − 275 }
+ − 276
+ − 277 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ − 278 SystemCoreClock = pllvco/pllp;
+ − 279 break;
+ − 280 default:
+ − 281 SystemCoreClock = HSI_VALUE;
+ − 282 break;
+ − 283 }
+ − 284 /* Compute HCLK frequency --------------------------------------------------*/
+ − 285 /* Get HCLK prescaler */
+ − 286 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ − 287 /* HCLK frequency */
+ − 288 SystemCoreClock >>= tmp;
+ − 289 }
+ − 290
+ − 291 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ − 292 /**
+ − 293 * @brief Setup the external memory controller.
+ − 294 * Called in startup_stm32f4xx.s before jump to main.
+ − 295 * This function configures the external memories (SRAM/SDRAM)
+ − 296 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ − 297 * @param None
+ − 298 * @retval None
+ − 299 */
+ − 300 void SystemInit_ExtMemCtl(void)
+ − 301 {
+ − 302 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ − 303 #if defined (DATA_IN_ExtSDRAM)
+ − 304 register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ − 305 register uint32_t index;
+ − 306
+ − 307 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ − 308 clock */
+ − 309 RCC->AHB1ENR |= 0x000001F8;
+ − 310
+ − 311 /* Connect PDx pins to FMC Alternate function */
+ − 312 GPIOD->AFR[0] = 0x000000CC;
+ − 313 GPIOD->AFR[1] = 0xCC000CCC;
+ − 314 /* Configure PDx pins in Alternate function mode */
+ − 315 GPIOD->MODER = 0xA02A000A;
+ − 316 /* Configure PDx pins speed to 50 MHz */
+ − 317 GPIOD->OSPEEDR = 0xA02A000A;
+ − 318 /* Configure PDx pins Output type to push-pull */
+ − 319 GPIOD->OTYPER = 0x00000000;
+ − 320 /* No pull-up, pull-down for PDx pins */
+ − 321 GPIOD->PUPDR = 0x00000000;
+ − 322
+ − 323 /* Connect PEx pins to FMC Alternate function */
+ − 324 GPIOE->AFR[0] = 0xC00000CC;
+ − 325 GPIOE->AFR[1] = 0xCCCCCCCC;
+ − 326 /* Configure PEx pins in Alternate function mode */
+ − 327 GPIOE->MODER = 0xAAAA800A;
+ − 328 /* Configure PEx pins speed to 50 MHz */
+ − 329 GPIOE->OSPEEDR = 0xAAAA800A;
+ − 330 /* Configure PEx pins Output type to push-pull */
+ − 331 GPIOE->OTYPER = 0x00000000;
+ − 332 /* No pull-up, pull-down for PEx pins */
+ − 333 GPIOE->PUPDR = 0x00000000;
+ − 334
+ − 335 /* Connect PFx pins to FMC Alternate function */
+ − 336 GPIOF->AFR[0] = 0xCCCCCCCC;
+ − 337 GPIOF->AFR[1] = 0xCCCCCCCC;
+ − 338 /* Configure PFx pins in Alternate function mode */
+ − 339 GPIOF->MODER = 0xAA800AAA;
+ − 340 /* Configure PFx pins speed to 50 MHz */
+ − 341 GPIOF->OSPEEDR = 0xAA800AAA;
+ − 342 /* Configure PFx pins Output type to push-pull */
+ − 343 GPIOF->OTYPER = 0x00000000;
+ − 344 /* No pull-up, pull-down for PFx pins */
+ − 345 GPIOF->PUPDR = 0x00000000;
+ − 346
+ − 347 /* Connect PGx pins to FMC Alternate function */
+ − 348 GPIOG->AFR[0] = 0xCCCCCCCC;
+ − 349 GPIOG->AFR[1] = 0xCCCCCCCC;
+ − 350 /* Configure PGx pins in Alternate function mode */
+ − 351 GPIOG->MODER = 0xAAAAAAAA;
+ − 352 /* Configure PGx pins speed to 50 MHz */
+ − 353 GPIOG->OSPEEDR = 0xAAAAAAAA;
+ − 354 /* Configure PGx pins Output type to push-pull */
+ − 355 GPIOG->OTYPER = 0x00000000;
+ − 356 /* No pull-up, pull-down for PGx pins */
+ − 357 GPIOG->PUPDR = 0x00000000;
+ − 358
+ − 359 /* Connect PHx pins to FMC Alternate function */
+ − 360 GPIOH->AFR[0] = 0x00C0CC00;
+ − 361 GPIOH->AFR[1] = 0xCCCCCCCC;
+ − 362 /* Configure PHx pins in Alternate function mode */
+ − 363 GPIOH->MODER = 0xAAAA08A0;
+ − 364 /* Configure PHx pins speed to 50 MHz */
+ − 365 GPIOH->OSPEEDR = 0xAAAA08A0;
+ − 366 /* Configure PHx pins Output type to push-pull */
+ − 367 GPIOH->OTYPER = 0x00000000;
+ − 368 /* No pull-up, pull-down for PHx pins */
+ − 369 GPIOH->PUPDR = 0x00000000;
+ − 370
+ − 371 /* Connect PIx pins to FMC Alternate function */
+ − 372 GPIOI->AFR[0] = 0xCCCCCCCC;
+ − 373 GPIOI->AFR[1] = 0x00000CC0;
+ − 374 /* Configure PIx pins in Alternate function mode */
+ − 375 GPIOI->MODER = 0x0028AAAA;
+ − 376 /* Configure PIx pins speed to 50 MHz */
+ − 377 GPIOI->OSPEEDR = 0x0028AAAA;
+ − 378 /* Configure PIx pins Output type to push-pull */
+ − 379 GPIOI->OTYPER = 0x00000000;
+ − 380 /* No pull-up, pull-down for PIx pins */
+ − 381 GPIOI->PUPDR = 0x00000000;
+ − 382
+ − 383 /*-- FMC Configuration ------------------------------------------------------*/
+ − 384 /* Enable the FMC interface clock */
+ − 385 RCC->AHB3ENR |= 0x00000001;
+ − 386
+ − 387 /* Configure and enable SDRAM bank1 */
+ − 388 FMC_Bank5_6->SDCR[0] = 0x000019E0;
+ − 389 FMC_Bank5_6->SDTR[0] = 0x01115351;
+ − 390
+ − 391 /* SDRAM initialization sequence */
+ − 392 /* Clock enable command */
+ − 393 FMC_Bank5_6->SDCMR = 0x00000011;
+ − 394 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ − 395 while((tmpreg != 0) && (timeout-- > 0))
+ − 396 {
+ − 397 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ − 398 }
+ − 399
+ − 400 /* Delay */
+ − 401 for (index = 0; index<1000; index++);
+ − 402
+ − 403 /* PALL command */
+ − 404 FMC_Bank5_6->SDCMR = 0x00000012;
+ − 405 timeout = 0xFFFF;
+ − 406 while((tmpreg != 0) && (timeout-- > 0))
+ − 407 {
+ − 408 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ − 409 }
+ − 410
+ − 411 /* Auto refresh command */
+ − 412 FMC_Bank5_6->SDCMR = 0x00000073;
+ − 413 timeout = 0xFFFF;
+ − 414 while((tmpreg != 0) && (timeout-- > 0))
+ − 415 {
+ − 416 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ − 417 }
+ − 418
+ − 419 /* MRD register program */
+ − 420 FMC_Bank5_6->SDCMR = 0x00046014;
+ − 421 timeout = 0xFFFF;
+ − 422 while((tmpreg != 0) && (timeout-- > 0))
+ − 423 {
+ − 424 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ − 425 }
+ − 426
+ − 427 /* Set refresh count */
+ − 428 tmpreg = FMC_Bank5_6->SDRTR;
+ − 429 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+ − 430
+ − 431 /* Disable write protection */
+ − 432 tmpreg = FMC_Bank5_6->SDCR[0];
+ − 433 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+ − 434 #endif /* DATA_IN_ExtSDRAM */
+ − 435 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ − 436
+ − 437 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ − 438 #if defined(DATA_IN_ExtSRAM)
+ − 439 /*-- GPIOs Configuration -----------------------------------------------------*/
+ − 440 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ − 441 RCC->AHB1ENR |= 0x00000078;
+ − 442
+ − 443 /* Connect PDx pins to FMC Alternate function */
+ − 444 GPIOD->AFR[0] = 0x00CCC0CC;
+ − 445 GPIOD->AFR[1] = 0xCCCCCCCC;
+ − 446 /* Configure PDx pins in Alternate function mode */
+ − 447 GPIOD->MODER = 0xAAAA0A8A;
+ − 448 /* Configure PDx pins speed to 100 MHz */
+ − 449 GPIOD->OSPEEDR = 0xFFFF0FCF;
+ − 450 /* Configure PDx pins Output type to push-pull */
+ − 451 GPIOD->OTYPER = 0x00000000;
+ − 452 /* No pull-up, pull-down for PDx pins */
+ − 453 GPIOD->PUPDR = 0x00000000;
+ − 454
+ − 455 /* Connect PEx pins to FMC Alternate function */
+ − 456 GPIOE->AFR[0] = 0xC00CC0CC;
+ − 457 GPIOE->AFR[1] = 0xCCCCCCCC;
+ − 458 /* Configure PEx pins in Alternate function mode */
+ − 459 GPIOE->MODER = 0xAAAA828A;
+ − 460 /* Configure PEx pins speed to 100 MHz */
+ − 461 GPIOE->OSPEEDR = 0xFFFFC3CF;
+ − 462 /* Configure PEx pins Output type to push-pull */
+ − 463 GPIOE->OTYPER = 0x00000000;
+ − 464 /* No pull-up, pull-down for PEx pins */
+ − 465 GPIOE->PUPDR = 0x00000000;
+ − 466
+ − 467 /* Connect PFx pins to FMC Alternate function */
+ − 468 GPIOF->AFR[0] = 0x00CCCCCC;
+ − 469 GPIOF->AFR[1] = 0xCCCC0000;
+ − 470 /* Configure PFx pins in Alternate function mode */
+ − 471 GPIOF->MODER = 0xAA000AAA;
+ − 472 /* Configure PFx pins speed to 100 MHz */
+ − 473 GPIOF->OSPEEDR = 0xFF000FFF;
+ − 474 /* Configure PFx pins Output type to push-pull */
+ − 475 GPIOF->OTYPER = 0x00000000;
+ − 476 /* No pull-up, pull-down for PFx pins */
+ − 477 GPIOF->PUPDR = 0x00000000;
+ − 478
+ − 479 /* Connect PGx pins to FMC Alternate function */
+ − 480 GPIOG->AFR[0] = 0x00CCCCCC;
+ − 481 GPIOG->AFR[1] = 0x000000C0;
+ − 482 /* Configure PGx pins in Alternate function mode */
+ − 483 GPIOG->MODER = 0x00085AAA;
+ − 484 /* Configure PGx pins speed to 100 MHz */
+ − 485 GPIOG->OSPEEDR = 0x000CAFFF;
+ − 486 /* Configure PGx pins Output type to push-pull */
+ − 487 GPIOG->OTYPER = 0x00000000;
+ − 488 /* No pull-up, pull-down for PGx pins */
+ − 489 GPIOG->PUPDR = 0x00000000;
+ − 490
+ − 491 /*-- FMC/FSMC Configuration --------------------------------------------------*/
+ − 492 /* Enable the FMC/FSMC interface clock */
+ − 493 RCC->AHB3ENR |= 0x00000001;
+ − 494
+ − 495 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ − 496 /* Configure and enable Bank1_SRAM2 */
+ − 497 FMC_Bank1->BTCR[2] = 0x00001011;
+ − 498 FMC_Bank1->BTCR[3] = 0x00000201;
+ − 499 FMC_Bank1E->BWTR[2] = 0x0fffffff;
+ − 500 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ − 501
+ − 502 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ − 503 /* Configure and enable Bank1_SRAM2 */
+ − 504 FSMC_Bank1->BTCR[2] = 0x00001011;
+ − 505 FSMC_Bank1->BTCR[3] = 0x00000201;
+ − 506 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+ − 507 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+ − 508
+ − 509 #endif /* DATA_IN_ExtSRAM */
+ − 510 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+ − 511 }
+ − 512 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+ − 513 /**
+ − 514 * @}
+ − 515 */
+ − 516
+ − 517 /**
+ − 518 * @}
+ − 519 */
+ − 520
+ − 521 /**
+ − 522 * @}
+ − 523 */
+ − 524 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/