annotate Common/Drivers/STM32F4xx_v220/Include/stm32f401xc.h @ 111:38785aa95837 FlipDisplay

Added new nvm parameter"FlipDisplay" indicating the screen orientation
author Ideenmodellierer
date Tue, 01 Jan 2019 21:03:10 +0100
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children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f401xc.h
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4 * @author MCD Application Team
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5 * @version V2.2.0
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6 * @date 15-December-2014
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7 * @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
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8 *
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9 * This file contains:
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10 * - Data structures and the address mapping for all peripherals
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11 * - Peripheral's registers declarations and bits definition
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12 * - Macros to access peripheral’s registers hardware
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13 *
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14 ******************************************************************************
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15 * @attention
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16 *
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17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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18 *
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19 * Redistribution and use in source and binary forms, with or without modification,
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20 * are permitted provided that the following conditions are met:
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21 * 1. Redistributions of source code must retain the above copyright notice,
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22 * this list of conditions and the following disclaimer.
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23 * 2. Redistributions in binary form must reproduce the above copyright notice,
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24 * this list of conditions and the following disclaimer in the documentation
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25 * and/or other materials provided with the distribution.
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26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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27 * may be used to endorse or promote products derived from this software
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28 * without specific prior written permission.
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29 *
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30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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40 *
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41 ******************************************************************************
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42 */
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43
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44 /** @addtogroup CMSIS
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45 * @{
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46 */
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47
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48 /** @addtogroup stm32f401xc
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49 * @{
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50 */
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51
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52 #ifndef __STM32F401xC_H
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53 #define __STM32F401xC_H
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54
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55 #ifdef __cplusplus
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56 extern "C" {
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57 #endif /* __cplusplus */
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58
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59
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60 /** @addtogroup Configuration_section_for_CMSIS
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61 * @{
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62 */
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63
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64 /**
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65 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
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66 */
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67 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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68 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
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69 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
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70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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71 #define __FPU_PRESENT 1 /*!< FPU present */
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72
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73 /**
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74 * @}
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75 */
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76
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77 /** @addtogroup Peripheral_interrupt_number_definition
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78 * @{
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79 */
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80
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81 /**
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82 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
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83 * in @ref Library_configuration_section
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84 */
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85 typedef enum
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86 {
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87 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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89 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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90 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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91 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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92 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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93 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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94 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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95 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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96 /****** STM32 specific Interrupt Numbers **********************************************************************/
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97 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
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98 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
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99 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
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100 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
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101 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
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102 RCC_IRQn = 5, /*!< RCC global Interrupt */
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103 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
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104 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
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105 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
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106 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
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107 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
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108 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
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109 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
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110 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
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111 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
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112 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
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113 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
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114 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
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115 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
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116 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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117 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
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118 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
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119 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
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120 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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121 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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122 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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123 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
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124 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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125 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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126 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
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127 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
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128 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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129 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
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130 USART1_IRQn = 37, /*!< USART1 global Interrupt */
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131 USART2_IRQn = 38, /*!< USART2 global Interrupt */
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132 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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133 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
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134 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
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135 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
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136 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
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137 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
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138 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
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139 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
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140 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
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141 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
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142 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
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143 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
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144 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
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145 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
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146 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
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147 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
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148 USART6_IRQn = 71, /*!< USART6 global interrupt */
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149 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
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150 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
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151 FPU_IRQn = 81, /*!< FPU global interrupt */
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152 SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
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153 } IRQn_Type;
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154
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155 /**
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156 * @}
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157 */
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158
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159 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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160 #include "system_stm32f4xx.h"
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161 #include <stdint.h>
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162
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163 /** @addtogroup Peripheral_registers_structures
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164 * @{
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165 */
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166
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167 /**
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168 * @brief Analog to Digital Converter
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169 */
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170
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171 typedef struct
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172 {
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173 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
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174 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
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175 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
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176 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
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177 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
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178 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
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179 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
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180 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
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181 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
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182 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
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183 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
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184 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
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185 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
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186 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
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187 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
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188 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
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189 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
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190 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
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191 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
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192 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
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193 } ADC_TypeDef;
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194
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195 typedef struct
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196 {
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197 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
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198 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
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199 __IO uint32_t CDR; /*!< ADC common regular data register for dual
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200 AND triple modes, Address offset: ADC1 base address + 0x308 */
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201 } ADC_Common_TypeDef;
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202
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203 /**
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204 * @brief CRC calculation unit
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205 */
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206
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207 typedef struct
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208 {
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209 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
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210 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
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211 uint8_t RESERVED0; /*!< Reserved, 0x05 */
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212 uint16_t RESERVED1; /*!< Reserved, 0x06 */
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213 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
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214 } CRC_TypeDef;
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215
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216 /**
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217 * @brief Debug MCU
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218 */
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219
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220 typedef struct
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221 {
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222 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
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223 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
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224 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
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225 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
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226 }DBGMCU_TypeDef;
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227
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228
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229 /**
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230 * @brief DMA Controller
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231 */
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232
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233 typedef struct
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234 {
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235 __IO uint32_t CR; /*!< DMA stream x configuration register */
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236 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
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237 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
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238 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
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239 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
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240 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
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241 } DMA_Stream_TypeDef;
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242
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243 typedef struct
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244 {
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245 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
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246 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
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247 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
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248 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
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249 } DMA_TypeDef;
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250
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251
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252 /**
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253 * @brief External Interrupt/Event Controller
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254 */
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255
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256 typedef struct
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257 {
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258 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
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259 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
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260 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
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261 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
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262 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
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263 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
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264 } EXTI_TypeDef;
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265
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266 /**
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267 * @brief FLASH Registers
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268 */
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269
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270 typedef struct
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271 {
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272 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
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273 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
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274 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
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275 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
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276 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
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277 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
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278 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
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279 } FLASH_TypeDef;
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280
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281 /**
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282 * @brief General Purpose I/O
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283 */
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284
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285 typedef struct
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286 {
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287 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
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288 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
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289 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
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290 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
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291 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
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292 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
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293 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
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294 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
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295 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
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296 } GPIO_TypeDef;
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297
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298 /**
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299 * @brief System configuration controller
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300 */
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301
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302 typedef struct
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303 {
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304 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
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305 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
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306 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
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307 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
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308 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
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309 } SYSCFG_TypeDef;
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310
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311 /**
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312 * @brief Inter-integrated Circuit Interface
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313 */
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314
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315 typedef struct
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316 {
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317 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
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318 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
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319 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
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320 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
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321 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
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322 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
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323 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
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324 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
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325 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
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326 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
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327 } I2C_TypeDef;
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328
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329 /**
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330 * @brief Independent WATCHDOG
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331 */
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332
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333 typedef struct
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334 {
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335 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
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336 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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337 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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338 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
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339 } IWDG_TypeDef;
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340
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341 /**
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342 * @brief Power Control
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343 */
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344
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345 typedef struct
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346 {
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347 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
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348 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
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349 } PWR_TypeDef;
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350
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351 /**
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352 * @brief Reset and Clock Control
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353 */
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354
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355 typedef struct
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356 {
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357 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
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358 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
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359 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
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360 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
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361 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
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362 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
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363 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
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364 uint32_t RESERVED0; /*!< Reserved, 0x1C */
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365 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
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366 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
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367 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
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368 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
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369 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
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370 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
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371 uint32_t RESERVED2; /*!< Reserved, 0x3C */
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372 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
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373 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
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374 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
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375 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
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376 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
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377 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
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378 uint32_t RESERVED4; /*!< Reserved, 0x5C */
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379 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
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380 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
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381 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
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382 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
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383 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
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384 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
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385 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
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386 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
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387
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388 } RCC_TypeDef;
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389
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390 /**
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391 * @brief Real-Time Clock
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392 */
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393
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394 typedef struct
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395 {
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396 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
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397 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
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398 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
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399 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
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400 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
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401 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
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402 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
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403 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
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404 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
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405 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
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406 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
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407 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
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408 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
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409 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
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410 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
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411 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
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412 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
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413 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
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414 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
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415 uint32_t RESERVED7; /*!< Reserved, 0x4C */
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416 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
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417 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
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418 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
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419 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
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420 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
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421 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
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422 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
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423 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
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424 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
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425 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
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426 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
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427 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
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428 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
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429 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
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430 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
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431 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
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432 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
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433 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
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434 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
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435 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
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436 } RTC_TypeDef;
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437
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438
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439 /**
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440 * @brief SD host Interface
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441 */
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442
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443 typedef struct
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444 {
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445 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
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446 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
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447 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
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448 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
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449 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
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450 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
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451 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
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452 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
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453 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
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454 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
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455 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
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456 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
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457 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
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458 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
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459 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
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460 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
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461 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
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462 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
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463 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
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464 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
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465 } SDIO_TypeDef;
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466
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467 /**
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468 * @brief Serial Peripheral Interface
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469 */
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470
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471 typedef struct
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472 {
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473 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
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474 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
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475 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
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476 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
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477 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
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478 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
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479 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
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480 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
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481 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
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482 } SPI_TypeDef;
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483
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484 /**
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485 * @brief TIM
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486 */
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487
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488 typedef struct
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489 {
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490 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
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491 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
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492 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
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493 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
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494 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
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495 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
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496 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
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497 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
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498 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
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499 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
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500 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
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501 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
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502 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
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503 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
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504 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
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505 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
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506 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
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507 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
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508 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
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509 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
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510 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
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511 } TIM_TypeDef;
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512
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513 /**
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514 * @brief Universal Synchronous Asynchronous Receiver Transmitter
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515 */
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516
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517 typedef struct
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518 {
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519 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
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520 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
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521 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
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522 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
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523 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
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524 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
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525 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
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526 } USART_TypeDef;
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527
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528 /**
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529 * @brief Window WATCHDOG
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530 */
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531
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532 typedef struct
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533 {
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534 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
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535 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
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536 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
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537 } WWDG_TypeDef;
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538
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539 /**
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540 * @brief __USB_OTG_Core_register
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541 */
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542 typedef struct
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543 {
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544 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset : 0x00 */
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545 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset : 0x04 */
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546 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset : 0x08 */
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547 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset : 0x0C */
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548 __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset : 0x10 */
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549 __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset : 0x14 */
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550 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset : 0x18 */
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551 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset : 0x1C */
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552 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset : 0x20 */
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553 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register Address offset : 0x24 */
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554 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset : 0x28 */
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555 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset : 0x2C */
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556 uint32_t Reserved30[2]; /* Reserved Address offset : 0x30 */
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557 __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset : 0x38 */
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558 __IO uint32_t CID; /*!< User ID Register Address offset : 0x3C */
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559 uint32_t Reserved40[48]; /*!< Reserved Address offset : 0x40-0xFF */
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560 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset : 0x100 */
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561 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
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562 }
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563 USB_OTG_GlobalTypeDef;
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564
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565
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566
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567 /**
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568 * @brief __device_Registers
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569 */
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570 typedef struct
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571 {
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572 __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */
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573 __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */
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574 __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset : 0x808 */
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575 uint32_t Reserved0C; /*!< Reserved Address offset : 0x80C */
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576 __IO uint32_t DIEPMSK; /* !< dev IN Endpoint Mask Address offset : 0x810 */
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577 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset : 0x814 */
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578 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset : 0x818 */
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579 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset : 0x81C */
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580 uint32_t Reserved20; /*!< Reserved Address offset : 0x820 */
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581 uint32_t Reserved9; /*!< Reserved Address offset : 0x824 */
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582 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset : 0x828 */
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583 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset : 0x82C */
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584 __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */
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585 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */
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586 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */
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587 __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */
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588 uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */
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589 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */
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590 uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */
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591 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */
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592 }
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593 USB_OTG_DeviceTypeDef;
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594
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595
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596 /**
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597 * @brief __IN_Endpoint-Specific_Register
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598 */
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599 typedef struct
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600 {
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601 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
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602 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */
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603 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
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604 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch */
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605 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
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606 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
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607 __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
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608 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
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609 }
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610 USB_OTG_INEndpointTypeDef;
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611
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612
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613 /**
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614 * @brief __OUT_Endpoint-Specific_Registers
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615 */
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616 typedef struct
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617 {
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618 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
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619 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
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620 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
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621 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
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622 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
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623 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
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624 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
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625 }
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626 USB_OTG_OUTEndpointTypeDef;
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627
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628
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629 /**
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630 * @brief __Host_Mode_Register_Structures
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631 */
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632 typedef struct
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633 {
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634 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
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635 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
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636 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
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637 uint32_t Reserved40C; /* Reserved 40Ch*/
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638 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
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639 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
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640 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
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641 }
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642 USB_OTG_HostTypeDef;
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643
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644
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645 /**
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646 * @brief __Host_Channel_Specific_Registers
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647 */
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648 typedef struct
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649 {
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650 __IO uint32_t HCCHAR;
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651 __IO uint32_t HCSPLT;
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652 __IO uint32_t HCINT;
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653 __IO uint32_t HCINTMSK;
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654 __IO uint32_t HCTSIZ;
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655 __IO uint32_t HCDMA;
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656 uint32_t Reserved[2];
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657 }
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658 USB_OTG_HostChannelTypeDef;
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659
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660
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661 /**
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662 * @brief Peripheral_memory_map
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663 */
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664 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
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665 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
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666 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
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667 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
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668 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
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669 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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670 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
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671 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
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672 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
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673 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
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674 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
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675 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
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676 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
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677 #define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
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678
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679 /* Legacy defines */
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680 #define SRAM_BASE SRAM1_BASE
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681 #define SRAM_BB_BASE SRAM1_BB_BASE
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682
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683
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684 /*!< Peripheral memory map */
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685 #define APB1PERIPH_BASE PERIPH_BASE
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686 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
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687 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
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688 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
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689
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690 /*!< APB1 peripherals */
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691 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
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692 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
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693 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
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694 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
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695 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
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696 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
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697 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
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698 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
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699 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
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700 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
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701 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
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702 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
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703 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
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704 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
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705 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
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706 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
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707
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708 /*!< APB2 peripherals */
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709 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
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710 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
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711 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
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712 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
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713 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
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714 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
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715 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
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716 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
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717 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
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718 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
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719 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
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720 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
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721 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
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722
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723 /*!< AHB1 peripherals */
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724 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
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725 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
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726 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
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727 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
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728 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
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729 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
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730 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
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731 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
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732 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
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733 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
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734 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
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735 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
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736 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
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737 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
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738 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
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739 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
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740 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
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741 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
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742 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
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743 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
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744 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
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745 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
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746 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
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747 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
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748 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
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749 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
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750 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
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751
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752 /* Debug MCU registers base address */
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753 #define DBGMCU_BASE ((uint32_t )0xE0042000)
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754
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755 /*!< USB registers base address */
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756 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
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757
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758 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
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759 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
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760 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
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761 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
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762 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
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763 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
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764 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
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765 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
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766 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
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767 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
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768 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
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769 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
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770
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771 /**
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772 * @}
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773 */
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774
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775 /** @addtogroup Peripheral_declaration
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776 * @{
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777 */
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778 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
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779 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
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780 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
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781 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
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782 #define RTC ((RTC_TypeDef *) RTC_BASE)
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783 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
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784 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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785 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
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786 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
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787 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
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788 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
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789 #define USART2 ((USART_TypeDef *) USART2_BASE)
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790 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
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791 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
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792 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
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793 #define PWR ((PWR_TypeDef *) PWR_BASE)
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794 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
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795 #define USART1 ((USART_TypeDef *) USART1_BASE)
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796 #define USART6 ((USART_TypeDef *) USART6_BASE)
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797 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
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798 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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799 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
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800 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
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801 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
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802 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
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803 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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804 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
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805 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
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806 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
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807 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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808 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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809 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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810 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
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811 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
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812 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
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813 #define CRC ((CRC_TypeDef *) CRC_BASE)
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814 #define RCC ((RCC_TypeDef *) RCC_BASE)
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815 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
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816 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
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817 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
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818 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
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819 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
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820 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
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821 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
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822 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
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823 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
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824 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
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825 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
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826 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
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827 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
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828 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
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829 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
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830 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
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831 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
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832 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
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833 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
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834
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835 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
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836
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837 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
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838
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839 /**
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840 * @}
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841 */
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842
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843 /** @addtogroup Exported_constants
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844 * @{
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845 */
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846
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847 /** @addtogroup Peripheral_Registers_Bits_Definition
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848 * @{
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849 */
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850
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851 /******************************************************************************/
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852 /* Peripheral Registers_Bits_Definition */
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853 /******************************************************************************/
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854
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855 /******************************************************************************/
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856 /* */
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857 /* Analog to Digital Converter */
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858 /* */
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859 /******************************************************************************/
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860 /******************** Bit definition for ADC_SR register ********************/
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861 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
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862 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
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863 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
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864 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
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865 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
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866 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
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867
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868 /******************* Bit definition for ADC_CR1 register ********************/
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869 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
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870 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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871 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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872 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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873 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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874 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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875 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
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876 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
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877 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
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878 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
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879 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
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880 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
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881 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
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882 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
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883 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
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884 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
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885 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
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886 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
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887 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
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888 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
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889 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
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890 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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891 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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892 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
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893
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894 /******************* Bit definition for ADC_CR2 register ********************/
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895 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
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896 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
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897 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
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898 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
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899 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
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900 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
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901 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
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902 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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903 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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904 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
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905 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
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906 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
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907 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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908 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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909 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
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910 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
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911 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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912 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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913 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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914 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
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915 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
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916 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
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917 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
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918 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
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919
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920 /****************** Bit definition for ADC_SMPR1 register *******************/
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921 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
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922 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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923 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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924 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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925 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
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926 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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927 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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928 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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929 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
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930 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
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931 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
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932 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
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933 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
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934 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
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935 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
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936 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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937 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
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938 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
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939 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
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940 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
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941 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
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942 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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943 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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diff changeset
944 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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diff changeset
945 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
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diff changeset
946 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
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diff changeset
947 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
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parents:
diff changeset
948 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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diff changeset
949 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
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diff changeset
950 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
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diff changeset
951 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
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diff changeset
952 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
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diff changeset
953 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
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diff changeset
954 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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diff changeset
955 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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diff changeset
956 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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957
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diff changeset
958 /****************** Bit definition for ADC_SMPR2 register *******************/
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diff changeset
959 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
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960 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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diff changeset
961 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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diff changeset
962 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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diff changeset
963 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
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diff changeset
964 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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diff changeset
965 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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diff changeset
966 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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967 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
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diff changeset
968 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
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969 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
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970 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
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971 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
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972 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
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973 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
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974 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
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975 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
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976 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
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diff changeset
977 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
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978 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
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diff changeset
979 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
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980 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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981 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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982 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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983 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
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984 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
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diff changeset
985 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
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986 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
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987 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
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988 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
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989 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
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990 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
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991 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
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992 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
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993 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
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994 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
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995 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
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996 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
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997 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
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998 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
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999
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diff changeset
1000 /****************** Bit definition for ADC_JOFR1 register *******************/
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1001 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
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1002
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1003 /****************** Bit definition for ADC_JOFR2 register *******************/
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1004 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
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1005
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1006 /****************** Bit definition for ADC_JOFR3 register *******************/
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diff changeset
1007 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
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1008
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1009 /****************** Bit definition for ADC_JOFR4 register *******************/
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1010 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
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1011
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diff changeset
1012 /******************* Bit definition for ADC_HTR register ********************/
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1013 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
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1014
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1015 /******************* Bit definition for ADC_LTR register ********************/
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1016 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
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1017
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1018 /******************* Bit definition for ADC_SQR1 register *******************/
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1019 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
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1020 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1021 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1022 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1023 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1024 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1025 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
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1026 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1027 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1028 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1029 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1030 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1031 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
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1032 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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1033 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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1034 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1035 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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1036 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1037 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
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1038 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1039 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1040 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1041 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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1042 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1043 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
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1044 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1045 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1046 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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1047 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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1048
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1049 /******************* Bit definition for ADC_SQR2 register *******************/
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1050 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
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1051 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1052 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1053 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1054 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1055 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1056 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
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1057 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1058 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1059 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1060 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1061 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1062 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
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1063 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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1064 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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1065 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1066 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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1067 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1068 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
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1069 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1070 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1071 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1072 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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1073 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1074 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
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1075 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1076 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1077 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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1078 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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1079 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
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1080 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
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1081 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
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1082 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
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1083 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
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1084 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
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1085 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
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1086
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1087 /******************* Bit definition for ADC_SQR3 register *******************/
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1088 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
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1089 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1090 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1091 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1092 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1093 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1094 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
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1095 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1096 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1097 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1098 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1099 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1100 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
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1101 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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1102 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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1103 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1104 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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1105 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1106 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
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1107 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1108 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1109 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1110 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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1111 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1112 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
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1113 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1114 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1115 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
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1116 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
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1117 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
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1118 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
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1119 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
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1120 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
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1121 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
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1122 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
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1123 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
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1124
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1125 /******************* Bit definition for ADC_JSQR register *******************/
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1126 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
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1127 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1128 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1129 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1130 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1131 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1132 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
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1133 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
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1134 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
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1135 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
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1136 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
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1137 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
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1138 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
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1139 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
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1140 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
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1141 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
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1142 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
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1143 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
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1144 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
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1145 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
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1146 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
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1147 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
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1148 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
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1149 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
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1150 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
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1151 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
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1152 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
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1153
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1154 /******************* Bit definition for ADC_JDR1 register *******************/
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1155 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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1156
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1157 /******************* Bit definition for ADC_JDR2 register *******************/
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1158 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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1159
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1160 /******************* Bit definition for ADC_JDR3 register *******************/
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1161 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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1162
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1163 /******************* Bit definition for ADC_JDR4 register *******************/
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1164 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
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1165
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1166 /******************** Bit definition for ADC_DR register ********************/
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1167 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
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1168 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
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1169
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1170 /******************* Bit definition for ADC_CSR register ********************/
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1171 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
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1172 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
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1173 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
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1174 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
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1175 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
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1176 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
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1177 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
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1178 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
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1179 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
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1180 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
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1181 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
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1182 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
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1183 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
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1184 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
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1185 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
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1186 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
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1187 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
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1188 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
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1189
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1190 /******************* Bit definition for ADC_CCR register ********************/
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1191 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
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1192 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1193 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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1194 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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1195 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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1196 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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1197 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
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1198 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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1199 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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1200 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
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diff changeset
1201 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1202 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
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heinrichsweikamp
parents:
diff changeset
1203 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
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heinrichsweikamp
parents:
diff changeset
1204 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1205 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
1206 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
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heinrichsweikamp
parents:
diff changeset
1207 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
1208 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
1209 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
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heinrichsweikamp
parents:
diff changeset
1210 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
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heinrichsweikamp
parents:
diff changeset
1211
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heinrichsweikamp
parents:
diff changeset
1212 /******************* Bit definition for ADC_CDR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1213 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
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heinrichsweikamp
parents:
diff changeset
1214 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1215
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heinrichsweikamp
parents:
diff changeset
1216 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1217 /* */
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heinrichsweikamp
parents:
diff changeset
1218 /* CRC calculation unit */
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heinrichsweikamp
parents:
diff changeset
1219 /* */
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heinrichsweikamp
parents:
diff changeset
1220 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1221 /******************* Bit definition for CRC_DR register *********************/
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heinrichsweikamp
parents:
diff changeset
1222 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
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heinrichsweikamp
parents:
diff changeset
1223
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heinrichsweikamp
parents:
diff changeset
1224
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1225 /******************* Bit definition for CRC_IDR register ********************/
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heinrichsweikamp
parents:
diff changeset
1226 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
1227
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heinrichsweikamp
parents:
diff changeset
1228
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heinrichsweikamp
parents:
diff changeset
1229 /******************** Bit definition for CRC_CR register ********************/
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heinrichsweikamp
parents:
diff changeset
1230 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
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parents:
diff changeset
1231
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heinrichsweikamp
parents:
diff changeset
1232 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1233 /* */
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heinrichsweikamp
parents:
diff changeset
1234 /* Debug MCU */
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heinrichsweikamp
parents:
diff changeset
1235 /* */
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heinrichsweikamp
parents:
diff changeset
1236 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1237
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heinrichsweikamp
parents:
diff changeset
1238 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1239 /* */
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heinrichsweikamp
parents:
diff changeset
1240 /* DMA Controller */
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heinrichsweikamp
parents:
diff changeset
1241 /* */
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heinrichsweikamp
parents:
diff changeset
1242 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
1243 /******************** Bits definition for DMA_SxCR register *****************/
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heinrichsweikamp
parents:
diff changeset
1244 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
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heinrichsweikamp
parents:
diff changeset
1245 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
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parents:
diff changeset
1246 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
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heinrichsweikamp
parents:
diff changeset
1247 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
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heinrichsweikamp
parents:
diff changeset
1248 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
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heinrichsweikamp
parents:
diff changeset
1249 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
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parents:
diff changeset
1250 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
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parents:
diff changeset
1251 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
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parents:
diff changeset
1252 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
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heinrichsweikamp
parents:
diff changeset
1253 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
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parents:
diff changeset
1254 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
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diff changeset
1255 #define DMA_SxCR_CT ((uint32_t)0x00080000)
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parents:
diff changeset
1256 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
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parents:
diff changeset
1257 #define DMA_SxCR_PL ((uint32_t)0x00030000)
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parents:
diff changeset
1258 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
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parents:
diff changeset
1259 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
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parents:
diff changeset
1260 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
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parents:
diff changeset
1261 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
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parents:
diff changeset
1262 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
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parents:
diff changeset
1263 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
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parents:
diff changeset
1264 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
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parents:
diff changeset
1265 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
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parents:
diff changeset
1266 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
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diff changeset
1267 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
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parents:
diff changeset
1268 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
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parents:
diff changeset
1269 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
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diff changeset
1270 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
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diff changeset
1271 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
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diff changeset
1272 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
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diff changeset
1273 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
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diff changeset
1274 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
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parents:
diff changeset
1275 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
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diff changeset
1276 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
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parents:
diff changeset
1277 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
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parents:
diff changeset
1278 #define DMA_SxCR_EN ((uint32_t)0x00000001)
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diff changeset
1279
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parents:
diff changeset
1280 /******************** Bits definition for DMA_SxCNDTR register **************/
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parents:
diff changeset
1281 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
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parents:
diff changeset
1282 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
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parents:
diff changeset
1283 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
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parents:
diff changeset
1284 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
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diff changeset
1285 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
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parents:
diff changeset
1286 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
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diff changeset
1287 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
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parents:
diff changeset
1288 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
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parents:
diff changeset
1289 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
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parents:
diff changeset
1290 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
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parents:
diff changeset
1291 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
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parents:
diff changeset
1292 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
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diff changeset
1293 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
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diff changeset
1294 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
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parents:
diff changeset
1295 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
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diff changeset
1296 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
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diff changeset
1297 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
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diff changeset
1298
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parents:
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1299 /******************** Bits definition for DMA_SxFCR register ****************/
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diff changeset
1300 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
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1301 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
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1302 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
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1303 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
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diff changeset
1304 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
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diff changeset
1305 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
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diff changeset
1306 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
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diff changeset
1307 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
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diff changeset
1308 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
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diff changeset
1309
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parents:
diff changeset
1310 /******************** Bits definition for DMA_LISR register *****************/
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1311 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
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1312 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
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1313 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
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diff changeset
1314 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
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1315 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
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1316 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
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diff changeset
1317 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
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diff changeset
1318 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
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diff changeset
1319 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
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diff changeset
1320 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
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1321 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
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1322 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
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diff changeset
1323 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
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1324 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
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diff changeset
1325 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
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1326 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
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1327 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
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1328 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
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1329 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
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diff changeset
1330 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
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1331
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diff changeset
1332 /******************** Bits definition for DMA_HISR register *****************/
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1333 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
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1334 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
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1335 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
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1336 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
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1337 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
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1338 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
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1339 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
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1340 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
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1341 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
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1342 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
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1343 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
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1344 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
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1345 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
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1346 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
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1347 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
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diff changeset
1348 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
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diff changeset
1349 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
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diff changeset
1350 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
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diff changeset
1351 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
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diff changeset
1352 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
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diff changeset
1353
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parents:
diff changeset
1354 /******************** Bits definition for DMA_LIFCR register ****************/
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diff changeset
1355 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
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diff changeset
1356 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
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diff changeset
1357 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
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diff changeset
1358 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
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diff changeset
1359 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
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diff changeset
1360 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
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diff changeset
1361 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
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diff changeset
1362 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
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diff changeset
1363 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
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diff changeset
1364 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
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diff changeset
1365 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
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diff changeset
1366 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
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diff changeset
1367 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
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diff changeset
1368 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
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diff changeset
1369 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
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diff changeset
1370 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
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diff changeset
1371 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
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diff changeset
1372 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
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diff changeset
1373 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
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diff changeset
1374 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
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diff changeset
1375
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diff changeset
1376 /******************** Bits definition for DMA_HIFCR register ****************/
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diff changeset
1377 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
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diff changeset
1378 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
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diff changeset
1379 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
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diff changeset
1380 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
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diff changeset
1381 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
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diff changeset
1382 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
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diff changeset
1383 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
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diff changeset
1384 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
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diff changeset
1385 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
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diff changeset
1386 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
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diff changeset
1387 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
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diff changeset
1388 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
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diff changeset
1389 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
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diff changeset
1390 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
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diff changeset
1391 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
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diff changeset
1392 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
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diff changeset
1393 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
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diff changeset
1394 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
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diff changeset
1395 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
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diff changeset
1396 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
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diff changeset
1397
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diff changeset
1398
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diff changeset
1399 /******************************************************************************/
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1400 /* */
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diff changeset
1401 /* External Interrupt/Event Controller */
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diff changeset
1402 /* */
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diff changeset
1403 /******************************************************************************/
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diff changeset
1404 /******************* Bit definition for EXTI_IMR register *******************/
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diff changeset
1405 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
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diff changeset
1406 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
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diff changeset
1407 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
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diff changeset
1408 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
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diff changeset
1409 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
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diff changeset
1410 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
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diff changeset
1411 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
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diff changeset
1412 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
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diff changeset
1413 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
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diff changeset
1414 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
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diff changeset
1415 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
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diff changeset
1416 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
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diff changeset
1417 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
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diff changeset
1418 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
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diff changeset
1419 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
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diff changeset
1420 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
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diff changeset
1421 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
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diff changeset
1422 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
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diff changeset
1423 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
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diff changeset
1424 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
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1425
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1426 /******************* Bit definition for EXTI_EMR register *******************/
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diff changeset
1427 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
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diff changeset
1428 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
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diff changeset
1429 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
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diff changeset
1430 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
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diff changeset
1431 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
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diff changeset
1432 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
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diff changeset
1433 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
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diff changeset
1434 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
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diff changeset
1435 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
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diff changeset
1436 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
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diff changeset
1437 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
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diff changeset
1438 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
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diff changeset
1439 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
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diff changeset
1440 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
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diff changeset
1441 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
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diff changeset
1442 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
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diff changeset
1443 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
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diff changeset
1444 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
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diff changeset
1445 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
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diff changeset
1446 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
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diff changeset
1447
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1448 /****************** Bit definition for EXTI_RTSR register *******************/
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diff changeset
1449 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
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diff changeset
1450 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
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diff changeset
1451 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
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diff changeset
1452 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
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diff changeset
1453 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
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diff changeset
1454 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
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diff changeset
1455 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
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diff changeset
1456 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
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diff changeset
1457 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
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diff changeset
1458 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
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diff changeset
1459 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
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diff changeset
1460 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
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diff changeset
1461 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
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diff changeset
1462 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
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diff changeset
1463 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
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diff changeset
1464 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
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diff changeset
1465 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
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diff changeset
1466 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
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diff changeset
1467 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
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1468 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
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1469
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1470 /****************** Bit definition for EXTI_FTSR register *******************/
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1471 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
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diff changeset
1472 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
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diff changeset
1473 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
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diff changeset
1474 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
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diff changeset
1475 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
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diff changeset
1476 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
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diff changeset
1477 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
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diff changeset
1478 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
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diff changeset
1479 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
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diff changeset
1480 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
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diff changeset
1481 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
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diff changeset
1482 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
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diff changeset
1483 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
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diff changeset
1484 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
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parents:
diff changeset
1485 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
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parents:
diff changeset
1486 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
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diff changeset
1487 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
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diff changeset
1488 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
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diff changeset
1489 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
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diff changeset
1490 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
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diff changeset
1491
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diff changeset
1492 /****************** Bit definition for EXTI_SWIER register ******************/
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diff changeset
1493 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
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diff changeset
1494 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
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diff changeset
1495 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
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diff changeset
1496 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
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diff changeset
1497 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
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diff changeset
1498 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
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diff changeset
1499 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
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diff changeset
1500 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
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diff changeset
1501 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
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diff changeset
1502 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
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diff changeset
1503 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
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diff changeset
1504 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
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diff changeset
1505 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
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diff changeset
1506 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
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diff changeset
1507 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
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diff changeset
1508 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
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diff changeset
1509 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
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diff changeset
1510 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
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parents:
diff changeset
1511 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
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diff changeset
1512 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
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1513
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diff changeset
1514 /******************* Bit definition for EXTI_PR register ********************/
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diff changeset
1515 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
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diff changeset
1516 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
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diff changeset
1517 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
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diff changeset
1518 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
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diff changeset
1519 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
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diff changeset
1520 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
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diff changeset
1521 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
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diff changeset
1522 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
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diff changeset
1523 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
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diff changeset
1524 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
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diff changeset
1525 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
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diff changeset
1526 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
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parents:
diff changeset
1527 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
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diff changeset
1528 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
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diff changeset
1529 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
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diff changeset
1530 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
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diff changeset
1531 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
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parents:
diff changeset
1532 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
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diff changeset
1533 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
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diff changeset
1534 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
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diff changeset
1535
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diff changeset
1536 /******************************************************************************/
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diff changeset
1537 /* */
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parents:
diff changeset
1538 /* FLASH */
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diff changeset
1539 /* */
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diff changeset
1540 /******************************************************************************/
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diff changeset
1541 /******************* Bits definition for FLASH_ACR register *****************/
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diff changeset
1542 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
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diff changeset
1543 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
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diff changeset
1544 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
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diff changeset
1545 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
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diff changeset
1546 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
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diff changeset
1547 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
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diff changeset
1548 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
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diff changeset
1549 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
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diff changeset
1550 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
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diff changeset
1551
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diff changeset
1552 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
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diff changeset
1553 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
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diff changeset
1554 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
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diff changeset
1555 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
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parents:
diff changeset
1556 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
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diff changeset
1557 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
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diff changeset
1558 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
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parents:
diff changeset
1559
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diff changeset
1560 /******************* Bits definition for FLASH_SR register ******************/
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diff changeset
1561 #define FLASH_SR_EOP ((uint32_t)0x00000001)
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parents:
diff changeset
1562 #define FLASH_SR_SOP ((uint32_t)0x00000002)
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diff changeset
1563 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
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diff changeset
1564 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
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diff changeset
1565 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
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diff changeset
1566 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
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diff changeset
1567 #define FLASH_SR_BSY ((uint32_t)0x00010000)
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diff changeset
1568
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diff changeset
1569 /******************* Bits definition for FLASH_CR register ******************/
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diff changeset
1570 #define FLASH_CR_PG ((uint32_t)0x00000001)
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diff changeset
1571 #define FLASH_CR_SER ((uint32_t)0x00000002)
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diff changeset
1572 #define FLASH_CR_MER ((uint32_t)0x00000004)
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diff changeset
1573 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
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diff changeset
1574 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
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diff changeset
1575 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
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diff changeset
1576 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
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diff changeset
1577 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
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diff changeset
1578 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
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diff changeset
1579 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
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diff changeset
1580 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
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diff changeset
1581 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
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diff changeset
1582 #define FLASH_CR_STRT ((uint32_t)0x00010000)
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diff changeset
1583 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
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1584 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
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1585
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1586 /******************* Bits definition for FLASH_OPTCR register ***************/
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diff changeset
1587 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
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diff changeset
1588 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
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1589 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
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diff changeset
1590 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
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diff changeset
1591 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
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1592
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1593 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
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1594 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
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1595 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
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diff changeset
1596 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
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1597 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
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diff changeset
1598 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
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diff changeset
1599 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
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1600 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
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1601 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
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1602 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
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1603 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
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1604 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
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1605 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
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1606 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
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1607 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
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1608 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
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1609 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
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1610 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
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1611 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
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1612 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
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1613 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
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1614 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
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1615 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
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1616 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
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1617 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
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1618
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1619 /****************** Bits definition for FLASH_OPTCR1 register ***************/
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1620 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
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1621 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
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1622 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
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1623 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
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1624 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
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1625 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
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1626 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
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1627 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
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1628 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
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1629 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
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1630 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
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1631 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
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1632 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
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1633
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1634 /******************************************************************************/
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1635 /* */
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1636 /* General Purpose I/O */
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diff changeset
1637 /* */
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1638 /******************************************************************************/
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diff changeset
1639 /****************** Bits definition for GPIO_MODER register *****************/
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1640 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
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1641 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
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1642 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
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1643
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1644 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
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1645 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
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1646 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
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1647
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1648 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
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1649 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
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1650 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
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1651
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1652 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
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1653 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
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1654 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
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1655
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1656 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
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1657 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
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1658 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
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1659
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1660 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
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1661 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
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1662 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
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1663
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1664 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
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1665 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
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1666 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
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1667
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1668 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
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1669 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
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1670 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
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1671
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1672 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
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1673 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
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1674 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
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1675
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1676 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
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1677 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
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1678 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
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1679
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1680 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
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1681 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
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1682 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
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1683
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1684 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
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1685 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
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1686 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
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1687
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1688 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
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1689 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
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1690 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
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1691
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1692 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
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1693 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
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1694 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
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1695
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1696 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
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1697 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
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1698 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
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1699
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1700 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
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1701 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
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1702 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
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1703
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parents:
diff changeset
1704 /****************** Bits definition for GPIO_OTYPER register ****************/
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1705 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
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1706 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
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1707 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
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parents:
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1708 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
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1709 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
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1710 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
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1711 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
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1712 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
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1713 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
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1714 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
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1715 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
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1716 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
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1717 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
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1718 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
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1719 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
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1720 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
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1721
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parents:
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1722 /****************** Bits definition for GPIO_OSPEEDR register ***************/
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1723 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
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1724 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
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1725 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
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1726
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1727 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
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1728 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
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1729 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
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1730
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1731 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
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1732 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
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1733 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
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1734
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1735 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
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1736 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
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1737 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
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1738
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1739 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
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1740 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
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1741 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
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1742
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1743 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
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1744 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
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1745 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
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1746
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1747 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
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1748 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
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1749 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
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1750
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1751 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
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1752 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
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1753 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
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1754
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1755 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
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1756 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
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1757 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
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1758
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1759 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
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1760 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
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1761 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
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1762
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1763 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
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1764 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
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1765 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
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1766
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1767 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
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1768 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
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diff changeset
1769 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
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diff changeset
1770
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diff changeset
1771 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
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diff changeset
1772 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
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diff changeset
1773 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
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1774
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diff changeset
1775 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
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1776 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
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1777 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
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1778
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diff changeset
1779 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
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diff changeset
1780 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
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diff changeset
1781 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
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1782
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diff changeset
1783 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
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1784 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
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diff changeset
1785 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
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1786
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diff changeset
1787 /****************** Bits definition for GPIO_PUPDR register *****************/
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1788 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
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1789 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
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1790 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
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1791
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1792 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
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1793 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
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1794 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
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1795
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1796 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
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1797 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
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1798 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
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1799
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1800 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
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1801 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
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1802 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
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1803
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1804 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
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1805 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
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1806 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
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1807
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1808 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
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1809 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
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1810 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
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1811
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1812 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
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1813 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
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1814 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
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1815
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1816 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
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1817 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
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1818 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
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1819
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1820 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
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1821 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
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1822 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
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1823
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1824 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
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1825 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
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1826 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
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1827
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1828 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
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1829 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
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1830 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
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1831
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1832 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
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1833 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
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1834 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
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1835
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1836 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
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1837 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
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1838 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
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1839
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1840 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
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1841 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
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1842 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
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1843
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1844 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
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1845 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
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1846 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
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1847
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1848 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
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1849 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
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1850 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
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1851
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1852 /****************** Bits definition for GPIO_IDR register *******************/
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1853 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
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1854 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
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1855 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
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1856 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
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1857 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
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1858 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
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1859 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
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1860 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
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1861 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
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1862 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
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1863 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
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1864 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
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1865 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
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1866 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
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1867 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
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1868 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
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1869 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
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1870 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
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1871 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
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1872 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
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1873 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
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1874 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
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1875 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
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1876 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
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1877 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
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1878 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
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1879 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
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1880 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
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1881 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
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1882 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
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1883 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
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1884 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
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1885 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
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1886
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1887 /****************** Bits definition for GPIO_ODR register *******************/
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1888 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
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1889 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
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1890 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
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1891 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
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1892 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
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1893 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
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1894 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
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1895 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
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1896 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
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1897 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
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1898 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
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1899 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
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1900 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
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1901 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
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1902 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
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1903 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
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1904 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
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1905 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
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1906 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
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1907 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
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1908 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
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1909 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
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1910 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
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1911 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
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1912 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
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1913 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
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1914 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
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1915 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
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1916 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
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1917 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
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1918 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
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1919 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
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1920 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
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1921
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1922 /****************** Bits definition for GPIO_BSRR register ******************/
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1923 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
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1924 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
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1925 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
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1926 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
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1927 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
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1928 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
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1929 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
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1930 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
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1931 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
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1932 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
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1933 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
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1934 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
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1935 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
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1936 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
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1937 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
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1938 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
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1939 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
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1940 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
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1941 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
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1942 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
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1943 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
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1944 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
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1945 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
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1946 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
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1947 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
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1948 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
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1949 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
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1950 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
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1951 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
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1952 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
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1953 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
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1954 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
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1955
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1956 /****************** Bit definition for GPIO_LCKR register *********************/
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1957 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
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1958 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
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1959 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
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1960 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
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1961 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
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1962 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
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1963 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
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1964 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
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1965 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
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1966 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
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1967 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
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1968 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
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1969 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
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1970 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
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1971 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
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1972 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
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1973 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
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1974
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1975 /******************************************************************************/
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1976 /* */
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1977 /* Inter-integrated Circuit Interface */
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1978 /* */
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1979 /******************************************************************************/
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1980 /******************* Bit definition for I2C_CR1 register ********************/
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1981 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
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1982 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
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1983 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
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1984 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
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1985 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
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1986 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
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1987 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
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1988 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
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1989 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
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1990 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
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1991 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
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1992 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
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1993 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
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1994 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
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1995
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1996 /******************* Bit definition for I2C_CR2 register ********************/
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1997 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
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1998 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
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1999 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
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2000 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
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2001 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
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2002 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
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2003 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
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2004
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2005 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
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2006 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
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2007 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
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2008 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
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2009 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
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2010
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2011 /******************* Bit definition for I2C_OAR1 register *******************/
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2012 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
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2013 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
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2014
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2015 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
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2016 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
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2017 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
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2018 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
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2019 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
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2020 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
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2021 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
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2022 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
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2023 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
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2024 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
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2025
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2026 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
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2027
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2028 /******************* Bit definition for I2C_OAR2 register *******************/
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2029 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
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2030 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
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2031
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2032 /******************** Bit definition for I2C_DR register ********************/
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2033 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
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2034
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2035 /******************* Bit definition for I2C_SR1 register ********************/
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2036 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
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2037 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
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2038 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
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2039 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
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2040 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
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2041 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
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2042 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
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2043 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
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2044 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
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2045 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
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2046 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
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2047 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
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2048 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
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2049 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
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2050
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2051 /******************* Bit definition for I2C_SR2 register ********************/
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2052 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2053 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2054 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2055 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2056 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2057 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2058 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2059 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2060
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2061 /******************* Bit definition for I2C_CCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2062 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2063 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2064 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2065
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2066 /****************** Bit definition for I2C_TRISE register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2067 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2068
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2069 /****************** Bit definition for I2C_FLTR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2070 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2071 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2072
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2073 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2074 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2075 /* Independent WATCHDOG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2076 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2077 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2078 /******************* Bit definition for IWDG_KR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2079 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2080
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2081 /******************* Bit definition for IWDG_PR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2082 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2083 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2084 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2085 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2086
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2087 /******************* Bit definition for IWDG_RLR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2088 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2089
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2090 /******************* Bit definition for IWDG_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2091 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2092 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2093
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2094
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2095 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2096 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2097 /* Power Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2098 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2099 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2100 /******************** Bit definition for PWR_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2101 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2102 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2103 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2104 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2105 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2106
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2107 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2108 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2109 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2110 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2111
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2112 /*!< PVD level configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2113 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2114 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2115 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2116 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2117 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2118 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2119 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2120 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2121
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2122 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2123 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2124 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2125 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2126 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2127 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2128 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2129 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2130
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2131 /* Legacy define */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2132 #define PWR_CR_PMODE PWR_CR_VOS
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2133
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2134 /******************* Bit definition for PWR_CSR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2135 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2136 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2137 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2138 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2139 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2140 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2141 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2142
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2143 /* Legacy define */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2144 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2145
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2146 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2147 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2148 /* Reset and Clock Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2149 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2150 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2151 /******************** Bit definition for RCC_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2152 #define RCC_CR_HSION ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2153 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2154
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2155 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2156 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2157 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2158 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2159 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2160 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2161
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2162 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2163 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2164 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2165 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2166 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2167 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2168 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2169 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2170 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2171
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2172 #define RCC_CR_HSEON ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2173 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2174 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2175 #define RCC_CR_CSSON ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2176 #define RCC_CR_PLLON ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2177 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2178 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2179 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2180
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2181 /******************** Bit definition for RCC_PLLCFGR register ***************/
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heinrichsweikamp
parents:
diff changeset
2182 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2183 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2184 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2185 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2186 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2187 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2188 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
2189
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heinrichsweikamp
parents:
diff changeset
2190 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
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heinrichsweikamp
parents:
diff changeset
2191 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2192 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2193 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
2194 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2195 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2196 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2197 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
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diff changeset
2198 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
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diff changeset
2199 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
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parents:
diff changeset
2200
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parents:
diff changeset
2201 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
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parents:
diff changeset
2202 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
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parents:
diff changeset
2203 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
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parents:
diff changeset
2204
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parents:
diff changeset
2205 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
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parents:
diff changeset
2206 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
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parents:
diff changeset
2207 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
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parents:
diff changeset
2208
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parents:
diff changeset
2209 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
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parents:
diff changeset
2210 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
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parents:
diff changeset
2211 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
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parents:
diff changeset
2212 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
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parents:
diff changeset
2213 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
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parents:
diff changeset
2214
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parents:
diff changeset
2215 /******************** Bit definition for RCC_CFGR register ******************/
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parents:
diff changeset
2216 /*!< SW configuration */
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diff changeset
2217 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
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diff changeset
2218 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
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diff changeset
2219 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
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parents:
diff changeset
2220
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parents:
diff changeset
2221 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
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diff changeset
2222 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
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parents:
diff changeset
2223 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
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parents:
diff changeset
2224
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parents:
diff changeset
2225 /*!< SWS configuration */
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parents:
diff changeset
2226 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
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diff changeset
2227 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
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diff changeset
2228 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
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parents:
diff changeset
2229
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parents:
diff changeset
2230 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
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parents:
diff changeset
2231 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
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parents:
diff changeset
2232 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
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parents:
diff changeset
2233
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parents:
diff changeset
2234 /*!< HPRE configuration */
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parents:
diff changeset
2235 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
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parents:
diff changeset
2236 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
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parents:
diff changeset
2237 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
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parents:
diff changeset
2238 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
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parents:
diff changeset
2239 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
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parents:
diff changeset
2240
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parents:
diff changeset
2241 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
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parents:
diff changeset
2242 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
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parents:
diff changeset
2243 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
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parents:
diff changeset
2244 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
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parents:
diff changeset
2245 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
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parents:
diff changeset
2246 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
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parents:
diff changeset
2247 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
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parents:
diff changeset
2248 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
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parents:
diff changeset
2249 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
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parents:
diff changeset
2250
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parents:
diff changeset
2251 /*!< PPRE1 configuration */
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parents:
diff changeset
2252 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
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parents:
diff changeset
2253 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
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parents:
diff changeset
2254 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
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parents:
diff changeset
2255 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
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parents:
diff changeset
2256
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parents:
diff changeset
2257 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
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parents:
diff changeset
2258 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
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parents:
diff changeset
2259 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
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heinrichsweikamp
parents:
diff changeset
2260 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
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parents:
diff changeset
2261 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
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heinrichsweikamp
parents:
diff changeset
2262
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parents:
diff changeset
2263 /*!< PPRE2 configuration */
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parents:
diff changeset
2264 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
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parents:
diff changeset
2265 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
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parents:
diff changeset
2266 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
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parents:
diff changeset
2267 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
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parents:
diff changeset
2268
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diff changeset
2269 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
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parents:
diff changeset
2270 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
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parents:
diff changeset
2271 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
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parents:
diff changeset
2272 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
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parents:
diff changeset
2273 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
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parents:
diff changeset
2274
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parents:
diff changeset
2275 /*!< RTCPRE configuration */
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parents:
diff changeset
2276 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
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diff changeset
2277 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
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parents:
diff changeset
2278 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
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diff changeset
2279 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
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diff changeset
2280 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
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parents:
diff changeset
2281 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
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parents:
diff changeset
2282
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parents:
diff changeset
2283 /*!< MCO1 configuration */
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parents:
diff changeset
2284 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
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diff changeset
2285 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
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diff changeset
2286 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
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diff changeset
2287
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diff changeset
2288 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
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parents:
diff changeset
2289
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diff changeset
2290 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
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diff changeset
2291 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
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diff changeset
2292 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
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diff changeset
2293 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
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diff changeset
2294
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diff changeset
2295 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
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diff changeset
2296 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
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parents:
diff changeset
2297 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
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diff changeset
2298 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
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diff changeset
2299
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diff changeset
2300 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
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diff changeset
2301 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
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diff changeset
2302 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
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2303
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2304 /******************** Bit definition for RCC_CIR register *******************/
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diff changeset
2305 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
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diff changeset
2306 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
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2307 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
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diff changeset
2308 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
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2309 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
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2310 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
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2311
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2312 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
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2313 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
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diff changeset
2314 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
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2315 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
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2316 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
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2317 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
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2318 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
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2319
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2320 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
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2321 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
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2322 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
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2323 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
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2324 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
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2325 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
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2326
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2327 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
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2328
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2329 /******************** Bit definition for RCC_AHB1RSTR register **************/
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2330 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
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2331 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
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2332 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
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2333 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
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2334 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
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2335 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
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2336 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
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2337 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
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2338 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
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2339
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parents:
diff changeset
2340 /******************** Bit definition for RCC_AHB2RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2341 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2342
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2343 /******************** Bit definition for RCC_AHB3RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2344
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2345 /******************** Bit definition for RCC_APB1RSTR register **************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2346 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2347 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2348 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2349 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2350 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2351 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2352 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2353 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2354 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2355 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2356 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
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heinrichsweikamp
parents:
diff changeset
2357 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2358
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heinrichsweikamp
parents:
diff changeset
2359 /******************** Bit definition for RCC_APB2RSTR register **************/
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heinrichsweikamp
parents:
diff changeset
2360 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
2361 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2362 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
2363 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2364 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
2365 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
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heinrichsweikamp
parents:
diff changeset
2366 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
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heinrichsweikamp
parents:
diff changeset
2367 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
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heinrichsweikamp
parents:
diff changeset
2368 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
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heinrichsweikamp
parents:
diff changeset
2369 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
2370 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
2371
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2372 /* Old SPI1RST bit definition, maintained for legacy purpose */
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heinrichsweikamp
parents:
diff changeset
2373 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2374
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2375 /******************** Bit definition for RCC_AHB1ENR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2376 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
2377 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2378 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2379 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2380 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2381 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2382 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2383 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2384 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
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heinrichsweikamp
parents:
diff changeset
2385 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2386 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2387
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2388 /******************** Bit definition for RCC_AHB2ENR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2389 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2390
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2391 /******************** Bit definition for RCC_AHB3ENR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2392
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2393 /******************** Bit definition for RCC_APB1ENR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2394 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2395 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2396 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2397 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2398 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2399 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2400 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2401 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2402 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2403 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2404 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2405 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2406
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2407 /******************** Bit definition for RCC_APB2ENR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2408 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2409 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
2410 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
2411 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
2412 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
2413 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2414 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2415 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
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heinrichsweikamp
parents:
diff changeset
2416 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
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heinrichsweikamp
parents:
diff changeset
2417 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2418 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
2419
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heinrichsweikamp
parents:
diff changeset
2420 /******************** Bit definition for RCC_AHB1LPENR register *************/
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heinrichsweikamp
parents:
diff changeset
2421 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
2422 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
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heinrichsweikamp
parents:
diff changeset
2423 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2424 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2425 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
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heinrichsweikamp
parents:
diff changeset
2426 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2427 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2428 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2429 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2430 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2431 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2432 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2433 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
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heinrichsweikamp
parents:
diff changeset
2434 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2435
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2436 /******************** Bit definition for RCC_AHB2LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2437 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2438
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2439 /******************** Bit definition for RCC_AHB3LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2440
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2441 /******************** Bit definition for RCC_APB1LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2442 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2443 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2444 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2445 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2446 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2447 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2448 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2449 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2450 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2451 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2452 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2453 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2454 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2455
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2456 /******************** Bit definition for RCC_APB2LPENR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2457 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2458 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2459 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2460 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2461 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2462 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2463 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2464 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2465 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2466 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2467 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2468
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2469 /******************** Bit definition for RCC_BDCR register ******************/
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heinrichsweikamp
parents:
diff changeset
2470 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2471 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2472 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
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heinrichsweikamp
parents:
diff changeset
2473
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2474 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
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heinrichsweikamp
parents:
diff changeset
2475 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
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heinrichsweikamp
parents:
diff changeset
2476 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
2477
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heinrichsweikamp
parents:
diff changeset
2478 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
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heinrichsweikamp
parents:
diff changeset
2479 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
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heinrichsweikamp
parents:
diff changeset
2480
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2481 /******************** Bit definition for RCC_CSR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2482 #define RCC_CSR_LSION ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2483 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2484 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2485 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2486 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2487 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2488 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2489 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2490 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2491 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2492
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2493 /******************** Bit definition for RCC_SSCGR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2494 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2495 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2496 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2497 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2498
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2499 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
5f11787b4f42 include in ostc4 repository
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diff changeset
2500 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2501 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2502 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2503 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2504 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2505 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2506 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2507 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2508 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2509 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2510
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2511 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2512 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2513 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2514 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2515
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2516 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
2517 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2518 /* Real-Time Clock (RTC) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2519 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2520 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2521 /******************** Bits definition for RTC_TR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2522 #define RTC_TR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2523 #define RTC_TR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2524 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2525 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2526 #define RTC_TR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2527 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2528 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2529 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2530 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2531 #define RTC_TR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2532 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2533 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2534 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2535 #define RTC_TR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2536 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2537 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2538 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2539 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2540 #define RTC_TR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2541 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2542 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2543 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2544 #define RTC_TR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2545 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2546 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2547 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2548 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2549
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2550 /******************** Bits definition for RTC_DR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2551 #define RTC_DR_YT ((uint32_t)0x00F00000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2552 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2553 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2554 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2555 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2556 #define RTC_DR_YU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2557 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2558 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2559 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2560 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2561 #define RTC_DR_WDU ((uint32_t)0x0000E000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2562 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2563 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2564 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2565 #define RTC_DR_MT ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2566 #define RTC_DR_MU ((uint32_t)0x00000F00)
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heinrichsweikamp
parents:
diff changeset
2567 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2568 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2569 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2570 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2571 #define RTC_DR_DT ((uint32_t)0x00000030)
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heinrichsweikamp
parents:
diff changeset
2572 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2573 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
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heinrichsweikamp
parents:
diff changeset
2574 #define RTC_DR_DU ((uint32_t)0x0000000F)
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heinrichsweikamp
parents:
diff changeset
2575 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
2576 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
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heinrichsweikamp
parents:
diff changeset
2577 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
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heinrichsweikamp
parents:
diff changeset
2578 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
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heinrichsweikamp
parents:
diff changeset
2579
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2580 /******************** Bits definition for RTC_CR register *******************/
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heinrichsweikamp
parents:
diff changeset
2581 #define RTC_CR_COE ((uint32_t)0x00800000)
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parents:
diff changeset
2582 #define RTC_CR_OSEL ((uint32_t)0x00600000)
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parents:
diff changeset
2583 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2584 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2585 #define RTC_CR_POL ((uint32_t)0x00100000)
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heinrichsweikamp
parents:
diff changeset
2586 #define RTC_CR_COSEL ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2587 #define RTC_CR_BCK ((uint32_t)0x00040000)
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heinrichsweikamp
parents:
diff changeset
2588 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
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heinrichsweikamp
parents:
diff changeset
2589 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
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heinrichsweikamp
parents:
diff changeset
2590 #define RTC_CR_TSIE ((uint32_t)0x00008000)
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heinrichsweikamp
parents:
diff changeset
2591 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
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heinrichsweikamp
parents:
diff changeset
2592 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
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heinrichsweikamp
parents:
diff changeset
2593 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
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heinrichsweikamp
parents:
diff changeset
2594 #define RTC_CR_TSE ((uint32_t)0x00000800)
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heinrichsweikamp
parents:
diff changeset
2595 #define RTC_CR_WUTE ((uint32_t)0x00000400)
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parents:
diff changeset
2596 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
2597 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
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parents:
diff changeset
2598 #define RTC_CR_DCE ((uint32_t)0x00000080)
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parents:
diff changeset
2599 #define RTC_CR_FMT ((uint32_t)0x00000040)
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parents:
diff changeset
2600 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
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parents:
diff changeset
2601 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
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parents:
diff changeset
2602 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
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parents:
diff changeset
2603 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
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parents:
diff changeset
2604 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
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parents:
diff changeset
2605 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2606 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
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parents:
diff changeset
2607
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heinrichsweikamp
parents:
diff changeset
2608 /******************** Bits definition for RTC_ISR register ******************/
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heinrichsweikamp
parents:
diff changeset
2609 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
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parents:
diff changeset
2610 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
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heinrichsweikamp
parents:
diff changeset
2611 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
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parents:
diff changeset
2612 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
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parents:
diff changeset
2613 #define RTC_ISR_TSF ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2614 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2615 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
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heinrichsweikamp
parents:
diff changeset
2616 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
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parents:
diff changeset
2617 #define RTC_ISR_INIT ((uint32_t)0x00000080)
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parents:
diff changeset
2618 #define RTC_ISR_INITF ((uint32_t)0x00000040)
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diff changeset
2619 #define RTC_ISR_RSF ((uint32_t)0x00000020)
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parents:
diff changeset
2620 #define RTC_ISR_INITS ((uint32_t)0x00000010)
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diff changeset
2621 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
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diff changeset
2622 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
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diff changeset
2623 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
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diff changeset
2624 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
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diff changeset
2625
5f11787b4f42 include in ostc4 repository
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parents:
diff changeset
2626 /******************** Bits definition for RTC_PRER register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2627 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2628 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2629
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2630 /******************** Bits definition for RTC_WUTR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2631 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2632
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2633 /******************** Bits definition for RTC_CALIBR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2634 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2635 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2636
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2637 /******************** Bits definition for RTC_ALRMAR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2638 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2639 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2640 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2641 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2642 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2643 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2644 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2645 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2646 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2647 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2648 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2649 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2650 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2651 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2652 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2653 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2654 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2655 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2656 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2657 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2658 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2659 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2660 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2661 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2662 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2663 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2664 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2665 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2666 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2667 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2668 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2669 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2670 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2671 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2672 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2673 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2674 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2675 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2676 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2677 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2678
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2679 /******************** Bits definition for RTC_ALRMBR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2680 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2681 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2682 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2683 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2684 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2685 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2686 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2687 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2688 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2689 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2690 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2691 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2692 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2693 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2694 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2695 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2696 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2697 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2698 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2699 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2700 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2701 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2702 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2703 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2704 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2705 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2706 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2707 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2708 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2709 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2710 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2711 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2712 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2713 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2714 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2715 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2716 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2717 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2718 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2719 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2720
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2721 /******************** Bits definition for RTC_WPR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2722 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2723
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2724 /******************** Bits definition for RTC_SSR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2725 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2726
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2727 /******************** Bits definition for RTC_SHIFTR register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2728 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2729 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2730
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2731 /******************** Bits definition for RTC_TSTR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2732 #define RTC_TSTR_PM ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2733 #define RTC_TSTR_HT ((uint32_t)0x00300000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2734 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2735 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2736 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2737 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2738 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2739 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2740 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2741 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2742 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2743 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2744 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2745 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2746 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2747 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2748 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2749 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2750 #define RTC_TSTR_ST ((uint32_t)0x00000070)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2751 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2752 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2753 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2754 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2755 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2756 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2757 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2758 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2759
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2760 /******************** Bits definition for RTC_TSDR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2761 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2762 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2763 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2764 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2765 #define RTC_TSDR_MT ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2766 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2767 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2768 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2769 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2770 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2771 #define RTC_TSDR_DT ((uint32_t)0x00000030)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2772 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2773 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2774 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2775 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2776 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2777 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2778 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2779
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2780 /******************** Bits definition for RTC_TSSSR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2781 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2782
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2783 /******************** Bits definition for RTC_CAL register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2784 #define RTC_CALR_CALP ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2785 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2786 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2787 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2788 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2789 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2790 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2791 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2792 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2793 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2794 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2795 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2796 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2797
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2798 /******************** Bits definition for RTC_TAFCR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2799 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2800 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2801 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2802 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2803 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2804 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2805 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2806 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2807 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2808 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2809 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2810 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2811 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2812 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2813 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2814 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2815 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2816 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2817 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2818 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2819
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2820 /******************** Bits definition for RTC_ALRMASSR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2821 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2822 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2823 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2824 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2825 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2826 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2827
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2828 /******************** Bits definition for RTC_ALRMBSSR register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2829 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2830 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2831 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2832 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2833 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2834 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2835
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2836 /******************** Bits definition for RTC_BKP0R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2837 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2838
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2839 /******************** Bits definition for RTC_BKP1R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2840 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2841
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2842 /******************** Bits definition for RTC_BKP2R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2843 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2844
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2845 /******************** Bits definition for RTC_BKP3R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2846 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2847
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2848 /******************** Bits definition for RTC_BKP4R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2849 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2850
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2851 /******************** Bits definition for RTC_BKP5R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2852 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2853
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2854 /******************** Bits definition for RTC_BKP6R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2855 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2856
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2857 /******************** Bits definition for RTC_BKP7R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2858 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2859
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2860 /******************** Bits definition for RTC_BKP8R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2861 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2862
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2863 /******************** Bits definition for RTC_BKP9R register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2864 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2865
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2866 /******************** Bits definition for RTC_BKP10R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2867 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2868
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2869 /******************** Bits definition for RTC_BKP11R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2870 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2871
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2872 /******************** Bits definition for RTC_BKP12R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2873 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2874
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2875 /******************** Bits definition for RTC_BKP13R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2876 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2877
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2878 /******************** Bits definition for RTC_BKP14R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2879 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2880
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2881 /******************** Bits definition for RTC_BKP15R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2882 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2883
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2884 /******************** Bits definition for RTC_BKP16R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2885 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2886
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2887 /******************** Bits definition for RTC_BKP17R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2888 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2889
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2890 /******************** Bits definition for RTC_BKP18R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2891 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2892
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2893 /******************** Bits definition for RTC_BKP19R register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2894 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2895
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2896
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2897
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2898 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
2899 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2900 /* SD host Interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2901 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2902 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2903 /****************** Bit definition for SDIO_POWER register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2904 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2905 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2906 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2907
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2908 /****************** Bit definition for SDIO_CLKCR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2909 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2910 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2911 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2912 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2913
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2914 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2915 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2916 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2917
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2918 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2919 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2920
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2921 /******************* Bit definition for SDIO_ARG register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2922 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2923
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heinrichsweikamp
parents:
diff changeset
2924 /******************* Bit definition for SDIO_CMD register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2925 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2926
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2927 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2928 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2929 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2930
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2931 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2932 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
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parents:
diff changeset
2933 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
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heinrichsweikamp
parents:
diff changeset
2934 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2935 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2936 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
2937 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2938
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heinrichsweikamp
parents:
diff changeset
2939 /***************** Bit definition for SDIO_RESPCMD register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2940 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2941
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heinrichsweikamp
parents:
diff changeset
2942 /****************** Bit definition for SDIO_RESP0 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2943 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2944
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2945 /****************** Bit definition for SDIO_RESP1 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2946 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2947
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2948 /****************** Bit definition for SDIO_RESP2 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2949 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2950
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heinrichsweikamp
parents:
diff changeset
2951 /****************** Bit definition for SDIO_RESP3 register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2952 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2953
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heinrichsweikamp
parents:
diff changeset
2954 /****************** Bit definition for SDIO_RESP4 register ******************/
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heinrichsweikamp
parents:
diff changeset
2955 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
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heinrichsweikamp
parents:
diff changeset
2956
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2957 /****************** Bit definition for SDIO_DTIMER register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2958 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2959
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2960 /****************** Bit definition for SDIO_DLEN register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2961 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2962
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2963 /****************** Bit definition for SDIO_DCTRL register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2964 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2965 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2966 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2967 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
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heinrichsweikamp
parents:
diff changeset
2968
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parents:
diff changeset
2969 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2970 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2971 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2972 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2973 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2974
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parents:
diff changeset
2975 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
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heinrichsweikamp
parents:
diff changeset
2976 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2977 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2978 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2979
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2980 /****************** Bit definition for SDIO_DCOUNT register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2981 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2982
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2983 /****************** Bit definition for SDIO_STA register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2984 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2985 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2986 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2987 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2988 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2989 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2990 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2991 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2992 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2993 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2994 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
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heinrichsweikamp
parents:
diff changeset
2995 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
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parents:
diff changeset
2996 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
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heinrichsweikamp
parents:
diff changeset
2997 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
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heinrichsweikamp
parents:
diff changeset
2998 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
2999 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
5f11787b4f42 include in ostc4 repository
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diff changeset
3000 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3001 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3002 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3003 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3004 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3005 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3006 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3007 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3008
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3009 /******************* Bit definition for SDIO_ICR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3010 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3011 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3012 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3013 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3014 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3015 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3016 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3017 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3018 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3019 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3020 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3021 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3022 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3023
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3024 /****************** Bit definition for SDIO_MASK register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3025 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3026 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3027 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3028 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3029 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3030 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3031 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3032 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
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parents:
diff changeset
3033 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3034 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3035 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3036 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3037 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3038 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
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heinrichsweikamp
parents:
diff changeset
3039 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3040 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3041 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3042 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3043 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3044 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3045 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3046 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3047 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3048 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3049
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diff changeset
3050 /***************** Bit definition for SDIO_FIFOCNT register *****************/
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heinrichsweikamp
parents:
diff changeset
3051 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
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heinrichsweikamp
parents:
diff changeset
3052
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heinrichsweikamp
parents:
diff changeset
3053 /****************** Bit definition for SDIO_FIFO register *******************/
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heinrichsweikamp
parents:
diff changeset
3054 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
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heinrichsweikamp
parents:
diff changeset
3055
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diff changeset
3056 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3057 /* */
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parents:
diff changeset
3058 /* Serial Peripheral Interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3059 /* */
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heinrichsweikamp
parents:
diff changeset
3060 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3061 /******************* Bit definition for SPI_CR1 register ********************/
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parents:
diff changeset
3062 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
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parents:
diff changeset
3063 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
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parents:
diff changeset
3064 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
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heinrichsweikamp
parents:
diff changeset
3065
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parents:
diff changeset
3066 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
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parents:
diff changeset
3067 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
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parents:
diff changeset
3068 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
3069 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
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heinrichsweikamp
parents:
diff changeset
3070
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parents:
diff changeset
3071 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
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heinrichsweikamp
parents:
diff changeset
3072 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
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parents:
diff changeset
3073 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
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parents:
diff changeset
3074 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
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parents:
diff changeset
3075 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
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parents:
diff changeset
3076 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
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parents:
diff changeset
3077 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
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parents:
diff changeset
3078 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
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parents:
diff changeset
3079 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
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heinrichsweikamp
parents:
diff changeset
3080 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
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heinrichsweikamp
parents:
diff changeset
3081
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heinrichsweikamp
parents:
diff changeset
3082 /******************* Bit definition for SPI_CR2 register ********************/
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parents:
diff changeset
3083 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
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parents:
diff changeset
3084 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
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parents:
diff changeset
3085 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
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parents:
diff changeset
3086 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
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parents:
diff changeset
3087 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
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parents:
diff changeset
3088 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
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parents:
diff changeset
3089 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
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heinrichsweikamp
parents:
diff changeset
3090
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parents:
diff changeset
3091 /******************** Bit definition for SPI_SR register ********************/
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parents:
diff changeset
3092 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
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parents:
diff changeset
3093 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
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parents:
diff changeset
3094 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
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parents:
diff changeset
3095 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
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parents:
diff changeset
3096 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
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parents:
diff changeset
3097 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
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parents:
diff changeset
3098 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
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parents:
diff changeset
3099 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
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parents:
diff changeset
3100 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
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parents:
diff changeset
3101
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parents:
diff changeset
3102 /******************** Bit definition for SPI_DR register ********************/
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parents:
diff changeset
3103 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
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heinrichsweikamp
parents:
diff changeset
3104
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heinrichsweikamp
parents:
diff changeset
3105 /******************* Bit definition for SPI_CRCPR register ******************/
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parents:
diff changeset
3106 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
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heinrichsweikamp
parents:
diff changeset
3107
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heinrichsweikamp
parents:
diff changeset
3108 /****************** Bit definition for SPI_RXCRCR register ******************/
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parents:
diff changeset
3109 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
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heinrichsweikamp
parents:
diff changeset
3110
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heinrichsweikamp
parents:
diff changeset
3111 /****************** Bit definition for SPI_TXCRCR register ******************/
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parents:
diff changeset
3112 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
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heinrichsweikamp
parents:
diff changeset
3113
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heinrichsweikamp
parents:
diff changeset
3114 /****************** Bit definition for SPI_I2SCFGR register *****************/
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diff changeset
3115 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
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diff changeset
3116
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parents:
diff changeset
3117 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
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parents:
diff changeset
3118 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
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parents:
diff changeset
3119 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
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parents:
diff changeset
3120
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parents:
diff changeset
3121 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
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diff changeset
3122
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parents:
diff changeset
3123 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
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parents:
diff changeset
3124 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
3125 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
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heinrichsweikamp
parents:
diff changeset
3126
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parents:
diff changeset
3127 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
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heinrichsweikamp
parents:
diff changeset
3128
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heinrichsweikamp
parents:
diff changeset
3129 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
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heinrichsweikamp
parents:
diff changeset
3130 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
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parents:
diff changeset
3131 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
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parents:
diff changeset
3132
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parents:
diff changeset
3133 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
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heinrichsweikamp
parents:
diff changeset
3134 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
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heinrichsweikamp
parents:
diff changeset
3135
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heinrichsweikamp
parents:
diff changeset
3136 /****************** Bit definition for SPI_I2SPR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3137 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
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heinrichsweikamp
parents:
diff changeset
3138 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
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heinrichsweikamp
parents:
diff changeset
3139 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
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heinrichsweikamp
parents:
diff changeset
3140
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heinrichsweikamp
parents:
diff changeset
3141 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3142 /* */
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heinrichsweikamp
parents:
diff changeset
3143 /* SYSCFG */
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heinrichsweikamp
parents:
diff changeset
3144 /* */
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heinrichsweikamp
parents:
diff changeset
3145 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3146 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
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heinrichsweikamp
parents:
diff changeset
3147 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
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heinrichsweikamp
parents:
diff changeset
3148 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
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heinrichsweikamp
parents:
diff changeset
3149 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
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heinrichsweikamp
parents:
diff changeset
3150 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
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heinrichsweikamp
parents:
diff changeset
3151
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3152 /****************** Bit definition for SYSCFG_PMC register ******************/
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heinrichsweikamp
parents:
diff changeset
3153 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3154
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heinrichsweikamp
parents:
diff changeset
3155 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
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heinrichsweikamp
parents:
diff changeset
3156 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
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heinrichsweikamp
parents:
diff changeset
3157 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
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heinrichsweikamp
parents:
diff changeset
3158 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
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heinrichsweikamp
parents:
diff changeset
3159 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3160 /**
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heinrichsweikamp
parents:
diff changeset
3161 * @brief EXTI0 configuration
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heinrichsweikamp
parents:
diff changeset
3162 */
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heinrichsweikamp
parents:
diff changeset
3163 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
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heinrichsweikamp
parents:
diff changeset
3164 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
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heinrichsweikamp
parents:
diff changeset
3165 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
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heinrichsweikamp
parents:
diff changeset
3166 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
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heinrichsweikamp
parents:
diff changeset
3167 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
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heinrichsweikamp
parents:
diff changeset
3168 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
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heinrichsweikamp
parents:
diff changeset
3169
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heinrichsweikamp
parents:
diff changeset
3170 /**
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heinrichsweikamp
parents:
diff changeset
3171 * @brief EXTI1 configuration
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heinrichsweikamp
parents:
diff changeset
3172 */
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heinrichsweikamp
parents:
diff changeset
3173 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
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heinrichsweikamp
parents:
diff changeset
3174 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
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heinrichsweikamp
parents:
diff changeset
3175 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
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heinrichsweikamp
parents:
diff changeset
3176 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
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heinrichsweikamp
parents:
diff changeset
3177 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
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heinrichsweikamp
parents:
diff changeset
3178 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
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heinrichsweikamp
parents:
diff changeset
3179
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heinrichsweikamp
parents:
diff changeset
3180 /**
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heinrichsweikamp
parents:
diff changeset
3181 * @brief EXTI2 configuration
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heinrichsweikamp
parents:
diff changeset
3182 */
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parents:
diff changeset
3183 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
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heinrichsweikamp
parents:
diff changeset
3184 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
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heinrichsweikamp
parents:
diff changeset
3185 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
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heinrichsweikamp
parents:
diff changeset
3186 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
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heinrichsweikamp
parents:
diff changeset
3187 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
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heinrichsweikamp
parents:
diff changeset
3188 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
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heinrichsweikamp
parents:
diff changeset
3189
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heinrichsweikamp
parents:
diff changeset
3190 /**
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heinrichsweikamp
parents:
diff changeset
3191 * @brief EXTI3 configuration
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heinrichsweikamp
parents:
diff changeset
3192 */
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diff changeset
3193 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
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parents:
diff changeset
3194 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
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parents:
diff changeset
3195 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
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heinrichsweikamp
parents:
diff changeset
3196 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
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parents:
diff changeset
3197 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
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diff changeset
3198 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
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parents:
diff changeset
3199
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diff changeset
3200 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
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diff changeset
3201 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3202 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3203 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3204 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3205 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3206 * @brief EXTI4 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3207 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3208 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3209 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3210 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3211 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3212 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3213 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3214
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3215 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3216 * @brief EXTI5 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3217 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3218 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3219 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3220 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3221 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3222 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3223 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3224
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3225 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3226 * @brief EXTI6 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3227 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3228 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3229 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3230 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3231 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3232 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3233 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3234
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3235 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3236 * @brief EXTI7 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3237 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3238 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3239 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3240 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3241 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3242 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3243 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3244
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3245
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3246 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3247 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3248 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3249 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3250 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3251
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3252 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3253 * @brief EXTI8 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3254 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3255 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3256 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3257 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3258 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3259 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3260 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3261
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3262 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3263 * @brief EXTI9 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3264 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3265 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3266 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3267 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3268 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3269 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3270 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3271
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3272 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3273 * @brief EXTI10 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3274 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3275 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3276 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3277 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3278 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3279 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3280 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3281
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3282 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3283 * @brief EXTI11 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3284 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3285 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3286 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3287 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3288 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3289 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3290 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3291
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3292 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3293 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3294 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3295 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3296 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3297 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3298 * @brief EXTI12 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3299 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3300 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3301 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3302 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3303 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3304 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3305 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3306
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3307 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3308 * @brief EXTI13 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3309 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3310 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3311 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3312 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3313 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3314 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3315 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3316
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3317 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3318 * @brief EXTI14 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3319 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3320 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3321 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3322 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3323 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3324 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3325 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3326
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3327 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3328 * @brief EXTI15 configuration
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3329 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3330 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3331 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3332 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3333 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3334 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3335 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3336
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3337 /****************** Bit definition for SYSCFG_CMPCR register ****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3338 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3339 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3340
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3341 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3342 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3343 /* TIM */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3344 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3345 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3346 /******************* Bit definition for TIM_CR1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3347 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3348 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3349 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3350 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3351 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3352
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3353 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3354 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3355 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3356
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3357 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3358
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3359 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3360 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3361 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3362
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3363 /******************* Bit definition for TIM_CR2 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3364 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3365 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3366 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3367
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3368 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3369 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3370 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3371 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3372
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3373 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3374 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3375 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3376 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3377 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3378 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3379 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3380 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3381
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heinrichsweikamp
parents:
diff changeset
3382 /******************* Bit definition for TIM_SMCR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3383 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3384 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
3385 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3386 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3387
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3388 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3389 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3390 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3391 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3392
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3393 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3394
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3395 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3396 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3397 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3398 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3399 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3400
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3401 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3402 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3403 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3404
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3405 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3406 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3407
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3408 /******************* Bit definition for TIM_DIER register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3409 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3410 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3411 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3412 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3413 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3414 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3415 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3416 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3417 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3418 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3419 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3420 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3421 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3422 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3423 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3424
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3425 /******************** Bit definition for TIM_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3426 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3427 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3428 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3429 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3430 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3431 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3432 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3433 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3434 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3435 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3436 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3437 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3438
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3439 /******************* Bit definition for TIM_EGR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3440 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3441 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3442 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3443 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3444 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3445 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3446 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3447 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3448
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3449 /****************** Bit definition for TIM_CCMR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3450 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3451 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3452 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3453
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3454 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3455 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3456
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3457 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3458 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3459 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3460 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3461
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3462 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3463
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3464 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3465 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3466 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3467
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3468 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3469 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3470
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3471 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3472 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3473 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3474 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3475
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heinrichsweikamp
parents:
diff changeset
3476 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3477
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heinrichsweikamp
parents:
diff changeset
3478 /*----------------------------------------------------------------------------*/
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heinrichsweikamp
parents:
diff changeset
3479
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heinrichsweikamp
parents:
diff changeset
3480 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
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heinrichsweikamp
parents:
diff changeset
3481 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
3482 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3483
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3484 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3485 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3486 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3487 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3488 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3489
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3490 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3491 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3492 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3493
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3494 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3495 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3496 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3497 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3498 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3499
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3500 /****************** Bit definition for TIM_CCMR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3501 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3502 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3503 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3504
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3505 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3506 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3507
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3508 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3509 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3510 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3511 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3512
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3513 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3514
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3515 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3516 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3517 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3518
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3519 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3520 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3521
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3522 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3523 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3524 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3525 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3526
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3527 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3528
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3529 /*----------------------------------------------------------------------------*/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3530
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3531 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3532 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3533 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3534
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3535 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3536 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3537 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3538 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3539 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3540
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3541 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3542 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3543 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3544
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3545 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3546 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3547 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3548 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3549 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3550
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3551 /******************* Bit definition for TIM_CCER register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3552 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3553 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3554 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3555 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3556 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3557 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3558 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3559 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3560 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3561 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3562 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3563 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3564 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3565 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3566 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3567
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3568 /******************* Bit definition for TIM_CNT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3569 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3570
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3571 /******************* Bit definition for TIM_PSC register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3572 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3573
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3574 /******************* Bit definition for TIM_ARR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3575 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3576
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3577 /******************* Bit definition for TIM_RCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3578 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3579
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3580 /******************* Bit definition for TIM_CCR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3581 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3582
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3583 /******************* Bit definition for TIM_CCR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3584 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3585
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3586 /******************* Bit definition for TIM_CCR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3587 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3588
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3589 /******************* Bit definition for TIM_CCR4 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3590 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3591
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3592 /******************* Bit definition for TIM_BDTR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3593 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3594 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3595 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3596 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3597 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3598 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3599 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3600 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3601 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3602
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3603 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3604 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3605 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3606
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3607 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3608 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3609 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3610 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3611 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3612 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3613
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3614 /******************* Bit definition for TIM_DCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3615 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3616 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3617 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3618 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3619 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3620 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3621
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3622 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3623 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3624 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3625 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3626 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3627 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3628
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3629 /******************* Bit definition for TIM_DMAR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3630 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3631
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3632 /******************* Bit definition for TIM_OR register *********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3633 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3634 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3635 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3636 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3637 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3638 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3639
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3640
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3641 /******************************************************************************/
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heinrichsweikamp
parents:
diff changeset
3642 /* */
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heinrichsweikamp
parents:
diff changeset
3643 /* Universal Synchronous Asynchronous Receiver Transmitter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3644 /* */
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heinrichsweikamp
parents:
diff changeset
3645 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3646 /******************* Bit definition for USART_SR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3647 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3648 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3649 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3650 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3651 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3652 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3653 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3654 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3655 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3656 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3657
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3658 /******************* Bit definition for USART_DR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3659 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3660
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3661 /****************** Bit definition for USART_BRR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3662 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3663 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3664
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3665 /****************** Bit definition for USART_CR1 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3666 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3667 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3668 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3669 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3670 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3671 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3672 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3673 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3674 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3675 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3676 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3677 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3678 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3679 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3680 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3681
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3682 /****************** Bit definition for USART_CR2 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3683 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3684 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3685 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3686 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3687 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3688 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3689 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3690
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3691 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3692 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3693 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3694
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3695 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3696
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3697 /****************** Bit definition for USART_CR3 register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3698 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3699 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3700 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3701 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3702 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3703 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3704 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3705 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3706 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3707 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3708 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3709 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3710
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3711 /****************** Bit definition for USART_GTPR register ******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3712 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3713 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3714 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3715 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3716 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3717 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3718 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3719 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3720 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3721
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3722 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3723
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3724 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3725 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3726 /* Window WATCHDOG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3727 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3728 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3729 /******************* Bit definition for WWDG_CR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3730 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3731 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3732 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3733 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3734 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3735 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3736 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3737 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3738
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3739 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3740
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3741 /******************* Bit definition for WWDG_CFR register *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3742 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3743 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3744 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3745 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3746 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3747 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3748 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3749 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3750
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3751 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3752 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
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heinrichsweikamp
parents:
diff changeset
3753 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3754
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3755 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
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heinrichsweikamp
parents:
diff changeset
3756
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3757 /******************* Bit definition for WWDG_SR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3758 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3759
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3760
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3761 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3762 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3763 /* DBG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3764 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3765 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3766 /******************** Bit definition for DBGMCU_IDCODE register *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3767 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3768 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3769
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3770 /******************** Bit definition for DBGMCU_CR register *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3771 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3772 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3773 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3774 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3775
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3776 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3777 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3778 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3779
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3780 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3781 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3782 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3783 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3784 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3785 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3786 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3787 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3788 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3789 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3790 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3791 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3792 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3793 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3794 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3795 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3796 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3797 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3798 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3799 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3800
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3801 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3802 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3803 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3804 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3805 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3806 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3807
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3808 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3809 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3810 /* USB_OTG */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3811 /* */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3812 /******************************************************************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3813 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3814 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3815 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3816 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3817 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3818 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3819 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3820 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3821 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3822 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3823 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3824
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3825 /******************** Bit definition forUSB_OTG_HCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3826
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3827 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3828 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3829 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3830 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3831
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3832 /******************** Bit definition forUSB_OTG_DCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3833
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3834 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3835 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3836 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3837 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3838
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3839 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3840 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3841 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3842 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3843 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3844 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3845 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3846 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3847
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3848 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3849 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3850 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3851
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3852 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3853 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3854 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3855
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3856 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3857 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3858 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3859 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3860
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3861 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3862 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3863 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3864 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3865 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3866 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3867 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3868
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3869 /******************** Bit definition forUSB_OTG_DCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3870 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3871 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3872 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3873 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3874
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3875 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3876 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3877 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3878 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3879 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3880 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3881 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3882 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3883 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3884
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3885 /******************** Bit definition forUSB_OTG_HFIR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3886 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3887
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3888 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3889 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3890 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3891
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3892 /******************** Bit definition forUSB_OTG_DSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3893 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3894
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3895 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3896 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3897 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3898 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3899 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3900
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3901 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3902 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3903
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3904 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3905 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3906 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3907 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3908 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3909 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3910 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3911 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3912
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3913 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3914
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3915 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3916 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3917 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3918 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3919 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3920 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3921 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3922
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3923 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3924 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3925 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3926 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3927 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3928 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3929 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3930 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3931 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3932 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3933 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3934 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3935 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3936 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3937 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3938 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3939 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3940 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3941
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3942 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3943 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3944 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3945 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3946 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3947 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3948
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3949 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3950 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3951 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3952 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3953 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3954 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3955 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3956 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3957
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3958 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3959 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3960 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3961 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3962 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3963 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3964 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3965 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3966 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3967
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3968 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3969 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3970
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3971 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3972 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3973 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3974 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3975 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3976 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3977 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3978 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3979 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3980
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3981 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3982 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3983 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3984 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3985 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3986 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3987 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3988 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3989 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3990
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3991 /******************** Bit definition forUSB_OTG_HAINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3992 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3993
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3994 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3995 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3996 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3997 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3998 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
3999 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4000 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4001 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4002
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4003 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4004 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4005 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4006 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4007 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4008 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4009 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4010 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4011 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4012 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4013 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4014 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4015 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4016 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4017 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4018 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4019 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4020 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4021 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4022 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4023 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4024 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4025 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4026 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4027 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4028 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4029 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4030
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4031 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4032 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4033 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4034 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4035 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4036 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4037 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4038 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4039 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4040 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4041 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4042 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4043 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4044 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4045 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4046 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4047 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4048 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4049 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4050 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4051 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4052 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4053 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4054 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4055 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4056 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4057 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4058
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4059 /******************** Bit definition forUSB_OTG_DAINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4060 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4061 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4062
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4063 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4064 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4065
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4066 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4067 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4068 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4069 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4070 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4071
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4072 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4073 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4074 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4075
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4076 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4077
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4078 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4079 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4080 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4081 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4082 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4083 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4084
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4085 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4086 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4087 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4088
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4089 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4090 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4091 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4092 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4093 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4094
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4095 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4096 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4097 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4098 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4099 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4100
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4101 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4102 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4103 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4104 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4105 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4106
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4107 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4108
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4109 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4110 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4111 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4112 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4113 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4114 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4115
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4116 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4117 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4118 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4119
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4120 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4121 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4122 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4123 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4124 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4125
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4126 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4127 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4128 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4129 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4130 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4131
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4132 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4133 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4134 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4135 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4136 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4137
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4138 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4139 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4140
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4141 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4142 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4143
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4144 /******************** Bit definition for OTG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4145 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4146 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4147 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4148 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4149
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4150 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4151 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4152
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4153 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4154 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4155
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4156 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4157 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4158 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4159 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4160 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4161 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4162 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4163 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4164 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4165
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4166 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4167 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4168 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4169 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4170 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4171 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4172 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4173 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4174
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4175 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4176 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4177 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4178
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4179 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4180 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4181 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4182 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4183 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4184 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4185 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4186 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4187 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4188 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4189 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4190
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4191 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4192 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4193 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4194 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4195 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4196 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4197 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4198 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4199 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4200 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4201 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4202
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4203 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4204 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4205
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4206 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4207 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4208 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4209
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4210 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4211 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4212 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4213 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4214 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4215 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4216 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4217
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4218 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4219 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4220 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4221
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4222 /******************** Bit definition forUSB_OTG_CID register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4223 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4224
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4225 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4226 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4227 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4228 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4229 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4230 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4231 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4232 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4233 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4234 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4235
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4236 /******************** Bit definition forUSB_OTG_HPRT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4237 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4238 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4239 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4240 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4241 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4242 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4243 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4244 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4245 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4246
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4247 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4248 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4249 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4250 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4251
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4252 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4253 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4254 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4255 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4256 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4257
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4258 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4259 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4260 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4261
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4262 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4263 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4264 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4265 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4266 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4267 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4268 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4269 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4270 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4271 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4272 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4273 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4274
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4275 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4276 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4277 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4278
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4279 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4280 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4281 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4282 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4283 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4284
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4285 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4286 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4287 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4288 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4289
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4290 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4291 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4292 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4293 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4294 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4295 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4296 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4297 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4298 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4299 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4300 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4301
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4302 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4303 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4304
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4305 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4306 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4307 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4308 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4309 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4310 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4311 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4312
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4313 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4314 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4315 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4316
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4317 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4318 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4319 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4320
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4321 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4322 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4323 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4324 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4325 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4326 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4327 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4328 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4329 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4330 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4331 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4332
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4333 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4334
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4335 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4336 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4337 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4338 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4339 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4340 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4341 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4342 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4343
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4344 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4345 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4346 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4347 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4348 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4349 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4350 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4351 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4352
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4353 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4354 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4355 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4356 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4357 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4358
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4359 /******************** Bit definition forUSB_OTG_HCINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4360 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4361 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4362 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4363 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4364 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4365 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4366 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4367 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4368 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4369 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4370 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4371
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4372 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4373 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4374 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4375 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4376 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4377 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4378 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4379 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4380 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4381 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4382 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4383 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4384
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4385 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4386 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4387 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4388 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4389 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4390 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4391 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4392 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4393 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4394 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4395 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4396 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4397
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4398 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4399
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4400 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4401 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4402 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4403 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4404 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4405 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4406 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4407 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4408 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4409 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4410
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4411 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4412 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4413
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4414 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4415 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4416
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4417 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4418 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4419
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4420 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4421 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4422 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4423
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4424 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4425
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4426 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4427 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4428 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4429 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4430 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4431 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4432 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4433 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4434 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4435 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4436 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4437 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4438 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4439 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4440
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4441 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4442 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4443 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4444 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4445 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4446 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4447 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4448
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4449 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4450
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4451 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4452 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4453
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4454 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4455 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4456 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4457
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4458 /******************** Bit definition for PCGCCTL register ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4459 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4460 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4461 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4462
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4463 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4464 * @}
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4465 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4466
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4467 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4468 * @}
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4469 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4470
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4471 /** @addtogroup Exported_macros
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4472 * @{
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4473 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4474
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4475 /******************************* ADC Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4476 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4477
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4478 /******************************* CRC Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4479 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4480
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4481 /******************************** DMA Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4482 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4483 ((INSTANCE) == DMA1_Stream1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4484 ((INSTANCE) == DMA1_Stream2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4485 ((INSTANCE) == DMA1_Stream3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4486 ((INSTANCE) == DMA1_Stream4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4487 ((INSTANCE) == DMA1_Stream5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4488 ((INSTANCE) == DMA1_Stream6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4489 ((INSTANCE) == DMA1_Stream7) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4490 ((INSTANCE) == DMA2_Stream0) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4491 ((INSTANCE) == DMA2_Stream1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4492 ((INSTANCE) == DMA2_Stream2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4493 ((INSTANCE) == DMA2_Stream3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4494 ((INSTANCE) == DMA2_Stream4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4495 ((INSTANCE) == DMA2_Stream5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4496 ((INSTANCE) == DMA2_Stream6) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4497 ((INSTANCE) == DMA2_Stream7))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4498
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4499 /******************************* GPIO Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4500 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4501 ((INSTANCE) == GPIOB) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4502 ((INSTANCE) == GPIOC) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4503 ((INSTANCE) == GPIOD) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4504 ((INSTANCE) == GPIOE) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4505 ((INSTANCE) == GPIOH))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4506
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4507 /******************************** I2C Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4508 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4509 ((INSTANCE) == I2C2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4510 ((INSTANCE) == I2C3))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4511
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4512 /******************************** I2S Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4513 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4514 ((INSTANCE) == SPI3))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4515
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4516 /*************************** I2S Extended Instances ***************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4517 #define IS_I2S_ALL_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4518 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4519 ((INSTANCE) == I2S2ext) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4520 ((INSTANCE) == I2S3ext))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4521
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4522 /****************************** RTC Instances *********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4523 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4524
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4525 /******************************** SPI Instances *******************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4526 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4527 ((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4528 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4529 ((INSTANCE) == SPI4))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4530
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4531 /*************************** SPI Extended Instances ***************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4532 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4533 ((INSTANCE) == SPI2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4534 ((INSTANCE) == SPI3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4535 ((INSTANCE) == I2S2ext) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4536 ((INSTANCE) == I2S3ext))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4537
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4538 /****************** TIM Instances : All supported instances *******************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4539 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4540 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4541 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4542 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4543 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4544 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4545 ((INSTANCE) == TIM10) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4546 ((INSTANCE) == TIM11))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4547
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4548 /************* TIM Instances : at least 1 capture/compare channel *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4549 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4550 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4551 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4552 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4553 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4554 ((INSTANCE) == TIM9) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4555 ((INSTANCE) == TIM10) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4556 ((INSTANCE) == TIM11))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4557
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4558 /************ TIM Instances : at least 2 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4559 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4560 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4561 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4562 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4563 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4564 ((INSTANCE) == TIM9))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4565
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4566 /************ TIM Instances : at least 3 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4567 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4568 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4569 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4570 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4571 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4572
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4573 /************ TIM Instances : at least 4 capture/compare channels *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4574 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4575 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4576 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4577 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4578 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4579
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4580 /******************** TIM Instances : Advanced-control timers *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4581 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4582
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4583 /******************* TIM Instances : Timer input XOR function *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4584 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4585 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4586 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4587 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4588 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4589
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4590 /****************** TIM Instances : DMA requests generation (UDE) *************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4591 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4592 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4593 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4594 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4595 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4596
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4597 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4598 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4599 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4600 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4601 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4602 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4603
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4604 /************ TIM Instances : DMA requests generation (COMDE) *****************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4605 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4606 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4607 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4608 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4609 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4610
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4611 /******************** TIM Instances : DMA burst feature ***********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4612 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4613 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4614 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4615 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4616 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4617
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4618 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4619 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4620 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4621 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4622 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4623 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4624 ((INSTANCE) == TIM9))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4625
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4626 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4627 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4628 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4629 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4630 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4631 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4632 ((INSTANCE) == TIM9))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4633
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4634 /********************** TIM Instances : 32 bit Counter ************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4635 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4636 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4637
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4638 /***************** TIM Instances : external trigger input availabe ************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4639 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4640 ((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4641 ((INSTANCE) == TIM3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4642 ((INSTANCE) == TIM4) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4643 ((INSTANCE) == TIM5))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4644
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4645 /****************** TIM Instances : remapping capability **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4646 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4647 ((INSTANCE) == TIM5) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4648 ((INSTANCE) == TIM11))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4649
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4650 /******************* TIM Instances : output(s) available **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4651 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4652 ((((INSTANCE) == TIM1) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4653 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4654 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4655 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4656 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4657 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4658 (((INSTANCE) == TIM2) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4659 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4660 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4661 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4662 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4663 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4664 (((INSTANCE) == TIM3) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4665 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4666 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4667 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4668 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4669 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4670 (((INSTANCE) == TIM4) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4671 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4672 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4673 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4674 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4675 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4676 (((INSTANCE) == TIM5) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4677 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4678 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4679 ((CHANNEL) == TIM_CHANNEL_3) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4680 ((CHANNEL) == TIM_CHANNEL_4))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4681 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4682 (((INSTANCE) == TIM9) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4683 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4684 ((CHANNEL) == TIM_CHANNEL_2))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4685 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4686 (((INSTANCE) == TIM10) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4687 (((CHANNEL) == TIM_CHANNEL_1))) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4688 || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4689 (((INSTANCE) == TIM11) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4690 (((CHANNEL) == TIM_CHANNEL_1))))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4691
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4692 /************ TIM Instances : complementary output(s) available ***************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4693 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4694 ((((INSTANCE) == TIM1) && \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4695 (((CHANNEL) == TIM_CHANNEL_1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4696 ((CHANNEL) == TIM_CHANNEL_2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4697 ((CHANNEL) == TIM_CHANNEL_3))))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4698
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4699 /******************** USART Instances : Synchronous mode **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4700 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4701 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4702 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4703
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4704 /******************** UART Instances : Asynchronous mode **********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4705 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4706 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4707 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4708
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4709 /****************** UART Instances : Hardware Flow control ********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4710 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4711 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4712 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4713
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4714 /********************* UART Instances : Smard card mode ***********************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4715 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4716 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4717 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4718
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4719 /*********************** UART Instances : IRDA mode ***************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4720 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4721 ((INSTANCE) == USART2) || \
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4722 ((INSTANCE) == USART6))
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4723
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4724 /****************************** IWDG Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4725 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4726
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4727 /****************************** WWDG Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4728 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4729
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4730 /****************************** SDIO Instances ********************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4731 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4732
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4733 /****************************** USB Exported Constants ************************/
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4734 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4735 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4 /* Including EP0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4736 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4 /* Including EP0 */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4737 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280 /* in Bytes */
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4738
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4739 /**
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4740 * @}
5f11787b4f42 include in ostc4 repository
heinrichsweikamp
parents:
diff changeset
4741 */
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4742
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4743 /**
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4744 * @}
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4745 */
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4746
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4747 /**
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4748 * @}
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4749 */
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4750
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4751 #ifdef __cplusplus
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4752 }
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4753 #endif /* __cplusplus */
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4754
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4755 #endif /* __STM32F401xC_H */
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4756
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4757
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4758
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4759 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/