38
+ − 1 /**
+ − 2 ******************************************************************************
+ − 3 * @file system_stm32f4xx.c
+ − 4 * @author MCD Application Team
+ − 5 * @version V1.1.0
+ − 6 * @date 26-June-2014
+ − 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ − 8 *
+ − 9 * This file provides two functions and one global variable to be called from
+ − 10 * user application:
+ − 11 * - SystemInit(): This function is called at startup just after reset and
+ − 12 * before branch to main program. This call is made inside
+ − 13 * the "startup_stm32f4xx.s" file.
+ − 14 *
+ − 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ − 16 * by the user application to setup the SysTick
+ − 17 * timer or configure other parameters.
+ − 18 *
+ − 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ − 20 * be called whenever the core clock is changed
+ − 21 * during program execution.
+ − 22 *
+ − 23 *
+ − 24 ******************************************************************************
+ − 25 * @attention
+ − 26 *
+ − 27 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
+ − 28 *
+ − 29 * Redistribution and use in source and binary forms, with or without modification,
+ − 30 * are permitted provided that the following conditions are met:
+ − 31 * 1. Redistributions of source code must retain the above copyright notice,
+ − 32 * this list of conditions and the following disclaimer.
+ − 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
+ − 34 * this list of conditions and the following disclaimer in the documentation
+ − 35 * and/or other materials provided with the distribution.
+ − 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ − 37 * may be used to endorse or promote products derived from this software
+ − 38 * without specific prior written permission.
+ − 39 *
+ − 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ − 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ − 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ − 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ − 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ − 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ − 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ − 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ − 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ − 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ − 50 *
+ − 51 ******************************************************************************
+ − 52 */
+ − 53
+ − 54 /** @addtogroup CMSIS
+ − 55 * @{
+ − 56 */
+ − 57
+ − 58 /** @addtogroup stm32f4xx_system
+ − 59 * @{
+ − 60 */
+ − 61
+ − 62 /** @addtogroup STM32F4xx_System_Private_Includes
+ − 63 * @{
+ − 64 */
+ − 65
+ − 66 #include <stdint.h>
+ − 67
+ − 68 #include "stm32f4xx_hal.h"
+ − 69
+ − 70 #if !defined (HSE_VALUE)
+ − 71 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+ − 72 #endif /* HSE_VALUE */
+ − 73
+ − 74 #if !defined (HSI_VALUE)
+ − 75 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+ − 76 #endif /* HSI_VALUE */
+ − 77
+ − 78 /**
+ − 79 * @}
+ − 80 */
+ − 81
+ − 82 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ − 83 * @{
+ − 84 */
+ − 85
+ − 86 /**
+ − 87 * @}
+ − 88 */
+ − 89
+ − 90 /** @addtogroup STM32F4xx_System_Private_Defines
+ − 91 * @{
+ − 92 */
+ − 93
+ − 94 /************************* Miscellaneous Configuration ************************/
+ − 95
+ − 96 /*!< Uncomment the following line if you need to relocate your vector Table in
+ − 97 Internal SRAM. */
+ − 98 /* #define VECT_TAB_SRAM */
+ − 99 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ − 100 This value must be a multiple of 0x200. */
+ − 101 /******************************************************************************/
+ − 102
+ − 103 /**
+ − 104 * @}
+ − 105 */
+ − 106
+ − 107 /** @addtogroup STM32F4xx_System_Private_Macros
+ − 108 * @{
+ − 109 */
+ − 110
+ − 111 /**
+ − 112 * @}
+ − 113 */
+ − 114
+ − 115 /** @addtogroup STM32F4xx_System_Private_Variables
+ − 116 * @{
+ − 117 */
+ − 118 /* This variable is updated in three ways:
+ − 119 1) by calling CMSIS function SystemCoreClockUpdate()
+ − 120 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ − 121 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ − 122 Note: If you use this function to configure the system clock; then there
+ − 123 is no need to call the 2 first functions listed above, since SystemCoreClock
+ − 124 variable is updated automatically.
+ − 125 */
131
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+ − 126 uint32_t SystemCoreClock = 16000000;
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+ − 127 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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+ − 128 const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
38
+ − 129 /**
+ − 130 * @}
+ − 131 */
+ − 132
+ − 133 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ − 134 * @{
+ − 135 */
+ − 136
+ − 137 /**
+ − 138 * @}
+ − 139 */
+ − 140
+ − 141 /** @addtogroup STM32F4xx_System_Private_Functions
+ − 142 * @{
+ − 143 */
+ − 144
+ − 145 /**
+ − 146 * @brief Setup the microcontroller system
+ − 147 * Initialize the FPU setting, vector table location and External memory
+ − 148 * configuration.
+ − 149 * @param None
+ − 150 * @retval None
+ − 151 */
+ − 152 void SystemInit(void)
+ − 153 {
+ − 154 /* FPU settings ------------------------------------------------------------*/
+ − 155 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ − 156 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ − 157 #endif
+ − 158 /* Reset the RCC clock configuration to the default reset state ------------*/
+ − 159 /* Set HSION bit */
+ − 160 RCC->CR |= (uint32_t)0x00000001;
+ − 161
+ − 162 /* Reset CFGR register */
+ − 163 RCC->CFGR = 0x00000000;
+ − 164
+ − 165 /* Reset HSEON, CSSON and PLLON bits */
+ − 166 RCC->CR &= (uint32_t)0xFEF6FFFF;
+ − 167
+ − 168 /* Reset PLLCFGR register */
+ − 169 RCC->PLLCFGR = 0x24003010;
+ − 170
+ − 171 /* Reset HSEBYP bit */
+ − 172 RCC->CR &= (uint32_t)0xFFFBFFFF;
+ − 173
+ − 174 /* Disable all interrupts */
+ − 175 RCC->CIR = 0x00000000;
+ − 176
+ − 177 /* Configure the Vector Table location add offset address ------------------*/
+ − 178 #ifdef VECT_TAB_SRAM
+ − 179 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+ − 180 #else
+ − 181 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+ − 182 #endif
+ − 183 }
+ − 184
+ − 185 /**
+ − 186 * @brief Update SystemCoreClock variable according to Clock Register Values.
+ − 187 * The SystemCoreClock variable contains the core clock (HCLK), it can
+ − 188 * be used by the user application to setup the SysTick timer or configure
+ − 189 * other parameters.
+ − 190 *
+ − 191 * @note Each time the core clock (HCLK) changes, this function must be called
+ − 192 * to update SystemCoreClock variable value. Otherwise, any configuration
+ − 193 * based on this variable will be incorrect.
+ − 194 *
+ − 195 * @note - The system frequency computed by this function is not the real
+ − 196 * frequency in the chip. It is calculated based on the predefined
+ − 197 * constant and the selected clock source:
+ − 198 *
+ − 199 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ − 200 *
+ − 201 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ − 202 *
+ − 203 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ − 204 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ − 205 *
+ − 206 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ − 207 * 16 MHz) but the real value may vary depending on the variations
+ − 208 * in voltage and temperature.
+ − 209 *
+ − 210 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ − 211 * depends on the application requirements), user has to ensure that HSE_VALUE
+ − 212 * is same as the real frequency of the crystal used. Otherwise, this function
+ − 213 * may have wrong result.
+ − 214 *
+ − 215 * - The result of this function could be not correct when using fractional
+ − 216 * value for HSE crystal.
+ − 217 *
+ − 218 * @param None
+ − 219 * @retval None
+ − 220 */
+ − 221 void SystemCoreClockUpdate(void)
+ − 222 {
+ − 223 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+ − 224
+ − 225 /* Get SYSCLK source -------------------------------------------------------*/
+ − 226 tmp = RCC->CFGR & RCC_CFGR_SWS;
+ − 227
+ − 228 switch (tmp)
+ − 229 {
+ − 230 case 0x00: /* HSI used as system clock source */
+ − 231 SystemCoreClock = HSI_VALUE;
+ − 232 break;
+ − 233 case 0x04: /* HSE used as system clock source */
+ − 234 SystemCoreClock = HSE_VALUE;
+ − 235 break;
+ − 236 case 0x08: /* PLL used as system clock source */
+ − 237
+ − 238 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ − 239 SYSCLK = PLL_VCO / PLL_P
+ − 240 */
+ − 241 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ − 242 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+ − 243
+ − 244 if (pllsource != 0)
+ − 245 {
+ − 246 /* HSE used as PLL clock source */
+ − 247 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ − 248 }
+ − 249 else
+ − 250 {
+ − 251 /* HSI used as PLL clock source */
+ − 252 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ − 253 }
+ − 254
+ − 255 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ − 256 SystemCoreClock = pllvco/pllp;
+ − 257 break;
+ − 258 default:
+ − 259 SystemCoreClock = HSI_VALUE;
+ − 260 break;
+ − 261 }
+ − 262 /* Compute HCLK frequency --------------------------------------------------*/
+ − 263 /* Get HCLK prescaler */
+ − 264 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ − 265 /* HCLK frequency */
+ − 266 SystemCoreClock >>= tmp;
+ − 267 }
+ − 268
+ − 269 /**
+ − 270 * @}
+ − 271 */
+ − 272
+ − 273 /**
+ − 274 * @}
+ − 275 */
+ − 276
+ − 277 /**
+ − 278 * @}
+ − 279 */
+ − 280 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
