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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h @ 970:3123aa8723fd Evo_2_23

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Old / new BT module communication: The old / new BT module do have a sligthly different command set. To keep them compatible a function has been added which returns, based on the HW identification, the command string which matches to the module. In case a command is not supported the value 0 is returned and the calling function may react. E.g. with skipping of configuration steps like it is done now for the new module.
author Ideenmodellierer
date Sun, 19 Jan 2025 20:55:30 +0100 (2 months ago)
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_spi.h
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4 * @author MCD Application Team
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5 * @brief Header file of SPI HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_SPI_H
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38 #define __STM32F4xx_HAL_SPI_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup SPI
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56 /** @defgroup SPI_Exported_Types SPI Exported Types
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57 * @{
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58 */
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59
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60 /**
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61 * @brief SPI Configuration Structure definition
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62 */
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63 typedef struct
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64 {
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65 uint32_t Mode; /*!< Specifies the SPI operating mode.
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66 This parameter can be a value of @ref SPI_Mode */
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67
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68 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
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69 This parameter can be a value of @ref SPI_Direction */
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70
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71 uint32_t DataSize; /*!< Specifies the SPI data size.
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72 This parameter can be a value of @ref SPI_Data_Size */
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73
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74 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
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75 This parameter can be a value of @ref SPI_Clock_Polarity */
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76
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77 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
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78 This parameter can be a value of @ref SPI_Clock_Phase */
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79
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80 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
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81 hardware (NSS pin) or by software using the SSI bit.
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82 This parameter can be a value of @ref SPI_Slave_Select_management */
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83
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84 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
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85 used to configure the transmit and receive SCK clock.
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86 This parameter can be a value of @ref SPI_BaudRate_Prescaler
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87 @note The communication clock is derived from the master
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88 clock. The slave clock does not need to be set. */
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89
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90 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
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91 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
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92
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93 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
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94 This parameter can be a value of @ref SPI_TI_mode */
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95
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96 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
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97 This parameter can be a value of @ref SPI_CRC_Calculation */
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98
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99 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
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100 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
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101 }SPI_InitTypeDef;
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102
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103 /**
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104 * @brief HAL SPI State structure definition
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105 */
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106 typedef enum
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107 {
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108 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
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109 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
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110 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
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111 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
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112 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
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113 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
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114 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
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115 }HAL_SPI_StateTypeDef;
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116
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117 /**
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118 * @brief SPI handle Structure definition
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119 */
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120 typedef struct __SPI_HandleTypeDef
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121 {
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122 SPI_TypeDef *Instance; /* SPI registers base address */
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123
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124 SPI_InitTypeDef Init; /* SPI communication parameters */
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125
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126 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
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127
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128 uint16_t TxXferSize; /* SPI Tx Transfer size */
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129
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130 __IO uint16_t TxXferCount; /* SPI Tx Transfer Counter */
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131
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132 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
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133
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134 uint16_t RxXferSize; /* SPI Rx Transfer size */
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135
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136 __IO uint16_t RxXferCount; /* SPI Rx Transfer Counter */
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137
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138 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
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139
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140 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
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141
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142 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA Handle parameters */
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143
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144 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA Handle parameters */
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145
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146 HAL_LockTypeDef Lock; /* Locking object */
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147
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148 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
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149
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150 __IO uint32_t ErrorCode; /* SPI Error code */
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151
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152 }SPI_HandleTypeDef;
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153
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154 /**
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155 * @}
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156 */
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157
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158 /* Exported constants --------------------------------------------------------*/
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159 /** @defgroup SPI_Exported_Constants SPI Exported Constants
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160 * @{
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161 */
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162
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163 /** @defgroup SPI_Error_Code SPI Error Code
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164 * @{
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165 */
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166 #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
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167 #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
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168 #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
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169 #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
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170 #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
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171 #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
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172 #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
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173 /**
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174 * @}
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175 */
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176
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177 /** @defgroup SPI_Mode SPI Mode
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178 * @{
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179 */
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180 #define SPI_MODE_SLAVE 0x00000000U
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181 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
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182 /**
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183 * @}
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184 */
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185
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186 /** @defgroup SPI_Direction SPI Direction Mode
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187 * @{
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188 */
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189 #define SPI_DIRECTION_2LINES 0x00000000U
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190 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
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191 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
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192 /**
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193 * @}
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194 */
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195
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196 /** @defgroup SPI_Data_Size SPI Data Size
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197 * @{
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198 */
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199 #define SPI_DATASIZE_8BIT 0x00000000U
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200 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
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201 /**
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202 * @}
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203 */
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204
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205 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
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206 * @{
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207 */
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208 #define SPI_POLARITY_LOW 0x00000000U
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209 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
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210 /**
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211 * @}
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212 */
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213
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214 /** @defgroup SPI_Clock_Phase SPI Clock Phase
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215 * @{
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216 */
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217 #define SPI_PHASE_1EDGE 0x00000000U
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218 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
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219 /**
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220 * @}
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221 */
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222
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223 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
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224 * @{
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225 */
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226 #define SPI_NSS_SOFT SPI_CR1_SSM
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227 #define SPI_NSS_HARD_INPUT 0x00000000U
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228 #define SPI_NSS_HARD_OUTPUT 0x00040000U
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229 /**
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230 * @}
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231 */
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232
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233 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
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234 * @{
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235 */
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236 #define SPI_BAUDRATEPRESCALER_2 0x00000000U
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237 #define SPI_BAUDRATEPRESCALER_4 0x00000008U
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238 #define SPI_BAUDRATEPRESCALER_8 0x00000010U
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239 #define SPI_BAUDRATEPRESCALER_16 0x00000018U
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240 #define SPI_BAUDRATEPRESCALER_32 0x00000020U
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241 #define SPI_BAUDRATEPRESCALER_64 0x00000028U
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242 #define SPI_BAUDRATEPRESCALER_128 0x00000030U
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243 #define SPI_BAUDRATEPRESCALER_256 0x00000038U
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244 /**
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245 * @}
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246 */
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247
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248 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
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249 * @{
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250 */
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251 #define SPI_FIRSTBIT_MSB 0x00000000U
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252 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
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253 /**
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254 * @}
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255 */
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256
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257 /** @defgroup SPI_TI_mode SPI TI Mode
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258 * @{
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259 */
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260 #define SPI_TIMODE_DISABLE 0x00000000U
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261 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
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262 /**
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263 * @}
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264 */
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265
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266 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
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267 * @{
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268 */
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269 #define SPI_CRCCALCULATION_DISABLE 0x00000000U
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270 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
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271 /**
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272 * @}
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273 */
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274
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275 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
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276 * @{
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277 */
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278 #define SPI_IT_TXE SPI_CR2_TXEIE
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279 #define SPI_IT_RXNE SPI_CR2_RXNEIE
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280 #define SPI_IT_ERR SPI_CR2_ERRIE
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281 /**
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282 * @}
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283 */
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284
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285 /** @defgroup SPI_Flags_definition SPI Flags Definition
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286 * @{
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287 */
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288 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
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289 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
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290 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
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291 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
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292 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
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293 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
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294 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
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295 /**
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296 * @}
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297 */
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298
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299 /**
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300 * @}
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301 */
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302
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303 /* Exported macro ------------------------------------------------------------*/
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304 /** @defgroup SPI_Exported_Macros SPI Exported Macros
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305 * @{
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306 */
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307
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308 /** @brief Reset SPI handle state.
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309 * @param __HANDLE__ specifies the SPI Handle.
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310 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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311 * @retval None
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312 */
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313 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
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314
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315 /** @brief Enable or disable the specified SPI interrupts.
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316 * @param __HANDLE__ specifies the SPI Handle.
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317 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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318 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
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319 * This parameter can be one of the following values:
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320 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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321 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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322 * @arg SPI_IT_ERR: Error interrupt enable
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323 * @retval None
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324 */
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325 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
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326 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
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327
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328 /** @brief Check whether the specified SPI interrupt source is enabled or not.
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329 * @param __HANDLE__ specifies the SPI Handle.
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330 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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331 * @param __INTERRUPT__ specifies the SPI interrupt source to check.
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332 * This parameter can be one of the following values:
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333 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
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334 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
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335 * @arg SPI_IT_ERR: Error interrupt enable
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336 * @retval The new state of __IT__ (TRUE or FALSE).
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337 */
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338 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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339
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340 /** @brief Check whether the specified SPI flag is set or not.
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341 * @param __HANDLE__ specifies the SPI Handle.
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342 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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343 * @param __FLAG__ specifies the flag to check.
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344 * This parameter can be one of the following values:
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345 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
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346 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
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347 * @arg SPI_FLAG_CRCERR: CRC error flag
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348 * @arg SPI_FLAG_MODF: Mode fault flag
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349 * @arg SPI_FLAG_OVR: Overrun flag
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350 * @arg SPI_FLAG_BSY: Busy flag
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351 * @arg SPI_FLAG_FRE: Frame format error flag
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352 * @retval The new state of __FLAG__ (TRUE or FALSE).
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353 */
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354 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
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355
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356 /** @brief Clear the SPI CRCERR pending flag.
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357 * @param __HANDLE__ specifies the SPI Handle.
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358 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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359 * @retval None
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360 */
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361 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
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362
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363 /** @brief Clear the SPI MODF pending flag.
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364 * @param __HANDLE__ specifies the SPI Handle.
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365 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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366 * @retval None
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367 */
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368 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
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369 do{ \
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370 __IO uint32_t tmpreg_modf = 0x00U; \
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371 tmpreg_modf = (__HANDLE__)->Instance->SR; \
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372 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
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373 UNUSED(tmpreg_modf); \
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374 } while(0U)
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375
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376 /** @brief Clear the SPI OVR pending flag.
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377 * @param __HANDLE__ specifies the SPI Handle.
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378 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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379 * @retval None
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380 */
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381 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
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382 do{ \
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383 __IO uint32_t tmpreg_ovr = 0x00U; \
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384 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
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385 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
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386 UNUSED(tmpreg_ovr); \
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387 } while(0U)
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388
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389 /** @brief Clear the SPI FRE pending flag.
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390 * @param __HANDLE__ specifies the SPI Handle.
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391 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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392 * @retval None
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393 */
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394 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
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395 do{ \
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396 __IO uint32_t tmpreg_fre = 0x00U; \
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397 tmpreg_fre = (__HANDLE__)->Instance->SR; \
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398 UNUSED(tmpreg_fre); \
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399 }while(0U)
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400
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401 /** @brief Enable the SPI peripheral.
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402 * @param __HANDLE__ specifies the SPI Handle.
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403 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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404 * @retval None
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405 */
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406 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
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407
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408 /** @brief Disable the SPI peripheral.
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409 * @param __HANDLE__ specifies the SPI Handle.
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410 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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411 * @retval None
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412 */
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413 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
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414 /**
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415 * @}
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416 */
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417
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418 /* Exported functions --------------------------------------------------------*/
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419 /** @addtogroup SPI_Exported_Functions
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420 * @{
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421 */
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422
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423 /** @addtogroup SPI_Exported_Functions_Group1
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424 * @{
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425 */
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426 /* Initialization/de-initialization functions **********************************/
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427 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
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428 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
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429 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
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430 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
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431 /**
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432 * @}
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433 */
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434
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435 /** @addtogroup SPI_Exported_Functions_Group2
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436 * @{
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437 */
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438 /* I/O operation functions *****************************************************/
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439 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
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440 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
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441 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
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442 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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443 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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444 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
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445 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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446 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
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447 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
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448 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
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449 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
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450 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
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451 /* Transfer Abort functions */
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452 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
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453 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
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454
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455 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
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456 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
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457 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
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458 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
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459 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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460 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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461 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
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462 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
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463 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
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464 /**
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465 * @}
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466 */
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467
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468 /** @addtogroup SPI_Exported_Functions_Group3
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469 * @{
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470 */
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471 /* Peripheral State and Error functions ***************************************/
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472 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
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473 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
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474 /**
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475 * @}
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476 */
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477
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478 /**
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479 * @}
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480 */
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481
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482 /* Private types -------------------------------------------------------------*/
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483 /* Private variables ---------------------------------------------------------*/
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484 /* Private constants ---------------------------------------------------------*/
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485
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486 /* Private macros ------------------------------------------------------------*/
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487 /** @defgroup SPI_Private_Macros SPI Private Macros
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488 * @{
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489 */
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490
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491 /** @brief Set the SPI transmit-only mode.
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492 * @param __HANDLE__ specifies the SPI Handle.
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493 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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494 * @retval None
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495 */
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496 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
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497
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498 /** @brief Set the SPI receive-only mode.
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499 * @param __HANDLE__ specifies the SPI Handle.
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500 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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501 * @retval None
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502 */
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503 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
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504
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505 /** @brief Reset the CRC calculation of the SPI.
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506 * @param __HANDLE__ specifies the SPI Handle.
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507 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
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508 * @retval None
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509 */
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510 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
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511 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
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512
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513 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
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514 ((MODE) == SPI_MODE_MASTER))
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515
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516 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
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517 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
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518 ((MODE) == SPI_DIRECTION_1LINE))
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519
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520 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
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521
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522 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
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523 ((MODE) == SPI_DIRECTION_1LINE))
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524
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525 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
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526 ((DATASIZE) == SPI_DATASIZE_8BIT))
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527
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528 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
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529 ((CPOL) == SPI_POLARITY_HIGH))
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530
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531 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
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532 ((CPHA) == SPI_PHASE_2EDGE))
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533
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534 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
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535 ((NSS) == SPI_NSS_HARD_INPUT) || \
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536 ((NSS) == SPI_NSS_HARD_OUTPUT))
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537
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538 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
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539 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
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540 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
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541 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
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542 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
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543 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
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544 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
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545 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
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546
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547 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
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548 ((BIT) == SPI_FIRSTBIT_LSB))
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549
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550 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
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551 ((MODE) == SPI_TIMODE_ENABLE))
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552
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553 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
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554 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
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555
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556 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
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557
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558 /**
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559 * @}
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560 */
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561
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562 /* Private functions ---------------------------------------------------------*/
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563 /** @defgroup SPI_Private_Functions SPI Private Functions
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564 * @{
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565 */
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566
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567 /**
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568 * @}
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569 */
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570
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571 /**
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572 * @}
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573 */
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574
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575 /**
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576 * @}
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577 */
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578
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579 #ifdef __cplusplus
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580 }
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581 #endif
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582
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583 #endif /* __STM32F4xx_HAL_SPI_H */
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584
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585 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/