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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_rcc_ex.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief Extension RCC HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities RCC extension peripheral:
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10 * + Extended Peripheral Control functions
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11 *
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12 ******************************************************************************
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13 * @attention
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14 *
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15 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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16 *
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17 * Redistribution and use in source and binary forms, with or without modification,
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18 * are permitted provided that the following conditions are met:
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19 * 1. Redistributions of source code must retain the above copyright notice,
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20 * this list of conditions and the following disclaimer.
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21 * 2. Redistributions in binary form must reproduce the above copyright notice,
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22 * this list of conditions and the following disclaimer in the documentation
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23 * and/or other materials provided with the distribution.
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24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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25 * may be used to endorse or promote products derived from this software
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26 * without specific prior written permission.
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27 *
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28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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38 *
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39 ******************************************************************************
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40 */
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41
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42 /* Includes ------------------------------------------------------------------*/
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43 #include "stm32f4xx_hal.h"
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44
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45 /** @addtogroup STM32F4xx_HAL_Driver
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46 * @{
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47 */
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48
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49 /** @defgroup RCCEx RCCEx
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50 * @brief RCCEx HAL module driver
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51 * @{
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52 */
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53
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54 #ifdef HAL_RCC_MODULE_ENABLED
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55
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56 /* Private typedef -----------------------------------------------------------*/
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57 /* Private define ------------------------------------------------------------*/
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58 /** @addtogroup RCCEx_Private_Constants
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59 * @{
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60 */
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61 #define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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62 #define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
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63 /**
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64 * @}
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65 */
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66 /* Private macro -------------------------------------------------------------*/
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67 /* Private variables ---------------------------------------------------------*/
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68 /* Private function prototypes -----------------------------------------------*/
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69 /* Private functions ---------------------------------------------------------*/
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70 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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71 * @{
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72 */
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73
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74 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
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75 * @brief Extended Peripheral Control functions
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76 *
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77 @verbatim
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78 ===============================================================================
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79 ##### Extended Peripheral Control functions #####
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80 ===============================================================================
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81 [..]
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82 This subsection provides a set of functions allowing to control the RCC Clocks
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83 frequencies.
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84 [..]
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85 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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86 select the RTC clock source; in this case the Backup domain will be reset in
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87 order to modify the RTC Clock source, as consequence RTC registers (including
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88 the backup registers) and RCC_BDCR register are set to their reset values.
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89
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90 @endverbatim
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91 * @{
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92 */
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93 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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94 /**
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95 * @brief Initializes the RCC extended peripherals clocks according to the specified
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96 * parameters in the RCC_PeriphCLKInitTypeDef.
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97 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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98 * contains the configuration information for the Extended Peripherals
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99 * clocks(I2S, SAI, LTDC RTC and TIM).
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100 *
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101 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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102 * the RTC clock source; in this case the Backup domain will be reset in
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103 * order to modify the RTC Clock source, as consequence RTC registers (including
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104 * the backup registers) and RCC_BDCR register are set to their reset values.
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105 *
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106 * @retval HAL status
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107 */
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108 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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109 {
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110 uint32_t tickstart = 0;
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111 uint32_t tmpreg = 0;
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112
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113 /* Check the parameters */
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114 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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115
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116 /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------------*/
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117
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118 /*----------------------- Common configuration SAI/I2S ---------------------------*/
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119 /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
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120 factor is common parameters for both peripherals */
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121 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
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122 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
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123 {
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124 /* check for Parameters */
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125 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
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126
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127 /* Disable the PLLI2S */
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128 __HAL_RCC_PLLI2S_DISABLE();
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129 /* Get tick */
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130 tickstart = HAL_GetTick();
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131 /* Wait till PLLI2S is disabled */
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132 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
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133 {
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134 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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135 {
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136 /* return in case of Timeout detected */
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137 return HAL_TIMEOUT;
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138 }
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139 }
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140
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141 /*---------------------------- I2S configuration -------------------------------*/
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142 /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
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143 only for I2S configuration */
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144 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
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145 {
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146 /* check for Parameters */
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147 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
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148 /* Configure the PLLI2S division factors */
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149 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
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150 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
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151 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
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152 }
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153
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154 /*---------------------------- SAI configuration -------------------------------*/
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155 /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
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156 be added only for SAI configuration */
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157 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
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158 {
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159 /* Check the PLLI2S division factors */
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160 assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
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161 assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
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162
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163 /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
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164 tmpreg = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
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165 /* Configure the PLLI2S division factors */
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166 /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
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167 /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
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168 /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
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169 __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg);
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170 /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
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171 __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
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172 }
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173
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174 /* Enable the PLLI2S */
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175 __HAL_RCC_PLLI2S_ENABLE();
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176 /* Get tick */
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177 tickstart = HAL_GetTick();
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178 /* Wait till PLLI2S is ready */
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179 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
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180 {
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181 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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182 {
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183 /* return in case of Timeout detected */
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184 return HAL_TIMEOUT;
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185 }
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186 }
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187 }
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188
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189 /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
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190
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191 /*----------------------- Common configuration SAI/LTDC --------------------*/
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192 /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
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193 factor is common parameters for both peripherals */
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194 if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
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195 (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
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196 {
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197 /* Check the PLLSAI division factors */
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198 assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
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199
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200 /* Disable PLLSAI Clock */
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201 __HAL_RCC_PLLSAI_DISABLE();
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202 /* Get tick */
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203 tickstart = HAL_GetTick();
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204 /* Wait till PLLSAI is disabled */
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205 while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
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206 {
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207 if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
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208 {
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209 /* return in case of Timeout detected */
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210 return HAL_TIMEOUT;
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211 }
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212 }
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213
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214 /*---------------------------- SAI configuration -------------------------*/
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215 /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
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216 be added only for SAI configuration */
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217 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
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218 {
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219 assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
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220 assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
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221
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222 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
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223 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
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224 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
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225 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
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226 /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
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227 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg);
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228 /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
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229 __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
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230 }
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231
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232 /*---------------------------- LTDC configuration ------------------------*/
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233 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
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234 {
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235 assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
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236 assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
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237
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238 /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
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239 tmpreg = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
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240 /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
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241 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
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242 /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
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243 __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg, PeriphClkInit->PLLSAI.PLLSAIR);
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244 /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
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245 __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
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246 }
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247 /* Enable PLLSAI Clock */
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248 __HAL_RCC_PLLSAI_ENABLE();
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249 /* Get tick */
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250 tickstart = HAL_GetTick();
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251 /* Wait till PLLSAI is ready */
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252 while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
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253 {
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254 if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
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255 {
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256 /* return in case of Timeout detected */
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257 return HAL_TIMEOUT;
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258 }
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259 }
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260 }
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261
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262
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263 /*---------------------------- RTC configuration ---------------------------*/
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264 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
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265 {
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266 /* Enable Power Clock*/
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267 __HAL_RCC_PWR_CLK_ENABLE();
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268
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269 /* Enable write access to Backup domain */
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270 PWR->CR |= PWR_CR_DBP;
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271
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272 /* Get tick */
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273 tickstart = HAL_GetTick();
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274
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275 while((PWR->CR & PWR_CR_DBP) == RESET)
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276 {
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277 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
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278 {
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279 return HAL_TIMEOUT;
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280 }
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281 }
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282
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283 /* Reset the Backup domain only if the RTC Clock source selection is modified */
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284 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
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285 {
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286 /* Store the content of BDCR register before the reset of Backup Domain */
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287 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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288 /* RTC Clock selection can be changed only if the Backup Domain is reset */
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289 __HAL_RCC_BACKUPRESET_FORCE();
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290 __HAL_RCC_BACKUPRESET_RELEASE();
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291 /* Restore the Content of BDCR register */
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292 RCC->BDCR = tmpreg;
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293 }
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294
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295 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
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296 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
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297 {
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298 /* Get tick */
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299 tickstart = HAL_GetTick();
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300
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301 /* Wait till LSE is ready */
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302 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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303 {
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304 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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305 {
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306 return HAL_TIMEOUT;
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307 }
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308 }
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309 }
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310 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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311 }
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312
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313 /*---------------------------- TIM configuration ---------------------------*/
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314 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
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315 {
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316 __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
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317 }
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318 return HAL_OK;
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319 }
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320
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321 /**
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322 * @brief Configures the RCC_OscInitStruct according to the internal
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323 * RCC configuration registers.
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324 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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325 * will be configured.
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326 * @retval None
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327 */
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328 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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329 {
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330 uint32_t tempreg;
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331
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332 /* Set all possible values for the extended clock type parameter------------*/
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333 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
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334
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335 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
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336 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
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337 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
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338 PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
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339 /* Get the PLLSAI Clock configuration -----------------------------------------------*/
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340 PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
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341 PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
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342 PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
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343 /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
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344 PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
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345 PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
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346 PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
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347 /* Get the RTC Clock configuration -----------------------------------------------*/
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348 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
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349 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
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350
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351 if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
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352 {
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353 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
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354 }
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355 else
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356 {
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357 PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
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358 }
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359 }
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360 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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361
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362 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
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363 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
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364 /**
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365 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
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366 * RCC_PeriphCLKInitTypeDef.
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367 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
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368 * contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
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369 *
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370 * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
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371 * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
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372 * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
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373 *
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374 * @retval HAL status
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375 */
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376 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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377 {
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378 uint32_t tickstart = 0;
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379 uint32_t tmpreg = 0;
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380
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381 /* Check the parameters */
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382 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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383
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384 /*---------------------------- I2S configuration ---------------------------*/
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385 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
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386 {
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387 /* check for Parameters */
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388 assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
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389 assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
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390 #if defined(STM32F411xE)
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391 assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
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392 #endif /* STM32F411xE */
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393 /* Disable the PLLI2S */
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394 __HAL_RCC_PLLI2S_DISABLE();
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395 /* Get tick */
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396 tickstart = HAL_GetTick();
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397 /* Wait till PLLI2S is disabled */
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398 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
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399 {
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400 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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401 {
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402 /* return in case of Timeout detected */
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403 return HAL_TIMEOUT;
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404 }
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405 }
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406
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407 #if defined(STM32F411xE)
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408 /* Configure the PLLI2S division factors */
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409 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
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410 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
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411 __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
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412 #else
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413 /* Configure the PLLI2S division factors */
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414 /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
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415 /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
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416 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
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417 #endif /* STM32F411xE */
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418
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419 /* Enable the PLLI2S */
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420 __HAL_RCC_PLLI2S_ENABLE();
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421 /* Get tick */
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422 tickstart = HAL_GetTick();
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423 /* Wait till PLLI2S is ready */
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424 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
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425 {
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426 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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427 {
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428 /* return in case of Timeout detected */
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429 return HAL_TIMEOUT;
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430 }
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431 }
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432 }
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433
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434 /*---------------------------- RTC configuration ---------------------------*/
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435 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
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436 {
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437 /* Enable Power Clock*/
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438 __HAL_RCC_PWR_CLK_ENABLE();
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439
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440 /* Enable write access to Backup domain */
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441 PWR->CR |= PWR_CR_DBP;
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442
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443 /* Get tick */
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444 tickstart = HAL_GetTick();
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445
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446 while((PWR->CR & PWR_CR_DBP) == RESET)
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447 {
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448 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
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449 {
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450 return HAL_TIMEOUT;
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451 }
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452 }
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453
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454 /* Reset the Backup domain only if the RTC Clock source selection is modified */
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455 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
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456 {
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457 /* Store the content of BDCR register before the reset of Backup Domain */
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458 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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459 /* RTC Clock selection can be changed only if the Backup Domain is reset */
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460 __HAL_RCC_BACKUPRESET_FORCE();
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461 __HAL_RCC_BACKUPRESET_RELEASE();
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462 /* Restore the Content of BDCR register */
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463 RCC->BDCR = tmpreg;
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|
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464 }
|
|
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465
|
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466 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
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|
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467 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
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468 {
|
|
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469 /* Get tick */
|
|
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470 tickstart = HAL_GetTick();
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|
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471
|
|
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472 /* Wait till LSE is ready */
|
|
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473 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
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474 {
|
|
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475 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
476 {
|
|
|
477 return HAL_TIMEOUT;
|
|
|
478 }
|
|
|
479 }
|
|
|
480 }
|
|
|
481 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
|
482 }
|
|
|
483
|
|
|
484 return HAL_OK;
|
|
|
485 }
|
|
|
486
|
|
|
487 /**
|
|
|
488 * @brief Configures the RCC_OscInitStruct according to the internal
|
|
|
489 * RCC configuration registers.
|
|
|
490 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
|
|
|
491 * will be configured.
|
|
|
492 * @retval None
|
|
|
493 */
|
|
|
494 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
|
495 {
|
|
|
496 uint32_t tempreg;
|
|
|
497
|
|
|
498 /* Set all possible values for the extended clock type parameter------------*/
|
|
|
499 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
|
|
|
500
|
|
|
501 /* Get the PLLI2S Clock configuration -----------------------------------------------*/
|
|
|
502 PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
|
|
|
503 PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
|
|
|
504 #if defined(STM32F411xE)
|
|
|
505 PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
|
|
|
506 #endif /* STM32F411xE */
|
|
|
507 /* Get the RTC Clock configuration -----------------------------------------------*/
|
|
|
508 tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
|
|
|
509 PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
|
|
|
510
|
|
|
511 }
|
|
|
512 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
|
|
|
513
|
|
|
514 #if defined(STM32F411xE)
|
|
|
515 /**
|
|
|
516 * @brief Select LSE mode
|
|
|
517 *
|
|
|
518 * @note This mode is only available for STM32F411xx devices.
|
|
|
519 *
|
|
|
520 * @param Mode: specifies the LSE mode.
|
|
|
521 * This parameter can be one of the following values:
|
|
|
522 * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
|
|
|
523 * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
|
|
|
524 * @retval None
|
|
|
525 */
|
|
|
526 void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
|
|
|
527 {
|
|
|
528 /* Check the parameters */
|
|
|
529 assert_param(IS_RCC_LSE_MODE(Mode));
|
|
|
530 if(Mode == RCC_LSE_HIGHDRIVE_MODE)
|
|
|
531 {
|
|
|
532 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
|
|
533 }
|
|
|
534 else
|
|
|
535 {
|
|
|
536 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
|
|
|
537 }
|
|
|
538 }
|
|
|
539
|
|
|
540 #endif /* STM32F411xE */
|
|
|
541
|
|
|
542 /**
|
|
|
543 * @}
|
|
|
544 */
|
|
|
545
|
|
|
546 /**
|
|
|
547 * @}
|
|
|
548 */
|
|
|
549
|
|
|
550 #endif /* HAL_RCC_MODULE_ENABLED */
|
|
|
551 /**
|
|
|
552 * @}
|
|
|
553 */
|
|
|
554
|
|
|
555 /**
|
|
|
556 * @}
|
|
|
557 */
|
|
|
558
|
|
|
559 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
