|
38
|
1 /**
|
|
|
2 ******************************************************************************
|
|
|
3 * @file stm32f4xx_hal_pwr_ex.c
|
|
|
4 * @author MCD Application Team
|
|
|
5 * @version V1.2.0
|
|
|
6 * @date 26-December-2014
|
|
|
7 * @brief Extended PWR HAL module driver.
|
|
|
8 * This file provides firmware functions to manage the following
|
|
|
9 * functionalities of PWR extension peripheral:
|
|
|
10 * + Peripheral Extended features functions
|
|
|
11 *
|
|
|
12 ******************************************************************************
|
|
|
13 * @attention
|
|
|
14 *
|
|
|
15 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
|
|
16 *
|
|
|
17 * Redistribution and use in source and binary forms, with or without modification,
|
|
|
18 * are permitted provided that the following conditions are met:
|
|
|
19 * 1. Redistributions of source code must retain the above copyright notice,
|
|
|
20 * this list of conditions and the following disclaimer.
|
|
|
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
|
|
|
22 * this list of conditions and the following disclaimer in the documentation
|
|
|
23 * and/or other materials provided with the distribution.
|
|
|
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
|
|
|
25 * may be used to endorse or promote products derived from this software
|
|
|
26 * without specific prior written permission.
|
|
|
27 *
|
|
|
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
|
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
|
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
|
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
|
|
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
|
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
|
|
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
|
|
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
|
|
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
38 *
|
|
|
39 ******************************************************************************
|
|
|
40 */
|
|
|
41
|
|
|
42 /* Includes ------------------------------------------------------------------*/
|
|
|
43 #include "stm32f4xx_hal.h"
|
|
|
44
|
|
|
45 /** @addtogroup STM32F4xx_HAL_Driver
|
|
|
46 * @{
|
|
|
47 */
|
|
|
48
|
|
|
49 /** @defgroup PWREx PWREx
|
|
|
50 * @brief PWR HAL module driver
|
|
|
51 * @{
|
|
|
52 */
|
|
|
53
|
|
|
54 #ifdef HAL_PWR_MODULE_ENABLED
|
|
|
55
|
|
|
56 /* Private typedef -----------------------------------------------------------*/
|
|
|
57 /* Private define ------------------------------------------------------------*/
|
|
|
58 /** @addtogroup PWREx_Private_Constants
|
|
|
59 * @{
|
|
|
60 */
|
|
|
61 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
|
|
|
62 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
|
|
|
63 #define PWR_BKPREG_TIMEOUT_VALUE 1000
|
|
|
64 /**
|
|
|
65 * @}
|
|
|
66 */
|
|
|
67
|
|
|
68 /* Private macro -------------------------------------------------------------*/
|
|
|
69 /* Private variables ---------------------------------------------------------*/
|
|
|
70 /* Private function prototypes -----------------------------------------------*/
|
|
|
71 /* Private functions ---------------------------------------------------------*/
|
|
|
72 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
|
|
73 * @{
|
|
|
74 */
|
|
|
75
|
|
|
76 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
|
|
|
77 * @brief Peripheral Extended features functions
|
|
|
78 *
|
|
|
79 @verbatim
|
|
|
80
|
|
|
81 ===============================================================================
|
|
|
82 ##### Peripheral extended features functions #####
|
|
|
83 ===============================================================================
|
|
|
84
|
|
|
85 *** Main and Backup Regulators configuration ***
|
|
|
86 ================================================
|
|
|
87 [..]
|
|
|
88 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
|
|
|
89 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
|
|
|
90 retained even in Standby or VBAT mode when the low power backup regulator
|
|
|
91 is enabled. It can be considered as an internal EEPROM when VBAT is
|
|
|
92 always present. You can use the HAL_PWREx_EnableBkUpReg() function to
|
|
|
93 enable the low power backup regulator.
|
|
|
94
|
|
|
95 (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
|
|
|
96 the backup SRAM is powered from VDD which replaces the VBAT power supply to
|
|
|
97 save battery life.
|
|
|
98
|
|
|
99 (+) The backup SRAM is not mass erased by a tamper event. It is read
|
|
|
100 protected to prevent confidential data, such as cryptographic private
|
|
|
101 key, from being accessed. The backup SRAM can be erased only through
|
|
|
102 the Flash interface when a protection level change from level 1 to
|
|
|
103 level 0 is requested.
|
|
|
104 -@- Refer to the description of Read protection (RDP) in the Flash
|
|
|
105 programming manual.
|
|
|
106
|
|
|
107 (+) The main internal regulator can be configured to have a tradeoff between
|
|
|
108 performance and power consumption when the device does not operate at
|
|
|
109 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
|
|
|
110 macro which configure VOS bit in PWR_CR register
|
|
|
111
|
|
|
112 Refer to the product datasheets for more details.
|
|
|
113
|
|
|
114 *** FLASH Power Down configuration ****
|
|
|
115 =======================================
|
|
|
116 [..]
|
|
|
117 (+) By setting the FPDS bit in the PWR_CR register by using the
|
|
|
118 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
|
|
|
119 down mode when the device enters Stop mode. When the Flash memory
|
|
|
120 is in power down mode, an additional startup delay is incurred when
|
|
|
121 waking up from Stop mode.
|
|
|
122
|
|
|
123 (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL
|
|
|
124 is OFF and the HSI or HSE clock source is selected as system clock.
|
|
|
125 The new value programmed is active only when the PLL is ON.
|
|
|
126 When the PLL is OFF, the voltage scale 3 is automatically selected.
|
|
|
127 Refer to the datasheets for more details.
|
|
|
128
|
|
|
129 *** Over-Drive and Under-Drive configuration ****
|
|
|
130 =================================================
|
|
|
131 [..]
|
|
|
132 (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has
|
|
|
133 2 operating modes available:
|
|
|
134 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given
|
|
|
135 voltage scaling (scale 1, scale 2 or scale 3)
|
|
|
136 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
|
|
|
137 higher frequency than the normal mode for a given voltage scaling (scale 1,
|
|
|
138 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
|
|
|
139 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
|
|
|
140 the sequence described in Reference manual.
|
|
|
141
|
|
|
142 (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator
|
|
|
143 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers
|
|
|
144 and internal SRAM. 2 operating modes are available:
|
|
|
145 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
|
|
|
146 available when the main regulator or the low power regulator is used in Scale 3 or
|
|
|
147 low voltage mode.
|
|
|
148 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
|
|
|
149 available when the main regulator or the low power regulator is in low voltage mode.
|
|
|
150
|
|
|
151 @endverbatim
|
|
|
152 * @{
|
|
|
153 */
|
|
|
154
|
|
|
155 /**
|
|
|
156 * @brief Enables the Backup Regulator.
|
|
|
157 * @retval HAL status
|
|
|
158 */
|
|
|
159 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
|
|
|
160 {
|
|
|
161 uint32_t tickstart = 0;
|
|
|
162
|
|
|
163 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
|
|
|
164
|
|
|
165 /* Get tick */
|
|
|
166 tickstart = HAL_GetTick();
|
|
|
167
|
|
|
168 /* Wait till Backup regulator ready flag is set */
|
|
|
169 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
|
|
|
170 {
|
|
|
171 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
|
|
172 {
|
|
|
173 return HAL_TIMEOUT;
|
|
|
174 }
|
|
|
175 }
|
|
|
176 return HAL_OK;
|
|
|
177 }
|
|
|
178
|
|
|
179 /**
|
|
|
180 * @brief Disables the Backup Regulator.
|
|
|
181 * @retval HAL status
|
|
|
182 */
|
|
|
183 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
|
|
|
184 {
|
|
|
185 uint32_t tickstart = 0;
|
|
|
186
|
|
|
187 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
|
|
|
188
|
|
|
189 /* Get tick */
|
|
|
190 tickstart = HAL_GetTick();
|
|
|
191
|
|
|
192 /* Wait till Backup regulator ready flag is set */
|
|
|
193 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
|
|
|
194 {
|
|
|
195 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
|
|
|
196 {
|
|
|
197 return HAL_TIMEOUT;
|
|
|
198 }
|
|
|
199 }
|
|
|
200 return HAL_OK;
|
|
|
201 }
|
|
|
202
|
|
|
203 /**
|
|
|
204 * @brief Enables the Flash Power Down in Stop mode.
|
|
|
205 * @retval None
|
|
|
206 */
|
|
|
207 void HAL_PWREx_EnableFlashPowerDown(void)
|
|
|
208 {
|
|
|
209 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
|
|
|
210 }
|
|
|
211
|
|
|
212 /**
|
|
|
213 * @brief Disables the Flash Power Down in Stop mode.
|
|
|
214 * @retval None
|
|
|
215 */
|
|
|
216 void HAL_PWREx_DisableFlashPowerDown(void)
|
|
|
217 {
|
|
|
218 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
|
|
|
219 }
|
|
|
220
|
|
|
221 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
|
|
|
222 /**
|
|
|
223 * @brief Enables Main Regulator low voltage mode.
|
|
|
224 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
|
|
|
225 * @retval None
|
|
|
226 */
|
|
|
227 void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
|
|
|
228 {
|
|
|
229 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
|
|
|
230 }
|
|
|
231
|
|
|
232 /**
|
|
|
233 * @brief Disables Main Regulator low voltage mode.
|
|
|
234 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
|
|
|
235 * @retval None
|
|
|
236 */
|
|
|
237 void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
|
|
|
238 {
|
|
|
239 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
|
|
|
240 }
|
|
|
241
|
|
|
242 /**
|
|
|
243 * @brief Enables Low Power Regulator low voltage mode.
|
|
|
244 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
|
|
|
245 * @retval None
|
|
|
246 */
|
|
|
247 void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
|
|
|
248 {
|
|
|
249 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
|
|
|
250 }
|
|
|
251
|
|
|
252 /**
|
|
|
253 * @brief Disables Low Power Regulator low voltage mode.
|
|
|
254 * @note This mode is only available for STM32F401xx/STM32F411xx devices.
|
|
|
255 * @retval None
|
|
|
256 */
|
|
|
257 void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
|
|
|
258 {
|
|
|
259 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
|
|
|
260 }
|
|
|
261
|
|
|
262 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
|
|
|
263
|
|
|
264 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
|
|
265 /**
|
|
|
266 * @brief Activates the Over-Drive mode.
|
|
|
267 * @note This function can be used only for STM32F42xx/STM32F43xx devices.
|
|
|
268 * This mode allows the CPU and the core logic to operate at a higher frequency
|
|
|
269 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
|
|
|
270 * @note It is recommended to enter or exit Over-drive mode when the application is not running
|
|
|
271 * critical tasks and when the system clock source is either HSI or HSE.
|
|
|
272 * During the Over-drive switch activation, no peripheral clocks should be enabled.
|
|
|
273 * The peripheral clocks must be enabled once the Over-drive mode is activated.
|
|
|
274 * @retval HAL status
|
|
|
275 */
|
|
|
276 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
|
|
|
277 {
|
|
|
278 uint32_t tickstart = 0;
|
|
|
279
|
|
|
280 __HAL_RCC_PWR_CLK_ENABLE();
|
|
|
281
|
|
|
282 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
|
|
283 __HAL_PWR_OVERDRIVE_ENABLE();
|
|
|
284
|
|
|
285 /* Get tick */
|
|
|
286 tickstart = HAL_GetTick();
|
|
|
287
|
|
|
288 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
|
|
289 {
|
|
|
290 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
|
291 {
|
|
|
292 return HAL_TIMEOUT;
|
|
|
293 }
|
|
|
294 }
|
|
|
295
|
|
|
296 /* Enable the Over-drive switch */
|
|
|
297 __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
|
|
|
298
|
|
|
299 /* Get tick */
|
|
|
300 tickstart = HAL_GetTick();
|
|
|
301
|
|
|
302 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
|
|
303 {
|
|
|
304 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
|
305 {
|
|
|
306 return HAL_TIMEOUT;
|
|
|
307 }
|
|
|
308 }
|
|
|
309 return HAL_OK;
|
|
|
310 }
|
|
|
311
|
|
|
312 /**
|
|
|
313 * @brief Deactivates the Over-Drive mode.
|
|
|
314 * @note This function can be used only for STM32F42xx/STM32F43xx devices.
|
|
|
315 * This mode allows the CPU and the core logic to operate at a higher frequency
|
|
|
316 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
|
|
|
317 * @note It is recommended to enter or exit Over-drive mode when the application is not running
|
|
|
318 * critical tasks and when the system clock source is either HSI or HSE.
|
|
|
319 * During the Over-drive switch activation, no peripheral clocks should be enabled.
|
|
|
320 * The peripheral clocks must be enabled once the Over-drive mode is activated.
|
|
|
321 * @retval HAL status
|
|
|
322 */
|
|
|
323 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
|
|
|
324 {
|
|
|
325 uint32_t tickstart = 0;
|
|
|
326
|
|
|
327 __HAL_RCC_PWR_CLK_ENABLE();
|
|
|
328
|
|
|
329 /* Disable the Over-drive switch */
|
|
|
330 __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
|
|
|
331
|
|
|
332 /* Get tick */
|
|
|
333 tickstart = HAL_GetTick();
|
|
|
334
|
|
|
335 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
|
|
|
336 {
|
|
|
337 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
|
338 {
|
|
|
339 return HAL_TIMEOUT;
|
|
|
340 }
|
|
|
341 }
|
|
|
342
|
|
|
343 /* Disable the Over-drive */
|
|
|
344 __HAL_PWR_OVERDRIVE_DISABLE();
|
|
|
345
|
|
|
346 /* Get tick */
|
|
|
347 tickstart = HAL_GetTick();
|
|
|
348
|
|
|
349 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
|
|
|
350 {
|
|
|
351 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
|
|
|
352 {
|
|
|
353 return HAL_TIMEOUT;
|
|
|
354 }
|
|
|
355 }
|
|
|
356
|
|
|
357 return HAL_OK;
|
|
|
358 }
|
|
|
359
|
|
|
360 /**
|
|
|
361 * @brief Enters in Under-Drive STOP mode.
|
|
|
362 *
|
|
|
363 * @note This mode is only available for STM32F42xxx/STM324F3xxx devices.
|
|
|
364 *
|
|
|
365 * @note This mode can be selected only when the Under-Drive is already active
|
|
|
366 *
|
|
|
367 * @note This mode is enabled only with STOP low power mode.
|
|
|
368 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
|
|
|
369 * mode is only available when the main regulator or the low power regulator
|
|
|
370 * is in low voltage mode
|
|
|
371 *
|
|
|
372 * @note If the Under-drive mode was enabled, it is automatically disabled after
|
|
|
373 * exiting Stop mode.
|
|
|
374 * When the voltage regulator operates in Under-drive mode, an additional
|
|
|
375 * startup delay is induced when waking up from Stop mode.
|
|
|
376 *
|
|
|
377 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
|
|
378 *
|
|
|
379 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
|
|
|
380 * the HSI RC oscillator is selected as system clock.
|
|
|
381 *
|
|
|
382 * @note When the voltage regulator operates in low power mode, an additional
|
|
|
383 * startup delay is incurred when waking up from Stop mode.
|
|
|
384 * By keeping the internal regulator ON during Stop mode, the consumption
|
|
|
385 * is higher although the startup time is reduced.
|
|
|
386 *
|
|
|
387 * @param Regulator: specifies the regulator state in STOP mode.
|
|
|
388 * This parameter can be one of the following values:
|
|
|
389 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
|
|
|
390 * and Flash memory in power-down when the device is in Stop under-drive mode
|
|
|
391 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
|
|
|
392 * and Flash memory in power-down when the device is in Stop under-drive mode
|
|
|
393 * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
|
|
394 * This parameter can be one of the following values:
|
|
|
395 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
|
|
|
396 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
|
|
|
397 * @retval None
|
|
|
398 */
|
|
|
399 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
|
|
400 {
|
|
|
401 uint32_t tmpreg = 0;
|
|
|
402 uint32_t tickstart = 0;
|
|
|
403
|
|
|
404 /* Check the parameters */
|
|
|
405 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
|
|
|
406 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
|
|
407
|
|
|
408 /* Enable Power ctrl clock */
|
|
|
409 __HAL_RCC_PWR_CLK_ENABLE();
|
|
|
410 /* Enable the Under-drive Mode ---------------------------------------------*/
|
|
|
411 /* Clear Under-drive flag */
|
|
|
412 __HAL_PWR_CLEAR_ODRUDR_FLAG();
|
|
|
413
|
|
|
414 /* Enable the Under-drive */
|
|
|
415 __HAL_PWR_UNDERDRIVE_ENABLE();
|
|
|
416
|
|
|
417 /* Get tick */
|
|
|
418 tickstart = HAL_GetTick();
|
|
|
419
|
|
|
420 /* Wait for UnderDrive mode is ready */
|
|
|
421 while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
|
|
|
422 {
|
|
|
423 if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
|
|
|
424 {
|
|
|
425 return HAL_TIMEOUT;
|
|
|
426 }
|
|
|
427 }
|
|
|
428
|
|
|
429 /* Select the regulator state in STOP mode ---------------------------------*/
|
|
|
430 tmpreg = PWR->CR;
|
|
|
431 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
|
|
|
432 tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
|
|
|
433
|
|
|
434 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
|
|
|
435 tmpreg |= Regulator;
|
|
|
436
|
|
|
437 /* Store the new value */
|
|
|
438 PWR->CR = tmpreg;
|
|
|
439
|
|
|
440 /* Set SLEEPDEEP bit of Cortex System Control Register */
|
|
|
441 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
|
|
442
|
|
|
443 /* Select STOP mode entry --------------------------------------------------*/
|
|
|
444 if(STOPEntry == PWR_SLEEPENTRY_WFI)
|
|
|
445 {
|
|
|
446 /* Request Wait For Interrupt */
|
|
|
447 __WFI();
|
|
|
448 }
|
|
|
449 else
|
|
|
450 {
|
|
|
451 /* Request Wait For Event */
|
|
|
452 __WFE();
|
|
|
453 }
|
|
|
454 /* Reset SLEEPDEEP bit of Cortex System Control Register */
|
|
|
455 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
|
|
456
|
|
|
457 return HAL_OK;
|
|
|
458 }
|
|
|
459
|
|
|
460 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
461 /**
|
|
|
462 * @}
|
|
|
463 */
|
|
|
464
|
|
|
465 /**
|
|
|
466 * @}
|
|
|
467 */
|
|
|
468
|
|
|
469 #endif /* HAL_PWR_MODULE_ENABLED */
|
|
|
470 /**
|
|
|
471 * @}
|
|
|
472 */
|
|
|
473
|
|
|
474 /**
|
|
|
475 * @}
|
|
|
476 */
|
|
|
477
|
|
|
478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
