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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h @ 792:25103f5c7e29

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Avoid a configuration warning after the firmware upgrade by disabling automatic setpoint switching. This makes sure the user's automatic setpoint configuration is not overwritten by the validity checks if the settings are not in the correct spots for the new configuration. Users will have to manually re-create the automatic setpoint switching configuration in the new format; Add a checkbox to 'SPdeco' in the menu - this will make it obvious to users that this setpoint can be disabled. (mikeller)
author heinrichsweikamp
date Sat, 05 Aug 2023 11:52:08 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_pwr.h
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4 * @author MCD Application Team
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5 * @brief Header file of PWR HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_PWR_H
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38 #define __STM32F4xx_HAL_PWR_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup PWR
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56
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57 /** @defgroup PWR_Exported_Types PWR Exported Types
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58 * @{
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59 */
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60
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61 /**
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62 * @brief PWR PVD configuration structure definition
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63 */
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64 typedef struct
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65 {
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66 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
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67 This parameter can be a value of @ref PWR_PVD_detection_level */
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68
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69 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
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70 This parameter can be a value of @ref PWR_PVD_Mode */
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71 }PWR_PVDTypeDef;
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72
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73 /**
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74 * @}
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75 */
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76
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77 /* Exported constants --------------------------------------------------------*/
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78 /** @defgroup PWR_Exported_Constants PWR Exported Constants
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79 * @{
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80 */
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81
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82 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
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83 * @{
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84 */
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85 #define PWR_WAKEUP_PIN1 0x00000100U
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86 /**
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87 * @}
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88 */
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89
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90 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
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91 * @{
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92 */
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93 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
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94 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
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95 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
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96 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
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97 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
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98 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
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99 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
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100 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
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101 (Compare internally to VREFINT) */
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102 /**
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103 * @}
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104 */
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105
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106 /** @defgroup PWR_PVD_Mode PWR PVD Mode
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107 * @{
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108 */
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109 #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */
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110 #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */
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111 #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */
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112 #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
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113 #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */
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114 #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */
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115 #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */
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116 /**
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117 * @}
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118 */
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119
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120
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121 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
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122 * @{
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123 */
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124 #define PWR_MAINREGULATOR_ON 0x00000000U
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125 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
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126 /**
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127 * @}
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128 */
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129
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130 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
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131 * @{
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132 */
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133 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
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134 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
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135 /**
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136 * @}
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137 */
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138
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139 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
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140 * @{
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141 */
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142 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
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143 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
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144 /**
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145 * @}
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146 */
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147
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148 /** @defgroup PWR_Flag PWR Flag
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149 * @{
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150 */
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151 #define PWR_FLAG_WU PWR_CSR_WUF
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152 #define PWR_FLAG_SB PWR_CSR_SBF
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153 #define PWR_FLAG_PVDO PWR_CSR_PVDO
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154 #define PWR_FLAG_BRR PWR_CSR_BRR
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155 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
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156 /**
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157 * @}
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158 */
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159
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160 /**
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161 * @}
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162 */
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163
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164 /* Exported macro ------------------------------------------------------------*/
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165 /** @defgroup PWR_Exported_Macro PWR Exported Macro
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166 * @{
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167 */
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168
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169 /** @brief Check PWR flag is set or not.
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170 * @param __FLAG__ specifies the flag to check.
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171 * This parameter can be one of the following values:
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172 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
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173 * was received from the WKUP pin or from the RTC alarm (Alarm A
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174 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
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175 * An additional wakeup event is detected if the WKUP pin is enabled
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176 * (by setting the EWUP bit) when the WKUP pin level is already high.
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177 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
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178 * resumed from StandBy mode.
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179 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
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180 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
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181 * For this reason, this bit is equal to 0 after Standby or reset
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182 * until the PVDE bit is set.
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183 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
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184 * when the device wakes up from Standby mode or by a system reset
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185 * or power reset.
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186 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
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187 * scaling output selection is ready.
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188 * @retval The new state of __FLAG__ (TRUE or FALSE).
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189 */
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190 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
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191
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192 /** @brief Clear the PWR's pending flags.
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193 * @param __FLAG__ specifies the flag to clear.
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194 * This parameter can be one of the following values:
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195 * @arg PWR_FLAG_WU: Wake Up flag
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196 * @arg PWR_FLAG_SB: StandBy flag
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197 */
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198 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
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199
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200 /**
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201 * @brief Enable the PVD Exti Line 16.
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202 * @retval None.
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203 */
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204 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
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205
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206 /**
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207 * @brief Disable the PVD EXTI Line 16.
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208 * @retval None.
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209 */
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210 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
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211
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212 /**
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213 * @brief Enable event on PVD Exti Line 16.
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214 * @retval None.
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215 */
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216 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
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217
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218 /**
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219 * @brief Disable event on PVD Exti Line 16.
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220 * @retval None.
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221 */
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222 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
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223
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224 /**
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225 * @brief Enable the PVD Extended Interrupt Rising Trigger.
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226 * @retval None.
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227 */
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228 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
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229
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230 /**
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231 * @brief Disable the PVD Extended Interrupt Rising Trigger.
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232 * @retval None.
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233 */
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234 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
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235
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236 /**
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237 * @brief Enable the PVD Extended Interrupt Falling Trigger.
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238 * @retval None.
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239 */
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240 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
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241
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242
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243 /**
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244 * @brief Disable the PVD Extended Interrupt Falling Trigger.
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245 * @retval None.
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246 */
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247 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
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248
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249
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250 /**
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251 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
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252 * @retval None.
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253 */
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254 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
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255 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
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256 }while(0U)
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257
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258 /**
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259 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
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260 * This parameter can be:
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261 * @retval None.
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262 */
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263 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
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264 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
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265 }while(0U)
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266
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267 /**
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268 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
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269 * @retval EXTI PVD Line Status.
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270 */
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271 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
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272
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273 /**
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274 * @brief Clear the PVD Exti flag.
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275 * @retval None.
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276 */
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277 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
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278
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279 /**
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280 * @brief Generates a Software interrupt on PVD EXTI line.
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281 * @retval None
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282 */
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283 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
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284
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285 /**
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286 * @}
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287 */
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288
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289 /* Include PWR HAL Extension module */
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290 #include "stm32f4xx_hal_pwr_ex.h"
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291
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292 /* Exported functions --------------------------------------------------------*/
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293 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
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294 * @{
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295 */
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296
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297 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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298 * @{
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299 */
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300 /* Initialization and de-initialization functions *****************************/
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301 void HAL_PWR_DeInit(void);
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302 void HAL_PWR_EnableBkUpAccess(void);
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303 void HAL_PWR_DisableBkUpAccess(void);
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304 /**
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305 * @}
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306 */
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307
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308 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
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309 * @{
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310 */
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311 /* Peripheral Control functions **********************************************/
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312 /* PVD configuration */
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313 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
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314 void HAL_PWR_EnablePVD(void);
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315 void HAL_PWR_DisablePVD(void);
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316
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317 /* WakeUp pins configuration */
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318 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
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319 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
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320
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321 /* Low Power modes entry */
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322 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
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323 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
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324 void HAL_PWR_EnterSTANDBYMode(void);
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325
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326 /* Power PVD IRQ Handler */
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327 void HAL_PWR_PVD_IRQHandler(void);
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328 void HAL_PWR_PVDCallback(void);
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329
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330 /* Cortex System Control functions *******************************************/
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331 void HAL_PWR_EnableSleepOnExit(void);
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332 void HAL_PWR_DisableSleepOnExit(void);
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333 void HAL_PWR_EnableSEVOnPend(void);
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334 void HAL_PWR_DisableSEVOnPend(void);
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335 /**
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336 * @}
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337 */
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338
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339 /**
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340 * @}
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341 */
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342
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343 /* Private types -------------------------------------------------------------*/
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344 /* Private variables ---------------------------------------------------------*/
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345 /* Private constants ---------------------------------------------------------*/
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346 /** @defgroup PWR_Private_Constants PWR Private Constants
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347 * @{
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348 */
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349
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350 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
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351 * @{
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352 */
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353 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
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354 /**
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355 * @}
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356 */
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357
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358 /** @defgroup PWR_register_alias_address PWR Register alias address
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359 * @{
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360 */
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361 /* ------------- PWR registers bit address in the alias region ---------------*/
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362 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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363 #define PWR_CR_OFFSET 0x00U
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364 #define PWR_CSR_OFFSET 0x04U
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365 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
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366 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
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367 /**
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368 * @}
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369 */
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370
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371 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
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372 * @{
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373 */
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374 /* --- CR Register ---*/
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375 /* Alias word address of DBP bit */
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376 #define DBP_BIT_NUMBER PWR_CR_DBP_Pos
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377 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
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378
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379 /* Alias word address of PVDE bit */
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380 #define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos
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381 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
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382
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383 /* Alias word address of VOS bit */
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384 #define VOS_BIT_NUMBER PWR_CR_VOS_Pos
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385 #define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
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386 /**
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387 * @}
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388 */
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389
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390 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
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391 * @{
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392 */
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393 /* --- CSR Register ---*/
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394 /* Alias word address of EWUP bit */
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395 #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos
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396 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
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397 /**
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398 * @}
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399 */
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400
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401 /**
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402 * @}
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403 */
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404 /* Private macros ------------------------------------------------------------*/
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405 /** @defgroup PWR_Private_Macros PWR Private Macros
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406 * @{
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407 */
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408
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409 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
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410 * @{
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411 */
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412 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
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413 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
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414 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
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415 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
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416 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
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417 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
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418 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
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419 ((MODE) == PWR_PVD_MODE_NORMAL))
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420 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
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421 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
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422 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
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423 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
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424 /**
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425 * @}
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426 */
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427
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428 /**
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429 * @}
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430 */
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431
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432 /**
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433 * @}
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434 */
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435
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436 /**
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437 * @}
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438 */
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439
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440 #ifdef __cplusplus
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441 }
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442 #endif
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443
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444
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445 #endif /* __STM32F4xx_HAL_PWR_H */
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446
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447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/