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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_fsmc.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief FSMC Low Layer HAL module driver.
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8 *
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9 * This file provides firmware functions to manage the following
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10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
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11 * + Initialization/de-initialization functions
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12 * + Peripheral Control functions
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13 * + Peripheral State functions
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14 *
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15 @verbatim
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16 ==============================================================================
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17 ##### FSMC peripheral features #####
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18 ==============================================================================
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19 [..] The Flexible static memory controller (FSMC) includes two memory controllers:
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20 (+) The NOR/PSRAM memory controller
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21 (+) The NAND/PC Card memory controller
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22
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23 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
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24 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
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25 (+) to translate AHB transactions into the appropriate external device protocol.
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26 (+) to meet the access time requirements of the external memory devices.
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27
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28 [..] All external memories share the addresses, data and control signals with the controller.
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29 Each external device is accessed by means of a unique Chip Select. The FSMC performs
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30 only one access at a time to an external device.
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31 The main features of the FSMC controller are the following:
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32 (+) Interface with static-memory mapped devices including:
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33 (++) Static random access memory (SRAM).
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34 (++) Read-only memory (ROM).
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35 (++) NOR Flash memory/OneNAND Flash memory.
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36 (++) PSRAM (4 memory banks).
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37 (++) 16-bit PC Card compatible devices.
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38 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
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39 data.
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40 (+) Independent Chip Select control for each memory bank.
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41 (+) Independent configuration for each memory bank.
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42
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43 @endverbatim
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44 ******************************************************************************
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45 * @attention
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46 *
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47 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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48 *
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49 * Redistribution and use in source and binary forms, with or without modification,
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50 * are permitted provided that the following conditions are met:
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51 * 1. Redistributions of source code must retain the above copyright notice,
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52 * this list of conditions and the following disclaimer.
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53 * 2. Redistributions in binary form must reproduce the above copyright notice,
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54 * this list of conditions and the following disclaimer in the documentation
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55 * and/or other materials provided with the distribution.
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56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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57 * may be used to endorse or promote products derived from this software
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58 * without specific prior written permission.
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59 *
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60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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70 *
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71 ******************************************************************************
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72 */
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73
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74 /* Includes ------------------------------------------------------------------*/
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75 #include "stm32f4xx_hal.h"
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76
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77 /** @addtogroup STM32F4xx_HAL_Driver
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78 * @{
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79 */
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80
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81 /** @defgroup FSMC_LL FSMC Low Layer
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82 * @brief FSMC driver modules
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83 * @{
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84 */
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85
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86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED)
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87 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
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88 /* Private typedef -----------------------------------------------------------*/
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89 /* Private define ------------------------------------------------------------*/
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90 /* Private macro -------------------------------------------------------------*/
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91 /* Private variables ---------------------------------------------------------*/
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92 /* Private function prototypes -----------------------------------------------*/
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93 /* Private functions ---------------------------------------------------------*/
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94 /** @addtogroup FSMC_LL_Private_Functions
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95 * @{
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96 */
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97
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98 /** @addtogroup FSMC_LL_NORSRAM
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99 * @brief NORSRAM Controller functions
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100 *
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101 @verbatim
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102 ==============================================================================
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103 ##### How to use NORSRAM device driver #####
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104 ==============================================================================
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105
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106 [..]
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107 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
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108 to run the NORSRAM external devices.
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109
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110 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
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111 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
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112 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
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113 (+) FSMC NORSRAM bank extended timing configuration using the function
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114 FSMC_NORSRAM_Extended_Timing_Init()
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115 (+) FSMC NORSRAM bank enable/disable write operation using the functions
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116 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
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117
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118 @endverbatim
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119 * @{
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120 */
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121
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122 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
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123 * @brief Initialization and Configuration functions
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124 *
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125 @verbatim
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126 ==============================================================================
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127 ##### Initialization and de_initialization functions #####
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128 ==============================================================================
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129 [..]
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130 This section provides functions allowing to:
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131 (+) Initialize and configure the FSMC NORSRAM interface
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132 (+) De-initialize the FSMC NORSRAM interface
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133 (+) Configure the FSMC clock and associated GPIOs
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134
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135 @endverbatim
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136 * @{
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137 */
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138
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139 /**
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140 * @brief Initialize the FSMC_NORSRAM device according to the specified
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141 * control parameters in the FSMC_NORSRAM_InitTypeDef
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142 * @param Device: Pointer to NORSRAM device instance
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143 * @param Init: Pointer to NORSRAM Initialization structure
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144 * @retval HAL status
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145 */
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146 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
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147 {
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148 uint32_t tmpr = 0;
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149
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150 /* Check the parameters */
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151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
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152 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
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153 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
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154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
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155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
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156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
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157 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
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158 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
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159 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
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160 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
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161 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
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162 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
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163 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
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164
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165 /* Get the BTCR register value */
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166 tmpr = Device->BTCR[Init->NSBank];
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167
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168 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
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169 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
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170 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
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171 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
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172 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
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173 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
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174 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
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175 /* Set NORSRAM device control parameters */
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176 tmpr |= (uint32_t)(Init->DataAddressMux |\
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177 Init->MemoryType |\
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178 Init->MemoryDataWidth |\
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179 Init->BurstAccessMode |\
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180 Init->WaitSignalPolarity |\
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181 Init->WrapMode |\
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182 Init->WaitSignalActive |\
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183 Init->WriteOperation |\
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184 Init->WaitSignal |\
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185 Init->ExtendedMode |\
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186 Init->AsynchronousWait |\
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187 Init->WriteBurst
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188 );
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189
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190 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
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191 {
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192 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
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193 }
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194
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195 Device->BTCR[Init->NSBank] = tmpr;
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196
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197 return HAL_OK;
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198 }
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199
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200 /**
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201 * @brief DeInitialize the FSMC_NORSRAM peripheral
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202 * @param Device: Pointer to NORSRAM device instance
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203 * @param ExDevice: Pointer to NORSRAM extended mode device instance
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204 * @param Bank: NORSRAM bank number
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205 * @retval HAL status
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206 */
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207 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
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208 {
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209 /* Check the parameters */
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210 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
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211 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
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212
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213 /* Disable the FSMC_NORSRAM device */
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214 __FSMC_NORSRAM_DISABLE(Device, Bank);
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215
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216 /* De-initialize the FSMC_NORSRAM device */
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217 /* FSMC_NORSRAM_BANK1 */
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218 if(Bank == FSMC_NORSRAM_BANK1)
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219 {
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220 Device->BTCR[Bank] = 0x000030DB;
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221 }
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222 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
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223 else
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224 {
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225 Device->BTCR[Bank] = 0x000030D2;
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226 }
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227
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228 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
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229 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
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230
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231 return HAL_OK;
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232 }
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233
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234
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235 /**
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236 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
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237 * parameters in the FSMC_NORSRAM_TimingTypeDef
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238 * @param Device: Pointer to NORSRAM device instance
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239 * @param Timing: Pointer to NORSRAM Timing structure
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240 * @param Bank: NORSRAM bank number
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241 * @retval HAL status
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242 */
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243 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
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244 {
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245 uint32_t tmpr = 0;
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246
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247 /* Check the parameters */
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248 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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249 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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250 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
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251 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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252 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
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253 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
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254 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
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255
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256 /* Get the BTCR register value */
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257 tmpr = Device->BTCR[Bank + 1];
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258
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259 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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260 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
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261 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
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262 FSMC_BTR1_ACCMOD));
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263
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264 /* Set FSMC_NORSRAM device timing parameters */
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265 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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266 ((Timing->AddressHoldTime) << 4) |\
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267 ((Timing->DataSetupTime) << 8) |\
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268 ((Timing->BusTurnAroundDuration) << 16) |\
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269 (((Timing->CLKDivision)-1) << 20) |\
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270 (((Timing->DataLatency)-2) << 24) |\
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271 (Timing->AccessMode));
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272
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273 Device->BTCR[Bank + 1] = tmpr;
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274
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275 return HAL_OK;
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276 }
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277
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278 /**
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279 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
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280 * parameters in the FSMC_NORSRAM_TimingTypeDef
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281 * @param Device: Pointer to NORSRAM device instance
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282 * @param Timing: Pointer to NORSRAM Timing structure
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283 * @param Bank: NORSRAM bank number
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284 * @retval HAL status
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285 */
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286 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
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287 {
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288 uint32_t tmpr = 0;
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289
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290 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
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291 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
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292 {
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293 /* Check the parameters */
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294 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
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295 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
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296 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
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297 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
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298 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
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299 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
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300 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
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301
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302 /* Get the BWTR register value */
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303 tmpr = Device->BWTR[Bank];
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304
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305 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
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306 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
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307 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_CLKDIV | FSMC_BWTR1_DATLAT | \
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308 FSMC_BWTR1_ACCMOD));
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309
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310 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
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311 ((Timing->AddressHoldTime) << 4) |\
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312 ((Timing->DataSetupTime) << 8) |\
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313 ((Timing->BusTurnAroundDuration) << 16) |\
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314 (((Timing->CLKDivision)-1) << 20) |\
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315 (((Timing->DataLatency)-2) << 24) |\
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316 (Timing->AccessMode));
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317
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318 Device->BWTR[Bank] = tmpr;
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319 }
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320 else
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321 {
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322 Device->BWTR[Bank] = 0x0FFFFFFF;
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323 }
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324
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325 return HAL_OK;
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326 }
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327 /**
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328 * @}
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329 */
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330
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331 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2
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332 * @brief management functions
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333 *
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334 @verbatim
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335 ==============================================================================
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336 ##### FSMC_NORSRAM Control functions #####
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337 ==============================================================================
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338 [..]
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339 This subsection provides a set of functions allowing to control dynamically
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340 the FSMC NORSRAM interface.
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341
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342 @endverbatim
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343 * @{
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344 */
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345
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346 /**
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347 * @brief Enables dynamically FSMC_NORSRAM write operation.
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348 * @param Device: Pointer to NORSRAM device instance
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349 * @param Bank: NORSRAM bank number
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350 * @retval HAL status
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351 */
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352 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
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353 {
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354 /* Enable write operation */
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355 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE;
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356
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357 return HAL_OK;
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358 }
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359
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360 /**
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361 * @brief Disables dynamically FSMC_NORSRAM write operation.
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362 * @param Device: Pointer to NORSRAM device instance
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363 * @param Bank: NORSRAM bank number
|
|
|
364 * @retval HAL status
|
|
|
365 */
|
|
|
366 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
|
|
|
367 {
|
|
|
368 /* Disable write operation */
|
|
|
369 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE;
|
|
|
370
|
|
|
371 return HAL_OK;
|
|
|
372 }
|
|
|
373 /**
|
|
|
374 * @}
|
|
|
375 */
|
|
|
376
|
|
|
377 /**
|
|
|
378 * @}
|
|
|
379 */
|
|
|
380
|
|
|
381 /** @addtogroup FSMC_LL_NAND
|
|
|
382 * @brief NAND Controller functions
|
|
|
383 *
|
|
|
384 @verbatim
|
|
|
385 ==============================================================================
|
|
|
386 ##### How to use NAND device driver #####
|
|
|
387 ==============================================================================
|
|
|
388 [..]
|
|
|
389 This driver contains a set of APIs to interface with the FSMC NAND banks in order
|
|
|
390 to run the NAND external devices.
|
|
|
391
|
|
|
392 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
|
|
|
393 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
|
|
|
394 (+) FSMC NAND bank common space timing configuration using the function
|
|
|
395 FSMC_NAND_CommonSpace_Timing_Init()
|
|
|
396 (+) FSMC NAND bank attribute space timing configuration using the function
|
|
|
397 FSMC_NAND_AttributeSpace_Timing_Init()
|
|
|
398 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
|
|
|
399 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
|
|
|
400 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
|
|
|
401
|
|
|
402 @endverbatim
|
|
|
403 * @{
|
|
|
404 */
|
|
|
405
|
|
|
406 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1
|
|
|
407 * @brief Initialization and Configuration functions
|
|
|
408 *
|
|
|
409 @verbatim
|
|
|
410 ==============================================================================
|
|
|
411 ##### Initialization and de_initialization functions #####
|
|
|
412 ==============================================================================
|
|
|
413 [..]
|
|
|
414 This section provides functions allowing to:
|
|
|
415 (+) Initialize and configure the FSMC NAND interface
|
|
|
416 (+) De-initialize the FSMC NAND interface
|
|
|
417 (+) Configure the FSMC clock and associated GPIOs
|
|
|
418
|
|
|
419 @endverbatim
|
|
|
420 * @{
|
|
|
421 */
|
|
|
422
|
|
|
423 /**
|
|
|
424 * @brief Initializes the FSMC_NAND device according to the specified
|
|
|
425 * control parameters in the FSMC_NAND_HandleTypeDef
|
|
|
426 * @param Device: Pointer to NAND device instance
|
|
|
427 * @param Init: Pointer to NAND Initialization structure
|
|
|
428 * @retval HAL status
|
|
|
429 */
|
|
|
430 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
|
|
|
431 {
|
|
|
432 uint32_t tmpr = 0;
|
|
|
433
|
|
|
434 /* Check the parameters */
|
|
|
435 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
|
|
|
436 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
|
|
|
437 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
|
|
|
438 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
|
|
|
439 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
|
|
|
440 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
|
|
|
441 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
|
|
|
442
|
|
|
443 if(Init->NandBank == FSMC_NAND_BANK2)
|
|
|
444 {
|
|
|
445 /* Get the NAND bank 2 register value */
|
|
|
446 tmpr = Device->PCR2;
|
|
|
447 }
|
|
|
448 else
|
|
|
449 {
|
|
|
450 /* Get the NAND bank 3 register value */
|
|
|
451 tmpr = Device->PCR3;
|
|
|
452 }
|
|
|
453
|
|
|
454 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
|
|
|
455 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
|
|
|
456 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
|
|
|
457 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
|
|
|
458
|
|
|
459 /* Set NAND device control parameters */
|
|
|
460 tmpr |= (uint32_t)(Init->Waitfeature |\
|
|
|
461 FSMC_PCR_MEMORY_TYPE_NAND |\
|
|
|
462 Init->MemoryDataWidth |\
|
|
|
463 Init->EccComputation |\
|
|
|
464 Init->ECCPageSize |\
|
|
|
465 ((Init->TCLRSetupTime) << 9) |\
|
|
|
466 ((Init->TARSetupTime) << 13));
|
|
|
467
|
|
|
468 if(Init->NandBank == FSMC_NAND_BANK2)
|
|
|
469 {
|
|
|
470 /* NAND bank 2 registers configuration */
|
|
|
471 Device->PCR2 = tmpr;
|
|
|
472 }
|
|
|
473 else
|
|
|
474 {
|
|
|
475 /* NAND bank 3 registers configuration */
|
|
|
476 Device->PCR3 = tmpr;
|
|
|
477 }
|
|
|
478
|
|
|
479 return HAL_OK;
|
|
|
480 }
|
|
|
481
|
|
|
482 /**
|
|
|
483 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
|
|
|
484 * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
|
|
485 * @param Device: Pointer to NAND device instance
|
|
|
486 * @param Timing: Pointer to NAND timing structure
|
|
|
487 * @param Bank: NAND bank number
|
|
|
488 * @retval HAL status
|
|
|
489 */
|
|
|
490 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
|
|
491 {
|
|
|
492 uint32_t tmpr = 0;
|
|
|
493
|
|
|
494 /* Check the parameters */
|
|
|
495 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
|
|
496 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
|
|
497 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
|
|
498 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
|
|
499
|
|
|
500 if(Bank == FSMC_NAND_BANK2)
|
|
|
501 {
|
|
|
502 /* Get the NAND bank 2 register value */
|
|
|
503 tmpr = Device->PMEM2;
|
|
|
504 }
|
|
|
505 else
|
|
|
506 {
|
|
|
507 /* Get the NAND bank 3 register value */
|
|
|
508 tmpr = Device->PMEM3;
|
|
|
509 }
|
|
|
510
|
|
|
511 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
|
|
|
512 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
|
|
|
513 FSMC_PMEM2_MEMHIZ2));
|
|
|
514
|
|
|
515 /* Set FSMC_NAND device timing parameters */
|
|
|
516 tmpr |= (uint32_t)(Timing->SetupTime |\
|
|
|
517 ((Timing->WaitSetupTime) << 8) |\
|
|
|
518 ((Timing->HoldSetupTime) << 16) |\
|
|
|
519 ((Timing->HiZSetupTime) << 24)
|
|
|
520 );
|
|
|
521
|
|
|
522 if(Bank == FSMC_NAND_BANK2)
|
|
|
523 {
|
|
|
524 /* NAND bank 2 registers configuration */
|
|
|
525 Device->PMEM2 = tmpr;
|
|
|
526 }
|
|
|
527 else
|
|
|
528 {
|
|
|
529 /* NAND bank 3 registers configuration */
|
|
|
530 Device->PMEM3 = tmpr;
|
|
|
531 }
|
|
|
532
|
|
|
533 return HAL_OK;
|
|
|
534 }
|
|
|
535
|
|
|
536 /**
|
|
|
537 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
|
|
|
538 * parameters in the FSMC_NAND_PCC_TimingTypeDef
|
|
|
539 * @param Device: Pointer to NAND device instance
|
|
|
540 * @param Timing: Pointer to NAND timing structure
|
|
|
541 * @param Bank: NAND bank number
|
|
|
542 * @retval HAL status
|
|
|
543 */
|
|
|
544 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
|
|
|
545 {
|
|
|
546 uint32_t tmpr = 0;
|
|
|
547
|
|
|
548 /* Check the parameters */
|
|
|
549 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
|
|
|
550 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
|
|
|
551 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
|
|
|
552 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
|
|
|
553
|
|
|
554 if(Bank == FSMC_NAND_BANK2)
|
|
|
555 {
|
|
|
556 /* Get the NAND bank 2 register value */
|
|
|
557 tmpr = Device->PATT2;
|
|
|
558 }
|
|
|
559 else
|
|
|
560 {
|
|
|
561 /* Get the NAND bank 3 register value */
|
|
|
562 tmpr = Device->PATT3;
|
|
|
563 }
|
|
|
564
|
|
|
565 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
|
|
|
566 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
|
|
|
567 FSMC_PATT2_ATTHIZ2));
|
|
|
568
|
|
|
569 /* Set FSMC_NAND device timing parameters */
|
|
|
570 tmpr |= (uint32_t)(Timing->SetupTime |\
|
|
|
571 ((Timing->WaitSetupTime) << 8) |\
|
|
|
572 ((Timing->HoldSetupTime) << 16) |\
|
|
|
573 ((Timing->HiZSetupTime) << 24)
|
|
|
574 );
|
|
|
575
|
|
|
576 if(Bank == FSMC_NAND_BANK2)
|
|
|
577 {
|
|
|
578 /* NAND bank 2 registers configuration */
|
|
|
579 Device->PATT2 = tmpr;
|
|
|
580 }
|
|
|
581 else
|
|
|
582 {
|
|
|
583 /* NAND bank 3 registers configuration */
|
|
|
584 Device->PATT3 = tmpr;
|
|
|
585 }
|
|
|
586
|
|
|
587 return HAL_OK;
|
|
|
588 }
|
|
|
589
|
|
|
590 /**
|
|
|
591 * @brief DeInitializes the FSMC_NAND device
|
|
|
592 * @param Device: Pointer to NAND device instance
|
|
|
593 * @param Bank: NAND bank number
|
|
|
594 * @retval HAL status
|
|
|
595 */
|
|
|
596 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
|
|
597 {
|
|
|
598 /* Disable the NAND Bank */
|
|
|
599 __FSMC_NAND_DISABLE(Device, Bank);
|
|
|
600
|
|
|
601 /* De-initialize the NAND Bank */
|
|
|
602 if(Bank == FSMC_NAND_BANK2)
|
|
|
603 {
|
|
|
604 /* Set the FSMC_NAND_BANK2 registers to their reset values */
|
|
|
605 Device->PCR2 = 0x00000018;
|
|
|
606 Device->SR2 = 0x00000040;
|
|
|
607 Device->PMEM2 = 0xFCFCFCFC;
|
|
|
608 Device->PATT2 = 0xFCFCFCFC;
|
|
|
609 }
|
|
|
610 /* FSMC_Bank3_NAND */
|
|
|
611 else
|
|
|
612 {
|
|
|
613 /* Set the FSMC_NAND_BANK3 registers to their reset values */
|
|
|
614 Device->PCR3 = 0x00000018;
|
|
|
615 Device->SR3 = 0x00000040;
|
|
|
616 Device->PMEM3 = 0xFCFCFCFC;
|
|
|
617 Device->PATT3 = 0xFCFCFCFC;
|
|
|
618 }
|
|
|
619
|
|
|
620 return HAL_OK;
|
|
|
621 }
|
|
|
622 /**
|
|
|
623 * @}
|
|
|
624 */
|
|
|
625
|
|
|
626 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2
|
|
|
627 * @brief management functions
|
|
|
628 *
|
|
|
629 @verbatim
|
|
|
630 ==============================================================================
|
|
|
631 ##### FSMC_NAND Control functions #####
|
|
|
632 ==============================================================================
|
|
|
633 [..]
|
|
|
634 This subsection provides a set of functions allowing to control dynamically
|
|
|
635 the FSMC NAND interface.
|
|
|
636
|
|
|
637 @endverbatim
|
|
|
638 * @{
|
|
|
639 */
|
|
|
640
|
|
|
641 /**
|
|
|
642 * @brief Enables dynamically FSMC_NAND ECC feature.
|
|
|
643 * @param Device: Pointer to NAND device instance
|
|
|
644 * @param Bank: NAND bank number
|
|
|
645 * @retval HAL status
|
|
|
646 */
|
|
|
647 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
|
|
648 {
|
|
|
649 /* Enable ECC feature */
|
|
|
650 if(Bank == FSMC_NAND_BANK2)
|
|
|
651 {
|
|
|
652 Device->PCR2 |= FSMC_PCR2_ECCEN;
|
|
|
653 }
|
|
|
654 else
|
|
|
655 {
|
|
|
656 Device->PCR3 |= FSMC_PCR3_ECCEN;
|
|
|
657 }
|
|
|
658
|
|
|
659 return HAL_OK;
|
|
|
660 }
|
|
|
661
|
|
|
662 /**
|
|
|
663 * @brief Disables dynamically FSMC_NAND ECC feature.
|
|
|
664 * @param Device: Pointer to NAND device instance
|
|
|
665 * @param Bank: NAND bank number
|
|
|
666 * @retval HAL status
|
|
|
667 */
|
|
|
668 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
|
|
|
669 {
|
|
|
670 /* Disable ECC feature */
|
|
|
671 if(Bank == FSMC_NAND_BANK2)
|
|
|
672 {
|
|
|
673 Device->PCR2 &= ~FSMC_PCR2_ECCEN;
|
|
|
674 }
|
|
|
675 else
|
|
|
676 {
|
|
|
677 Device->PCR3 &= ~FSMC_PCR3_ECCEN;
|
|
|
678 }
|
|
|
679
|
|
|
680 return HAL_OK;
|
|
|
681 }
|
|
|
682
|
|
|
683 /**
|
|
|
684 * @brief Disables dynamically FSMC_NAND ECC feature.
|
|
|
685 * @param Device: Pointer to NAND device instance
|
|
|
686 * @param ECCval: Pointer to ECC value
|
|
|
687 * @param Bank: NAND bank number
|
|
|
688 * @param Timeout: Timeout wait value
|
|
|
689 * @retval HAL status
|
|
|
690 */
|
|
|
691 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
|
|
|
692 {
|
|
|
693 uint32_t tickstart = 0;
|
|
|
694
|
|
|
695 /* Check the parameters */
|
|
|
696 assert_param(IS_FSMC_NAND_DEVICE(Device));
|
|
|
697 assert_param(IS_FSMC_NAND_BANK(Bank));
|
|
|
698
|
|
|
699 /* Get tick */
|
|
|
700 tickstart = HAL_GetTick();
|
|
|
701
|
|
|
702 /* Wait until FIFO is empty */
|
|
|
703 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
|
|
|
704 {
|
|
|
705 /* Check for the Timeout */
|
|
|
706 if(Timeout != HAL_MAX_DELAY)
|
|
|
707 {
|
|
|
708 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
|
|
709 {
|
|
|
710 return HAL_TIMEOUT;
|
|
|
711 }
|
|
|
712 }
|
|
|
713 }
|
|
|
714
|
|
|
715 if(Bank == FSMC_NAND_BANK2)
|
|
|
716 {
|
|
|
717 /* Get the ECCR2 register value */
|
|
|
718 *ECCval = (uint32_t)Device->ECCR2;
|
|
|
719 }
|
|
|
720 else
|
|
|
721 {
|
|
|
722 /* Get the ECCR3 register value */
|
|
|
723 *ECCval = (uint32_t)Device->ECCR3;
|
|
|
724 }
|
|
|
725
|
|
|
726 return HAL_OK;
|
|
|
727 }
|
|
|
728
|
|
|
729 /**
|
|
|
730 * @}
|
|
|
731 */
|
|
|
732
|
|
|
733 /**
|
|
|
734 * @}
|
|
|
735 */
|
|
|
736
|
|
|
737 /** @addtogroup FSMC_LL_PCCARD
|
|
|
738 * @brief PCCARD Controller functions
|
|
|
739 *
|
|
|
740 @verbatim
|
|
|
741 ==============================================================================
|
|
|
742 ##### How to use PCCARD device driver #####
|
|
|
743 ==============================================================================
|
|
|
744 [..]
|
|
|
745 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
|
|
|
746 to run the PCCARD/compact flash external devices.
|
|
|
747
|
|
|
748 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
|
|
|
749 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
|
|
|
750 (+) FSMC PCCARD bank common space timing configuration using the function
|
|
|
751 FSMC_PCCARD_CommonSpace_Timing_Init()
|
|
|
752 (+) FSMC PCCARD bank attribute space timing configuration using the function
|
|
|
753 FSMC_PCCARD_AttributeSpace_Timing_Init()
|
|
|
754 (+) FSMC PCCARD bank IO space timing configuration using the function
|
|
|
755 FSMC_PCCARD_IOSpace_Timing_Init()
|
|
|
756
|
|
|
757 @endverbatim
|
|
|
758 * @{
|
|
|
759 */
|
|
|
760
|
|
|
761 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1
|
|
|
762 * @brief Initialization and Configuration functions
|
|
|
763 *
|
|
|
764 @verbatim
|
|
|
765 ==============================================================================
|
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766 ##### Initialization and de_initialization functions #####
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767 ==============================================================================
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768 [..]
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769 This section provides functions allowing to:
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770 (+) Initialize and configure the FSMC PCCARD interface
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771 (+) De-initialize the FSMC PCCARD interface
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772 (+) Configure the FSMC clock and associated GPIOs
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773
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774 @endverbatim
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775 * @{
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776 */
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777
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778 /**
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779 * @brief Initializes the FSMC_PCCARD device according to the specified
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780 * control parameters in the FSMC_PCCARD_HandleTypeDef
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781 * @param Device: Pointer to PCCARD device instance
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782 * @param Init: Pointer to PCCARD Initialization structure
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783 * @retval HAL status
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784 */
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785 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
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786 {
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787 uint32_t tmpr = 0;
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788
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789 /* Check the parameters */
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790 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
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791 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
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792 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
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793
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794 /* Get PCCARD control register value */
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795 tmpr = Device->PCR4;
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796
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797 /* Clear TAR, TCLR, PWAITEN and PWID bits */
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798 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
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799 FSMC_PCR4_PWID));
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800
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801 /* Set FSMC_PCCARD device control parameters */
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802 tmpr |= (uint32_t)(Init->Waitfeature |\
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803 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
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804 (Init->TCLRSetupTime << 9) |\
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805 (Init->TARSetupTime << 13));
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806
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807 Device->PCR4 = tmpr;
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808
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809 return HAL_OK;
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810 }
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811
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812 /**
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813 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
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814 * parameters in the FSMC_NAND_PCC_TimingTypeDef
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815 * @param Device: Pointer to PCCARD device instance
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816 * @param Timing: Pointer to PCCARD timing structure
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817 * @retval HAL status
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818 */
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819 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
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820 {
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821 uint32_t tmpr = 0;
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822
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823 /* Check the parameters */
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824 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
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825 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
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826 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
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827 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
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828
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829 /* Get PCCARD common space timing register value */
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830 tmpr = Device->PMEM4;
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831
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832 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
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833 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
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834 FSMC_PMEM4_MEMHIZ4));
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835 /* Set PCCARD timing parameters */
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836 tmpr |= (uint32_t)((Timing->SetupTime |\
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837 ((Timing->WaitSetupTime) << 8) |\
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838 (Timing->HoldSetupTime) << 16) |\
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839 ((Timing->HiZSetupTime) << 24));
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840
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841 Device->PMEM4 = tmpr;
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842
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843 return HAL_OK;
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844 }
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845
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846 /**
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847 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
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848 * parameters in the FSMC_NAND_PCC_TimingTypeDef
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849 * @param Device: Pointer to PCCARD device instance
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850 * @param Timing: Pointer to PCCARD timing structure
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851 * @retval HAL status
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852 */
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853 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
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854 {
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855 uint32_t tmpr = 0;
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856
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857 /* Check the parameters */
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858 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
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859 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
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860 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
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861 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
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862
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863 /* Get PCCARD timing parameters */
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864 tmpr = Device->PATT4;
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865
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866 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
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867 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
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868 FSMC_PATT4_ATTHIZ4));
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869
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870 /* Set PCCARD timing parameters */
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871 tmpr |= (uint32_t)(Timing->SetupTime |\
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872 ((Timing->WaitSetupTime) << 8) |\
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873 ((Timing->HoldSetupTime) << 16) |\
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874 ((Timing->HiZSetupTime) << 24));
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875 Device->PATT4 = tmpr;
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876
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877 return HAL_OK;
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878 }
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879
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880 /**
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881 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
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882 * parameters in the FSMC_NAND_PCC_TimingTypeDef
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883 * @param Device: Pointer to PCCARD device instance
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884 * @param Timing: Pointer to PCCARD timing structure
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885 * @retval HAL status
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886 */
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887 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
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888 {
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889 uint32_t tmpr = 0;
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890
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891 /* Check the parameters */
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892 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
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893 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
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894 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
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895 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
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896
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897 /* Get FSMC_PCCARD device timing parameters */
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898 tmpr = Device->PIO4;
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899
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900 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
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901 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
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902 FSMC_PIO4_IOHIZ4));
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903
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904 /* Set FSMC_PCCARD device timing parameters */
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905 tmpr |= (uint32_t)(Timing->SetupTime |\
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906 ((Timing->WaitSetupTime) << 8) |\
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907 ((Timing->HoldSetupTime) << 16) |\
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908 ((Timing->HiZSetupTime) << 24));
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909
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910 Device->PIO4 = tmpr;
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911
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912 return HAL_OK;
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913 }
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914
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915 /**
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916 * @brief DeInitializes the FSMC_PCCARD device
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917 * @param Device: Pointer to PCCARD device instance
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918 * @retval HAL status
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919 */
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920 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
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921 {
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922 /* Disable the FSMC_PCCARD device */
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923 __FSMC_PCCARD_DISABLE(Device);
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924
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925 /* De-initialize the FSMC_PCCARD device */
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926 Device->PCR4 = 0x00000018;
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927 Device->SR4 = 0x00000000;
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928 Device->PMEM4 = 0xFCFCFCFC;
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929 Device->PATT4 = 0xFCFCFCFC;
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930 Device->PIO4 = 0xFCFCFCFC;
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931
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932 return HAL_OK;
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933 }
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934 /**
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935 * @}
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936 */
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937
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938 /**
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939 * @}
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940 */
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941
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942 /**
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943 * @}
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944 */
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945 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
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946 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
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947
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948 /**
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949 * @}
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950 */
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951
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952 /**
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953 * @}
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954 */
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955 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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