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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_sdram.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief SDRAM HAL module driver.
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8 * This file provides a generic firmware to drive SDRAM memories mounted
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9 * as external device.
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10 *
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11 @verbatim
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12 ==============================================================================
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13 ##### How to use this driver #####
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14 ==============================================================================
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15 [..]
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16 This driver is a generic layered driver which contains a set of APIs used to
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17 control SDRAM memories. It uses the FMC layer functions to interface
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18 with SDRAM devices.
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19 The following sequence should be followed to configure the FMC to interface
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20 with SDRAM memories:
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21
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22 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
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23 SDRAM_HandleTypeDef hdsram
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24
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25 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
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26 values of the structure member.
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27
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28 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
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29 base register instance for NOR or SDRAM device
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30
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31 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
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32 FMC_SDRAM_TimingTypeDef Timing;
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33 and fill its fields with the allowed values of the structure member.
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34
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35 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
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36 performs the following sequence:
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37
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38 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
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39 (##) Control register configuration using the FMC SDRAM interface function
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40 FMC_SDRAM_Init()
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41 (##) Timing register configuration using the FMC SDRAM interface function
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42 FMC_SDRAM_Timing_Init()
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43 (##) Program the SDRAM external device by applying its initialization sequence
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44 according to the device plugged in your hardware. This step is mandatory
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45 for accessing the SDRAM device.
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46
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47 (#) At this stage you can perform read/write accesses from/to the memory connected
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48 to the SDRAM Bank. You can perform either polling or DMA transfer using the
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49 following APIs:
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50 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
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51 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
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52
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53 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
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54 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
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55 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
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56 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
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57 structure.
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58
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59 (#) You can continuously monitor the SDRAM device HAL state by calling the function
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60 HAL_SDRAM_GetState()
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61
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62 @endverbatim
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63 ******************************************************************************
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64 * @attention
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65 *
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66 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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67 *
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68 * Redistribution and use in source and binary forms, with or without modification,
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69 * are permitted provided that the following conditions are met:
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70 * 1. Redistributions of source code must retain the above copyright notice,
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71 * this list of conditions and the following disclaimer.
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72 * 2. Redistributions in binary form must reproduce the above copyright notice,
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73 * this list of conditions and the following disclaimer in the documentation
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74 * and/or other materials provided with the distribution.
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75 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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76 * may be used to endorse or promote products derived from this software
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77 * without specific prior written permission.
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78 *
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79 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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80 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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81 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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82 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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83 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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84 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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85 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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86 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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87 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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88 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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89 *
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90 ******************************************************************************
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91 */
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92
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93 /* Includes ------------------------------------------------------------------*/
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94 #include "stm32f4xx_hal.h"
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95
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96 /** @addtogroup STM32F4xx_HAL_Driver
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97 * @{
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98 */
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99
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100 /** @defgroup SDRAM SDRAM
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101 * @brief SDRAM driver modules
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102 * @{
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103 */
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104 #ifdef HAL_SDRAM_MODULE_ENABLED
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105 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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106
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107 /* Private typedef -----------------------------------------------------------*/
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108 /* Private define ------------------------------------------------------------*/
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109 /* Private macro -------------------------------------------------------------*/
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110 /* Private variables ---------------------------------------------------------*/
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111 /* Private functions ---------------------------------------------------------*/
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112 /* Exported functions --------------------------------------------------------*/
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113 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
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114 * @{
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115 */
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116
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117 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
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118 * @brief Initialization and Configuration functions
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119 *
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120 @verbatim
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121 ==============================================================================
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122 ##### SDRAM Initialization and de_initialization functions #####
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123 ==============================================================================
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124 [..]
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125 This section provides functions allowing to initialize/de-initialize
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126 the SDRAM memory
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127
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128 @endverbatim
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129 * @{
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130 */
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131
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132 /**
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133 * @brief Performs the SDRAM device initialization sequence.
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134 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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135 * the configuration information for SDRAM module.
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136 * @param Timing: Pointer to SDRAM control timing structure
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137 * @retval HAL status
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138 */
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139 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
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140 {
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141 /* Check the SDRAM handle parameter */
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142 if(hsdram == NULL)
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143 {
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144 return HAL_ERROR;
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145 }
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146
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147 if(hsdram->State == HAL_SDRAM_STATE_RESET)
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148 {
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149 /* Initialize the low level hardware (MSP) */
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150 HAL_SDRAM_MspInit(hsdram);
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151 }
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152
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153 /* Initialize the SDRAM controller state */
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154 hsdram->State = HAL_SDRAM_STATE_BUSY;
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155
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156 /* Initialize SDRAM control Interface */
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157 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
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158
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159 /* Initialize SDRAM timing Interface */
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160 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
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161
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162 /* Update the SDRAM controller state */
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163 hsdram->State = HAL_SDRAM_STATE_READY;
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164
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165 return HAL_OK;
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166 }
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167
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168 /**
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169 * @brief Perform the SDRAM device initialization sequence.
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170 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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171 * the configuration information for SDRAM module.
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172 * @retval HAL status
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173 */
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174 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
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175 {
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176 /* Initialize the low level hardware (MSP) */
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177 HAL_SDRAM_MspDeInit(hsdram);
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178
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179 /* Configure the SDRAM registers with their reset values */
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180 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
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181
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182 /* Reset the SDRAM controller state */
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183 hsdram->State = HAL_SDRAM_STATE_RESET;
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184
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185 /* Release Lock */
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186 __HAL_UNLOCK(hsdram);
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187
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188 return HAL_OK;
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189 }
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190
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191 /**
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192 * @brief SDRAM MSP Init.
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193 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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194 * the configuration information for SDRAM module.
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195 * @retval None
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196 */
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197 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
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198 {
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199 /* NOTE: This function Should not be modified, when the callback is needed,
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200 the HAL_SDRAM_MspInit could be implemented in the user file
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201 */
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202 }
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203
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204 /**
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205 * @brief SDRAM MSP DeInit.
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206 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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207 * the configuration information for SDRAM module.
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208 * @retval None
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209 */
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210 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
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211 {
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212 /* NOTE: This function Should not be modified, when the callback is needed,
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213 the HAL_SDRAM_MspDeInit could be implemented in the user file
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214 */
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215 }
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216
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217 /**
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218 * @brief This function handles SDRAM refresh error interrupt request.
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219 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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220 * the configuration information for SDRAM module.
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221 * @retval HAL status
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222 */
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223 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
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224 {
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225 /* Check SDRAM interrupt Rising edge flag */
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226 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
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227 {
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228 /* SDRAM refresh error interrupt callback */
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229 HAL_SDRAM_RefreshErrorCallback(hsdram);
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230
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231 /* Clear SDRAM refresh error interrupt pending bit */
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232 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
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233 }
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234 }
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235
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236 /**
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237 * @brief SDRAM Refresh error callback.
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238 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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239 * the configuration information for SDRAM module.
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240 * @retval None
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241 */
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242 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
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243 {
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244 /* NOTE: This function Should not be modified, when the callback is needed,
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245 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
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246 */
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247 }
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248
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249 /**
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250 * @brief DMA transfer complete callback.
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251 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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252 * the configuration information for the specified DMA module.
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253 * @retval None
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254 */
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255 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
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256 {
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257 /* NOTE: This function Should not be modified, when the callback is needed,
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258 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
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259 */
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260 }
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261
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262 /**
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263 * @brief DMA transfer complete error callback.
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264 * @param hdma: DMA handle
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265 * @retval None
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266 */
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267 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
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268 {
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269 /* NOTE: This function Should not be modified, when the callback is needed,
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270 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
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271 */
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272 }
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273 /**
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274 * @}
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275 */
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276
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277 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
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278 * @brief Input Output and memory control functions
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279 *
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280 @verbatim
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281 ==============================================================================
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282 ##### SDRAM Input and Output functions #####
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283 ==============================================================================
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284 [..]
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285 This section provides functions allowing to use and control the SDRAM memory
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286
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287 @endverbatim
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288 * @{
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289 */
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290
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291 /**
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292 * @brief Reads 8-bit data buffer from the SDRAM memory.
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293 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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294 * the configuration information for SDRAM module.
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295 * @param pAddress: Pointer to read start address
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296 * @param pDstBuffer: Pointer to destination buffer
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297 * @param BufferSize: Size of the buffer to read from memory
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298 * @retval HAL status
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299 */
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300 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
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301 {
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302 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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303
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304 /* Process Locked */
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305 __HAL_LOCK(hsdram);
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306
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307 /* Check the SDRAM controller state */
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308 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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309 {
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310 return HAL_BUSY;
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311 }
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312 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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313 {
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314 return HAL_ERROR;
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315 }
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316
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317 /* Read data from source */
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318 for(; BufferSize != 0; BufferSize--)
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319 {
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320 *pDstBuffer = *(__IO uint8_t *)pSdramAddress;
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321 pDstBuffer++;
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322 pSdramAddress++;
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323 }
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324
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325 /* Process Unlocked */
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326 __HAL_UNLOCK(hsdram);
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327
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328 return HAL_OK;
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329 }
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330
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331 /**
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332 * @brief Writes 8-bit data buffer to SDRAM memory.
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333 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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334 * the configuration information for SDRAM module.
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335 * @param pAddress: Pointer to write start address
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336 * @param pSrcBuffer: Pointer to source buffer to write
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337 * @param BufferSize: Size of the buffer to write to memory
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338 * @retval HAL status
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339 */
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340 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
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341 {
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342 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
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343 uint32_t tmp = 0;
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344
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345 /* Process Locked */
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346 __HAL_LOCK(hsdram);
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347
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348 /* Check the SDRAM controller state */
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349 tmp = hsdram->State;
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350
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351 if(tmp == HAL_SDRAM_STATE_BUSY)
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352 {
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353 return HAL_BUSY;
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354 }
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355 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
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356 {
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357 return HAL_ERROR;
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358 }
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359
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360 /* Write data to memory */
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361 for(; BufferSize != 0; BufferSize--)
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362 {
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363 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
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364 pSrcBuffer++;
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365 pSdramAddress++;
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366 }
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367
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368 /* Process Unlocked */
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369 __HAL_UNLOCK(hsdram);
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370
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371 return HAL_OK;
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372 }
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373
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374 /**
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375 * @brief Reads 16-bit data buffer from the SDRAM memory.
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376 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
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377 * the configuration information for SDRAM module.
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378 * @param pAddress: Pointer to read start address
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379 * @param pDstBuffer: Pointer to destination buffer
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380 * @param BufferSize: Size of the buffer to read from memory
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381 * @retval HAL status
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382 */
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383 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
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384 {
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385 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
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386
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387 /* Process Locked */
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388 __HAL_LOCK(hsdram);
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389
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390 /* Check the SDRAM controller state */
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391 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
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392 {
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393 return HAL_BUSY;
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394 }
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395 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
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396 {
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397 return HAL_ERROR;
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398 }
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399
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400 /* Read data from source */
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401 for(; BufferSize != 0; BufferSize--)
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402 {
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403 *pDstBuffer = *(__IO uint16_t *)pSdramAddress;
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404 pDstBuffer++;
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|
405 pSdramAddress++;
|
|
|
406 }
|
|
|
407
|
|
|
408 /* Process Unlocked */
|
|
|
409 __HAL_UNLOCK(hsdram);
|
|
|
410
|
|
|
411 return HAL_OK;
|
|
|
412 }
|
|
|
413
|
|
|
414 /**
|
|
|
415 * @brief Writes 16-bit data buffer to SDRAM memory.
|
|
|
416 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
417 * the configuration information for SDRAM module.
|
|
|
418 * @param pAddress: Pointer to write start address
|
|
|
419 * @param pSrcBuffer: Pointer to source buffer to write
|
|
|
420 * @param BufferSize: Size of the buffer to write to memory
|
|
|
421 * @retval HAL status
|
|
|
422 */
|
|
|
423 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
|
|
|
424 {
|
|
|
425 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
|
|
|
426 uint32_t tmp = 0;
|
|
|
427
|
|
|
428 /* Process Locked */
|
|
|
429 __HAL_LOCK(hsdram);
|
|
|
430
|
|
|
431 /* Check the SDRAM controller state */
|
|
|
432 tmp = hsdram->State;
|
|
|
433
|
|
|
434 if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
|
435 {
|
|
|
436 return HAL_BUSY;
|
|
|
437 }
|
|
|
438 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
|
|
439 {
|
|
|
440 return HAL_ERROR;
|
|
|
441 }
|
|
|
442
|
|
|
443 /* Write data to memory */
|
|
|
444 for(; BufferSize != 0; BufferSize--)
|
|
|
445 {
|
|
|
446 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
|
|
|
447 pSrcBuffer++;
|
|
|
448 pSdramAddress++;
|
|
|
449 }
|
|
|
450
|
|
|
451 /* Process Unlocked */
|
|
|
452 __HAL_UNLOCK(hsdram);
|
|
|
453
|
|
|
454 return HAL_OK;
|
|
|
455 }
|
|
|
456
|
|
|
457 /**
|
|
|
458 * @brief Reads 32-bit data buffer from the SDRAM memory.
|
|
|
459 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
460 * the configuration information for SDRAM module.
|
|
|
461 * @param pAddress: Pointer to read start address
|
|
|
462 * @param pDstBuffer: Pointer to destination buffer
|
|
|
463 * @param BufferSize: Size of the buffer to read from memory
|
|
|
464 * @retval HAL status
|
|
|
465 */
|
|
|
466 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
|
|
467 {
|
|
|
468 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
|
|
469
|
|
|
470 /* Process Locked */
|
|
|
471 __HAL_LOCK(hsdram);
|
|
|
472
|
|
|
473 /* Check the SDRAM controller state */
|
|
|
474 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
475 {
|
|
|
476 return HAL_BUSY;
|
|
|
477 }
|
|
|
478 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
|
|
|
479 {
|
|
|
480 return HAL_ERROR;
|
|
|
481 }
|
|
|
482
|
|
|
483 /* Read data from source */
|
|
|
484 for(; BufferSize != 0; BufferSize--)
|
|
|
485 {
|
|
|
486 *pDstBuffer = *(__IO uint32_t *)pSdramAddress;
|
|
|
487 pDstBuffer++;
|
|
|
488 pSdramAddress++;
|
|
|
489 }
|
|
|
490
|
|
|
491 /* Process Unlocked */
|
|
|
492 __HAL_UNLOCK(hsdram);
|
|
|
493
|
|
|
494 return HAL_OK;
|
|
|
495 }
|
|
|
496
|
|
|
497 /**
|
|
|
498 * @brief Writes 32-bit data buffer to SDRAM memory.
|
|
|
499 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
500 * the configuration information for SDRAM module.
|
|
|
501 * @param pAddress: Pointer to write start address
|
|
|
502 * @param pSrcBuffer: Pointer to source buffer to write
|
|
|
503 * @param BufferSize: Size of the buffer to write to memory
|
|
|
504 * @retval HAL status
|
|
|
505 */
|
|
|
506 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
|
|
507 {
|
|
|
508 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
|
|
|
509 uint32_t tmp = 0;
|
|
|
510
|
|
|
511 /* Process Locked */
|
|
|
512 __HAL_LOCK(hsdram);
|
|
|
513
|
|
|
514 /* Check the SDRAM controller state */
|
|
|
515 tmp = hsdram->State;
|
|
|
516
|
|
|
517 if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
|
518 {
|
|
|
519 return HAL_BUSY;
|
|
|
520 }
|
|
|
521 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
|
|
522 {
|
|
|
523 return HAL_ERROR;
|
|
|
524 }
|
|
|
525
|
|
|
526 /* Write data to memory */
|
|
|
527 for(; BufferSize != 0; BufferSize--)
|
|
|
528 {
|
|
|
529 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
|
|
|
530 pSrcBuffer++;
|
|
|
531 pSdramAddress++;
|
|
|
532 }
|
|
|
533
|
|
|
534 /* Process Unlocked */
|
|
|
535 __HAL_UNLOCK(hsdram);
|
|
|
536
|
|
|
537 return HAL_OK;
|
|
|
538 }
|
|
|
539
|
|
|
540 /**
|
|
|
541 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
|
|
|
542 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
543 * the configuration information for SDRAM module.
|
|
|
544 * @param pAddress: Pointer to read start address
|
|
|
545 * @param pDstBuffer: Pointer to destination buffer
|
|
|
546 * @param BufferSize: Size of the buffer to read from memory
|
|
|
547 * @retval HAL status
|
|
|
548 */
|
|
|
549 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
|
|
|
550 {
|
|
|
551 uint32_t tmp = 0;
|
|
|
552
|
|
|
553 /* Process Locked */
|
|
|
554 __HAL_LOCK(hsdram);
|
|
|
555
|
|
|
556 /* Check the SDRAM controller state */
|
|
|
557 tmp = hsdram->State;
|
|
|
558
|
|
|
559 if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
|
560 {
|
|
|
561 return HAL_BUSY;
|
|
|
562 }
|
|
|
563 else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
|
|
|
564 {
|
|
|
565 return HAL_ERROR;
|
|
|
566 }
|
|
|
567
|
|
|
568 /* Configure DMA user callbacks */
|
|
|
569 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
|
|
570 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
|
|
571
|
|
|
572 /* Enable the DMA Stream */
|
|
|
573 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
|
|
|
574
|
|
|
575 /* Process Unlocked */
|
|
|
576 __HAL_UNLOCK(hsdram);
|
|
|
577
|
|
|
578 return HAL_OK;
|
|
|
579 }
|
|
|
580
|
|
|
581 /**
|
|
|
582 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
|
|
|
583 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
584 * the configuration information for SDRAM module.
|
|
|
585 * @param pAddress: Pointer to write start address
|
|
|
586 * @param pSrcBuffer: Pointer to source buffer to write
|
|
|
587 * @param BufferSize: Size of the buffer to write to memory
|
|
|
588 * @retval HAL status
|
|
|
589 */
|
|
|
590 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
|
|
|
591 {
|
|
|
592 uint32_t tmp = 0;
|
|
|
593
|
|
|
594 /* Process Locked */
|
|
|
595 __HAL_LOCK(hsdram);
|
|
|
596
|
|
|
597 /* Check the SDRAM controller state */
|
|
|
598 tmp = hsdram->State;
|
|
|
599
|
|
|
600 if(tmp == HAL_SDRAM_STATE_BUSY)
|
|
|
601 {
|
|
|
602 return HAL_BUSY;
|
|
|
603 }
|
|
|
604 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
|
|
605 {
|
|
|
606 return HAL_ERROR;
|
|
|
607 }
|
|
|
608
|
|
|
609 /* Configure DMA user callbacks */
|
|
|
610 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
|
|
|
611 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
|
|
|
612
|
|
|
613 /* Enable the DMA Stream */
|
|
|
614 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
|
|
|
615
|
|
|
616 /* Process Unlocked */
|
|
|
617 __HAL_UNLOCK(hsdram);
|
|
|
618
|
|
|
619 return HAL_OK;
|
|
|
620 }
|
|
|
621 /**
|
|
|
622 * @}
|
|
|
623 */
|
|
|
624
|
|
|
625 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
|
|
|
626 * @brief management functions
|
|
|
627 *
|
|
|
628 @verbatim
|
|
|
629 ==============================================================================
|
|
|
630 ##### SDRAM Control functions #####
|
|
|
631 ==============================================================================
|
|
|
632 [..]
|
|
|
633 This subsection provides a set of functions allowing to control dynamically
|
|
|
634 the SDRAM interface.
|
|
|
635
|
|
|
636 @endverbatim
|
|
|
637 * @{
|
|
|
638 */
|
|
|
639
|
|
|
640 /**
|
|
|
641 * @brief Enables dynamically SDRAM write protection.
|
|
|
642 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
643 * the configuration information for SDRAM module.
|
|
|
644 * @retval HAL status
|
|
|
645 */
|
|
|
646 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
|
|
|
647 {
|
|
|
648 /* Check the SDRAM controller state */
|
|
|
649 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
650 {
|
|
|
651 return HAL_BUSY;
|
|
|
652 }
|
|
|
653
|
|
|
654 /* Update the SDRAM state */
|
|
|
655 hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
656
|
|
|
657 /* Enable write protection */
|
|
|
658 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
|
|
|
659
|
|
|
660 /* Update the SDRAM state */
|
|
|
661 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
|
|
|
662
|
|
|
663 return HAL_OK;
|
|
|
664 }
|
|
|
665
|
|
|
666 /**
|
|
|
667 * @brief Disables dynamically SDRAM write protection.
|
|
|
668 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
669 * the configuration information for SDRAM module.
|
|
|
670 * @retval HAL status
|
|
|
671 */
|
|
|
672 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
|
|
|
673 {
|
|
|
674 /* Check the SDRAM controller state */
|
|
|
675 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
676 {
|
|
|
677 return HAL_BUSY;
|
|
|
678 }
|
|
|
679
|
|
|
680 /* Update the SDRAM state */
|
|
|
681 hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
682
|
|
|
683 /* Disable write protection */
|
|
|
684 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
|
|
|
685
|
|
|
686 /* Update the SDRAM state */
|
|
|
687 hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
688
|
|
|
689 return HAL_OK;
|
|
|
690 }
|
|
|
691
|
|
|
692 /**
|
|
|
693 * @brief Sends Command to the SDRAM bank.
|
|
|
694 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
695 * the configuration information for SDRAM module.
|
|
|
696 * @param Command: SDRAM command structure
|
|
|
697 * @param Timeout: Timeout duration
|
|
|
698 * @retval HAL status
|
|
|
699 */
|
|
|
700 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
|
|
|
701 {
|
|
|
702 /* Check the SDRAM controller state */
|
|
|
703 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
704 {
|
|
|
705 return HAL_BUSY;
|
|
|
706 }
|
|
|
707
|
|
|
708 /* Update the SDRAM state */
|
|
|
709 hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
710
|
|
|
711 /* Send SDRAM command */
|
|
|
712 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
|
|
|
713
|
|
|
714 /* Update the SDRAM controller state */
|
|
|
715 if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
|
|
|
716 {
|
|
|
717 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
|
|
|
718 }
|
|
|
719 else
|
|
|
720 {
|
|
|
721 hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
722 }
|
|
|
723
|
|
|
724 return HAL_OK;
|
|
|
725 }
|
|
|
726
|
|
|
727 /**
|
|
|
728 * @brief Programs the SDRAM Memory Refresh rate.
|
|
|
729 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
730 * the configuration information for SDRAM module.
|
|
|
731 * @param RefreshRate: The SDRAM refresh rate value
|
|
|
732 * @retval HAL status
|
|
|
733 */
|
|
|
734 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
|
|
|
735 {
|
|
|
736 /* Check the SDRAM controller state */
|
|
|
737 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
738 {
|
|
|
739 return HAL_BUSY;
|
|
|
740 }
|
|
|
741
|
|
|
742 /* Update the SDRAM state */
|
|
|
743 hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
744
|
|
|
745 /* Program the refresh rate */
|
|
|
746 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
|
|
|
747
|
|
|
748 /* Update the SDRAM state */
|
|
|
749 hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
750
|
|
|
751 return HAL_OK;
|
|
|
752 }
|
|
|
753
|
|
|
754 /**
|
|
|
755 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
|
|
|
756 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
757 * the configuration information for SDRAM module.
|
|
|
758 * @param AutoRefreshNumber: The SDRAM auto Refresh number
|
|
|
759 * @retval HAL status
|
|
|
760 */
|
|
|
761 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
|
|
|
762 {
|
|
|
763 /* Check the SDRAM controller state */
|
|
|
764 if(hsdram->State == HAL_SDRAM_STATE_BUSY)
|
|
|
765 {
|
|
|
766 return HAL_BUSY;
|
|
|
767 }
|
|
|
768
|
|
|
769 /* Update the SDRAM state */
|
|
|
770 hsdram->State = HAL_SDRAM_STATE_BUSY;
|
|
|
771
|
|
|
772 /* Set the Auto-Refresh number */
|
|
|
773 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
|
|
|
774
|
|
|
775 /* Update the SDRAM state */
|
|
|
776 hsdram->State = HAL_SDRAM_STATE_READY;
|
|
|
777
|
|
|
778 return HAL_OK;
|
|
|
779 }
|
|
|
780
|
|
|
781 /**
|
|
|
782 * @brief Returns the SDRAM memory current mode.
|
|
|
783 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
784 * the configuration information for SDRAM module.
|
|
|
785 * @retval The SDRAM memory mode.
|
|
|
786 */
|
|
|
787 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
|
|
|
788 {
|
|
|
789 /* Return the SDRAM memory current mode */
|
|
|
790 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
|
|
|
791 }
|
|
|
792
|
|
|
793 /**
|
|
|
794 * @}
|
|
|
795 */
|
|
|
796
|
|
|
797 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
|
|
|
798 * @brief Peripheral State functions
|
|
|
799 *
|
|
|
800 @verbatim
|
|
|
801 ==============================================================================
|
|
|
802 ##### SDRAM State functions #####
|
|
|
803 ==============================================================================
|
|
|
804 [..]
|
|
|
805 This subsection permits to get in run-time the status of the SDRAM controller
|
|
|
806 and the data flow.
|
|
|
807
|
|
|
808 @endverbatim
|
|
|
809 * @{
|
|
|
810 */
|
|
|
811
|
|
|
812 /**
|
|
|
813 * @brief Returns the SDRAM state.
|
|
|
814 * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
|
|
|
815 * the configuration information for SDRAM module.
|
|
|
816 * @retval HAL state
|
|
|
817 */
|
|
|
818 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
|
|
|
819 {
|
|
|
820 return hsdram->State;
|
|
|
821 }
|
|
|
822
|
|
|
823 /**
|
|
|
824 * @}
|
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|
825 */
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|
826
|
|
|
827 /**
|
|
|
828 * @}
|
|
|
829 */
|
|
|
830 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
831 #endif /* HAL_SDRAM_MODULE_ENABLED */
|
|
|
832 /**
|
|
|
833 * @}
|
|
|
834 */
|
|
|
835
|
|
|
836 /**
|
|
|
837 * @}
|
|
|
838 */
|
|
|
839
|
|
|
840 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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