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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_iwdg.h @ 903:0f2e5a166d40 Evo_2_23

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Disable GNSS operations using compile switch: GNSS IO operation caused the RTE to not switch into sleep mode in case of wrong HW version => Operations have been disabled by inactive ENABLE_GNSS compile switch
author Ideenmodellierer
date Thu, 03 Oct 2024 20:25:49 +0200
parents c78bcbd5deda
children
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_iwdg.h
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4 * @author MCD Application Team
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5 * @brief Header file of IWDG LL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_LL_IWDG_H
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38 #define __STM32F4xx_LL_IWDG_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx.h"
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46
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47 /** @addtogroup STM32F4xx_LL_Driver
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48 * @{
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49 */
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50
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51 #if defined(IWDG)
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52
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53 /** @defgroup IWDG_LL IWDG
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54 * @{
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55 */
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56
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57 /* Private types -------------------------------------------------------------*/
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58 /* Private variables ---------------------------------------------------------*/
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59
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60 /* Private constants ---------------------------------------------------------*/
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61 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
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62 * @{
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63 */
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64
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65 #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
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66 #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
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67 #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
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68 #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
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69
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70 /**
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71 * @}
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72 */
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73
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74 /* Private macros ------------------------------------------------------------*/
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75
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76 /* Exported types ------------------------------------------------------------*/
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77 /* Exported constants --------------------------------------------------------*/
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78 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
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79 * @{
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80 */
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81
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82 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
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83 * @brief Flags defines which can be used with LL_IWDG_ReadReg function
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84 * @{
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85 */
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86 #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
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87 #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
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88
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89 /**
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90 * @}
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91 */
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92
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93 /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
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94 * @{
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95 */
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96 #define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
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97 #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
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98 #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
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99 #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
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100 #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
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101 #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
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102 #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
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103 /**
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104 * @}
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105 */
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106
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107 /**
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108 * @}
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109 */
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110
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111 /* Exported macro ------------------------------------------------------------*/
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112 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
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113 * @{
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114 */
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115
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116 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
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117 * @{
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118 */
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119
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120 /**
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121 * @brief Write a value in IWDG register
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122 * @param __INSTANCE__ IWDG Instance
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123 * @param __REG__ Register to be written
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124 * @param __VALUE__ Value to be written in the register
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125 * @retval None
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126 */
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127 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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128
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129 /**
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130 * @brief Read a value in IWDG register
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131 * @param __INSTANCE__ IWDG Instance
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132 * @param __REG__ Register to be read
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133 * @retval Register value
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134 */
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135 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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136 /**
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137 * @}
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138 */
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139
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140 /**
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141 * @}
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142 */
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143
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144
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145 /* Exported functions --------------------------------------------------------*/
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146 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
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147 * @{
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148 */
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149 /** @defgroup IWDG_LL_EF_Configuration Configuration
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150 * @{
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151 */
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152
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153 /**
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154 * @brief Start the Independent Watchdog
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155 * @note Except if the hardware watchdog option is selected
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156 * @rmtoll KR KEY LL_IWDG_Enable
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157 * @param IWDGx IWDG Instance
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158 * @retval None
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159 */
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160 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
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161 {
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162 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
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163 }
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164
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165 /**
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166 * @brief Reloads IWDG counter with value defined in the reload register
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167 * @rmtoll KR KEY LL_IWDG_ReloadCounter
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168 * @param IWDGx IWDG Instance
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169 * @retval None
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170 */
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171 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
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172 {
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173 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
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174 }
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175
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176 /**
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177 * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
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178 * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
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179 * @param IWDGx IWDG Instance
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180 * @retval None
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181 */
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182 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
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183 {
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184 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
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185 }
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186
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187 /**
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188 * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
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189 * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
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190 * @param IWDGx IWDG Instance
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191 * @retval None
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192 */
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193 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
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194 {
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195 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
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196 }
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197
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198 /**
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199 * @brief Select the prescaler of the IWDG
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200 * @rmtoll PR PR LL_IWDG_SetPrescaler
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201 * @param IWDGx IWDG Instance
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202 * @param Prescaler This parameter can be one of the following values:
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203 * @arg @ref LL_IWDG_PRESCALER_4
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204 * @arg @ref LL_IWDG_PRESCALER_8
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205 * @arg @ref LL_IWDG_PRESCALER_16
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206 * @arg @ref LL_IWDG_PRESCALER_32
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207 * @arg @ref LL_IWDG_PRESCALER_64
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208 * @arg @ref LL_IWDG_PRESCALER_128
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209 * @arg @ref LL_IWDG_PRESCALER_256
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210 * @retval None
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211 */
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212 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
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213 {
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214 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
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215 }
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216
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217 /**
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218 * @brief Get the selected prescaler of the IWDG
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219 * @rmtoll PR PR LL_IWDG_GetPrescaler
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220 * @param IWDGx IWDG Instance
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221 * @retval Returned value can be one of the following values:
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222 * @arg @ref LL_IWDG_PRESCALER_4
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223 * @arg @ref LL_IWDG_PRESCALER_8
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224 * @arg @ref LL_IWDG_PRESCALER_16
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225 * @arg @ref LL_IWDG_PRESCALER_32
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226 * @arg @ref LL_IWDG_PRESCALER_64
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227 * @arg @ref LL_IWDG_PRESCALER_128
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228 * @arg @ref LL_IWDG_PRESCALER_256
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229 */
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230 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
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231 {
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232 return (uint32_t)(READ_REG(IWDGx->PR));
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233 }
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234
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235 /**
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236 * @brief Specify the IWDG down-counter reload value
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237 * @rmtoll RLR RL LL_IWDG_SetReloadCounter
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238 * @param IWDGx IWDG Instance
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239 * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
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240 * @retval None
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241 */
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242 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
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243 {
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244 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
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245 }
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246
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247 /**
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248 * @brief Get the specified IWDG down-counter reload value
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249 * @rmtoll RLR RL LL_IWDG_GetReloadCounter
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250 * @param IWDGx IWDG Instance
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251 * @retval Value between Min_Data=0 and Max_Data=0x0FFF
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252 */
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253 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
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254 {
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255 return (uint32_t)(READ_REG(IWDGx->RLR));
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256 }
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257
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258
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259 /**
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260 * @}
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261 */
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262
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263 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
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264 * @{
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265 */
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266
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267 /**
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268 * @brief Check if flag Prescaler Value Update is set or not
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269 * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
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270 * @param IWDGx IWDG Instance
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271 * @retval State of bit (1 or 0).
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272 */
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273 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
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274 {
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275 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
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276 }
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277
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278 /**
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279 * @brief Check if flag Reload Value Update is set or not
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280 * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
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281 * @param IWDGx IWDG Instance
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282 * @retval State of bit (1 or 0).
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283 */
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284 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
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285 {
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286 return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
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287 }
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288
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289
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290 /**
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291 * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
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292 * @rmtoll SR PVU LL_IWDG_IsReady\n
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293 * SR RVU LL_IWDG_IsReady
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294 * @param IWDGx IWDG Instance
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295 * @retval State of bits (1 or 0).
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296 */
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297 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
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298 {
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299 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U);
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300 }
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301
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302 /**
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303 * @}
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304 */
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305
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306
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307 /**
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308 * @}
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309 */
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310
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311 /**
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312 * @}
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313 */
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314
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315 #endif /* IWDG) */
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316
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317 /**
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318 * @}
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319 */
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320
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321 #ifdef __cplusplus
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322 }
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323 #endif
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324
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325 #endif /* __STM32F4xx_LL_IWDG_H */
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326
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327 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/