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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_hash.h @ 903:0f2e5a166d40 Evo_2_23

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Disable GNSS operations using compile switch: GNSS IO operation caused the RTE to not switch into sleep mode in case of wrong HW version => Operations have been disabled by inactive ENABLE_GNSS compile switch
author Ideenmodellierer
date Thu, 03 Oct 2024 20:25:49 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_hash.h
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4 * @author MCD Application Team
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5 * @brief Header file of HASH HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_HAL_HASH_H
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38 #define __STM32F4xx_HAL_HASH_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 #if defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F479xx)
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45
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46 /* Includes ------------------------------------------------------------------*/
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47 #include "stm32f4xx_hal_def.h"
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48
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49 /** @addtogroup STM32F4xx_HAL_Driver
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50 * @{
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51 */
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52
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53 /** @addtogroup HASH
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54 * @brief HASH HAL module driver
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55 * @{
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56 */
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57
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58 /* Exported types ------------------------------------------------------------*/
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59 /** @defgroup HASH_Exported_Types HASH Exported Types
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60 * @{
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61 */
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62
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63 /** @defgroup HASH_Exported_Types_Group1 HASH Configuration Structure definition
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64 * @{
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65 */
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66
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67 typedef struct
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68 {
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69 uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
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70 This parameter can be a value of @ref HASH_Data_Type */
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71
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72 uint32_t KeySize; /*!< The key size is used only in HMAC operation */
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73
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74 uint8_t* pKey; /*!< The key is used only in HMAC operation */
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75 }HASH_InitTypeDef;
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76
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77 /**
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78 * @}
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79 */
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80
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81 /** @defgroup HASH_Exported_Types_Group2 HASH State structures definition
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82 * @{
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83 */
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84
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85 typedef enum
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86 {
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87 HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
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88 HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
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89 HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
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90 HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
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91 HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
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92 }HAL_HASH_StateTypeDef;
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93
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94 /**
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95 * @}
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96 */
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97
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98 /** @defgroup HASH_Exported_Types_Group3 HASH phase structures definition
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99 * @{
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100 */
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101
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102 typedef enum
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103 {
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104 HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
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105 HAL_HASH_PHASE_PROCESS = 0x02U /*!< HASH peripheral is in processing phase */
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106 }HAL_HASH_PhaseTypeDef;
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107
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108 /**
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109 * @}
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110 */
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111
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112 /** @defgroup HASH_Exported_Types_Group4 HASH Handle structures definition
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113 * @{
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114 */
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115
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116 typedef struct
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117 {
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118 HASH_InitTypeDef Init; /*!< HASH required parameters */
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119
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120 uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
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121
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122 uint8_t *pHashOutBuffPtr; /*!< Pointer to input buffer */
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123
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124 __IO uint32_t HashBuffSize; /*!< Size of buffer to be processed */
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125
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126 __IO uint32_t HashInCount; /*!< Counter of inputed data */
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127
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128 __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
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129
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130 HAL_StatusTypeDef Status; /*!< HASH peripheral status */
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131
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132 HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
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133
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134 DMA_HandleTypeDef *hdmain; /*!< HASH In DMA handle parameters */
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135
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136 HAL_LockTypeDef Lock; /*!< HASH locking object */
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137
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138 __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
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139 } HASH_HandleTypeDef;
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140
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141 /**
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142 * @}
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143 */
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144
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145
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146 /**
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147 * @}
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148 */
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149
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150 /* Exported constants --------------------------------------------------------*/
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151 /** @defgroup HASH_Exported_Constants HASH Exported Constants
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152 * @{
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153 */
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154
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155 /** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
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156 * @{
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157 */
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158 #define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */
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159 #define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
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160 #define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
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161 #define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
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162 /**
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163 * @}
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164 */
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165
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166 /** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
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167 * @{
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168 */
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169 #define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */
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170 #define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
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171 /**
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172 * @}
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173 */
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174
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175 /** @defgroup HASH_Data_Type HASH Data Type
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176 * @{
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177 */
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178 #define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */
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179 #define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
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180 #define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
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181 #define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
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182 /**
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183 * @}
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184 */
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185
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186 /** @defgroup HASH_Exported_Constants_Group4 HASH HMAC Long key
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187 * @brief HASH HMAC Long key used only for HMAC mode
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188 * @{
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189 */
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190 #define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key is <= 64 bytes */
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191 #define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
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192 /**
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193 * @}
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194 */
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195
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196 /** @defgroup HASH_Exported_Constants_Group5 HASH Flags definition
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197 * @{
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198 */
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199 #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
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200 #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
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201 #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
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202 #define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
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203 #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
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204 /**
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205 * @}
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206 */
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207
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208 /** @defgroup HASH_Exported_Constants_Group6 HASH Interrupts definition
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209 * @{
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210 */
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211 #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
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212 #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
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213 /**
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214 * @}
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215 */
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216
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217 /**
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218 * @}
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219 */
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220
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221 /* Exported macro ------------------------------------------------------------*/
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222 /** @defgroup HASH_Exported_Macros HASH Exported Macros
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223 * @{
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224 */
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225
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226 /** @brief Reset HASH handle state
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227 * @param __HANDLE__ specifies the HASH handle.
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228 * @retval None
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229 */
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230 #define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
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231
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232 /** @brief Check whether the specified HASH flag is set or not.
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233 * @param __FLAG__ specifies the flag to check.
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234 * This parameter can be one of the following values:
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235 * @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
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236 * @arg HASH_FLAG_DCIS: Digest calculation complete
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237 * @arg HASH_FLAG_DMAS: DMA interface is enabled (DMAE=1) or a transfer is ongoing
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238 * @arg HASH_FLAG_BUSY: The hash core is Busy : processing a block of data
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239 * @arg HASH_FLAG_DINNE: DIN not empty : The input buffer contains at least one word of data
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240 * @retval The new state of __FLAG__ (TRUE or FALSE).
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241 */
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242 #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
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243 ((HASH->SR & (__FLAG__)) == (__FLAG__)))
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244
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245 /**
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246 * @brief Enable the multiple DMA mode.
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247 * This feature is available only in STM32F429x and STM32F439x devices.
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248 * @retval None
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249 */
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250 #define __HAL_HASH_SET_MDMAT() HASH->CR |= HASH_CR_MDMAT
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251
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252 /**
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253 * @brief Disable the multiple DMA mode.
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254 * @retval None
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255 */
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256 #define __HAL_HASH_RESET_MDMAT() HASH->CR &= (uint32_t)(~HASH_CR_MDMAT)
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257
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258 /**
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259 * @brief Start the digest computation
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260 * @retval None
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261 */
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262 #define __HAL_HASH_START_DIGEST() HASH->STR |= HASH_STR_DCAL
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263
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264 /**
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265 * @brief Set the number of valid bits in last word written in Data register
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266 * @param SIZE size in byte of last data written in Data register.
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267 * @retval None
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268 */
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269 #define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
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270 HASH->STR |= 8U * ((SIZE) % 4U);\
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271 }while(0)
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272
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273 /**
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274 * @}
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275 */
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276
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277 /* Include HASH HAL Extension module */
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278 #include "stm32f4xx_hal_hash_ex.h"
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279 /* Exported functions --------------------------------------------------------*/
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280
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281 /** @defgroup HASH_Exported_Functions HASH Exported Functions
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282 * @{
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283 */
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284
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285 /** @addtogroup HASH_Exported_Functions_Group1
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286 * @{
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287 */
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288 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
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289 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
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290 /**
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291 * @}
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292 */
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293
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294 /** @addtogroup HASH_Exported_Functions_Group2
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295 * @{
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296 */
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297 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
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298 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
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299 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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300 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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301 /**
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302 * @}
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303 */
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304
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305 /** @addtogroup HASH_Exported_Functions_Group3
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306 * @{
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307 */
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308 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
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309 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
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310 /**
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311 * @}
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312 */
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313
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314 /** @addtogroup HASH_Exported_Functions_Group4
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315 * @{
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316 */
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317 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
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318 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
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319 /**
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320 * @}
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321 */
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322
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323 /** @addtogroup HASH_Exported_Functions_Group5
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324 * @{
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325 */
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326 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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327 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
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328 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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329 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
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330 /**
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331 * @}
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332 */
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333
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334 /** @addtogroup HASH_Exported_Functions_Group6
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335 * @{
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336 */
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337 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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338 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
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339 /**
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340 * @}
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341 */
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342
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343 /** @addtogroup HASH_Exported_Functions_Group7
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344 * @{
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345 */
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346 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
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347 /**
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348 * @}
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349 */
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350
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351 /** @addtogroup HASH_Exported_Functions_Group8
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352 * @{
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353 */
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354 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
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355 void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
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356 void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
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357 void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
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358 void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
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359 void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
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360 /**
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361 * @}
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362 */
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363
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364 /**
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365 * @}
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366 */
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367
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368 /* Private types -------------------------------------------------------------*/
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369 /** @defgroup HASH_Private_Types HASH Private Types
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370 * @{
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371 */
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372
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373 /**
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374 * @}
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375 */
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376
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377 /* Private variables ---------------------------------------------------------*/
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378 /** @defgroup HASH_Private_Variables HASH Private Variables
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379 * @{
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380 */
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381
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382 /**
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383 * @}
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384 */
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385
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386 /* Private constants ---------------------------------------------------------*/
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387 /** @defgroup HASH_Private_Constants HASH Private Constants
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388 * @{
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389 */
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390
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391 /**
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392 * @}
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393 */
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394
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395 /* Private macros ------------------------------------------------------------*/
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396 /** @defgroup HASH_Private_Macros HASH Private Macros
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397 * @{
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398 */
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399 #define IS_HASH_ALGOSELECTION(__ALGOSELECTION__) (((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA1) || \
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400 ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA224) || \
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401 ((__ALGOSELECTION__) == HASH_ALGOSELECTION_SHA256) || \
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402 ((__ALGOSELECTION__) == HASH_ALGOSELECTION_MD5))
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403
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404
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405 #define IS_HASH_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == HASH_ALGOMODE_HASH) || \
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406 ((__ALGOMODE__) == HASH_ALGOMODE_HMAC))
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407
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408
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409 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
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410 ((__DATATYPE__) == HASH_DATATYPE_16B)|| \
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411 ((__DATATYPE__) == HASH_DATATYPE_8B) || \
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412 ((__DATATYPE__) == HASH_DATATYPE_1B))
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413
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414
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415 #define IS_HASH_HMAC_KEYTYPE(__KEYTYPE__) (((__KEYTYPE__) == HASH_HMAC_KEYTYPE_SHORTKEY) || \
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416 ((__KEYTYPE__) == HASH_HMAC_KEYTYPE_LONGKEY))
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417
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418 #define IS_HASH_SHA1_BUFFER_SIZE(__SIZE__) ((((__SIZE__)%4U) != 0U)? 0U: 1U)
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419
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420 /**
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421 * @}
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422 */
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423
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424 /* Private functions ---------------------------------------------------------*/
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425 /** @defgroup HASH_Private_Functions HASH Private Functions
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426 * @{
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427 */
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428
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429 /**
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430 * @}
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431 */
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432
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433 #endif /* STM32F415xx || STM32F417xx || STM32F437xx || STM32F439xx || STM32F479xx */
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434 /**
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435 * @}
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436 */
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437
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438 /**
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439 * @}
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440 */
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441
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442 #ifdef __cplusplus
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443 }
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444 #endif
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445
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446
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447 #endif /* __STM32F4xx_HAL_HASH_H */
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448
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449 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/