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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @ 903:0f2e5a166d40 Evo_2_23

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Disable GNSS operations using compile switch: GNSS IO operation caused the RTE to not switch into sleep mode in case of wrong HW version => Operations have been disabled by inactive ENABLE_GNSS compile switch
author Ideenmodellierer
date Thu, 03 Oct 2024 20:25:49 +0200
parents c78bcbd5deda
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128
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_adc_ex.h
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4 * @author MCD Application Team
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5 * @brief Header file of ADC HAL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_ADC_EX_H
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38 #define __STM32F4xx_ADC_EX_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx_hal_def.h"
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46
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47 /** @addtogroup STM32F4xx_HAL_Driver
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48 * @{
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49 */
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50
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51 /** @addtogroup ADCEx
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52 * @{
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53 */
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54
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55 /* Exported types ------------------------------------------------------------*/
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56 /** @defgroup ADCEx_Exported_Types ADC Exported Types
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57 * @{
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58 */
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59
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60 /**
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61 * @brief ADC Configuration injected Channel structure definition
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62 * @note Parameters of this structure are shared within 2 scopes:
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63 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
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64 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
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65 * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
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66 * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
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67 * ADC state can be either:
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68 * - For all parameters: ADC disabled
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69 * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
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70 * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
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71 */
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72 typedef struct
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73 {
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74 uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
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75 This parameter can be a value of @ref ADC_channels
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76 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
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77 uint32_t InjectedRank; /*!< Rank in the injected group sequencer
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78 This parameter must be a value of @ref ADCEx_injected_rank
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79 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
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80 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
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81 Unit: ADC clock cycles
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82 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
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83 This parameter can be a value of @ref ADC_sampling_times
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84 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
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85 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
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86 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
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87 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
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88 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
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89 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
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90 Offset value must be a positive number.
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91 Depending of ADC resolution selected (12, 10, 8 or 6 bits),
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92 this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
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93 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
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94 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
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95 This parameter must be a number between Min_Data = 1 and Max_Data = 4.
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96 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
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97 configure a channel on injected group can impact the configuration of other channels previously set. */
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98 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
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99 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
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100 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
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101 This parameter can be set to ENABLE or DISABLE.
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102 Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
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103 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
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104 configure a channel on injected group can impact the configuration of other channels previously set. */
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105 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
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106 This parameter can be set to ENABLE or DISABLE.
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107 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
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108 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
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109 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
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110 To maintain JAUTO always enabled, DMA must be configured in circular mode.
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111 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
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112 configure a channel on injected group can impact the configuration of other channels previously set. */
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113 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
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114 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
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115 If set to external trigger source, triggering is on event rising edge.
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116 This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected
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117 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
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118 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
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119 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
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120 configure a channel on injected group can impact the configuration of other channels previously set. */
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121 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
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122 This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
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123 If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
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124 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
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125 configure a channel on injected group can impact the configuration of other channels previously set. */
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126 }ADC_InjectionConfTypeDef;
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127
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128 /**
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129 * @brief ADC Configuration multi-mode structure definition
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130 */
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131 typedef struct
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132 {
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133 uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
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134 This parameter can be a value of @ref ADCEx_Common_mode */
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135 uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
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136 This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */
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137 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
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138 This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
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139 }ADC_MultiModeTypeDef;
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140
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141 /**
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142 * @}
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143 */
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144
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145 /* Exported constants --------------------------------------------------------*/
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146 /** @defgroup ADCEx_Exported_Constants ADC Exported Constants
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147 * @{
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148 */
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149
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150 /** @defgroup ADCEx_Common_mode ADC Common Mode
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151 * @{
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152 */
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153 #define ADC_MODE_INDEPENDENT 0x00000000U
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154 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
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155 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
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156 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
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157 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
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158 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
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159 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
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160 #define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
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161 #define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
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162 #define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
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163 #define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
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164 #define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
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165 #define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
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166 /**
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167 * @}
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168 */
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169
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170 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
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171 * @{
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172 */
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173 #define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */
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174 #define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
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175 #define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
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176 #define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
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177 /**
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178 * @}
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179 */
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180
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181 /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
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182 * @{
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183 */
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184 #define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U
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185 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
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186 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
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187 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
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188 /**
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189 * @}
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190 */
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191
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192 /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
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193 * @{
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194 */
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195 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U
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196 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
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197 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
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198 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
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199 #define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
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200 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
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201 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
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202 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
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203 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
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204 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
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205 #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
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206 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
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207 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
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208 #define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
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209 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
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210 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
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211 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U)
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212 /**
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213 * @}
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214 */
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215
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216 /** @defgroup ADCEx_injected_rank ADC Injected Rank
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217 * @{
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218 */
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219 #define ADC_INJECTED_RANK_1 0x00000001U
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220 #define ADC_INJECTED_RANK_2 0x00000002U
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221 #define ADC_INJECTED_RANK_3 0x00000003U
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222 #define ADC_INJECTED_RANK_4 0x00000004U
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223 /**
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224 * @}
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225 */
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226
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227 /** @defgroup ADCEx_channels ADC Specific Channels
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228 * @{
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229 */
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230 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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231 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
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232 defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
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233 defined(STM32F412Cx)
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234 #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
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235 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
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236 STM32F412Vx || STM32F412Rx || STM32F412Cx */
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237
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238 #if defined(STM32F413xx) || defined(STM32F423xx)
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239 #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18)
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240 #endif /* STM32F413xx || STM32F423xx */
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241
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242 #if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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243 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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244 #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
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245 #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
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246 #endif /* STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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247 /**
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248 * @}
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249 */
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250
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251
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252 /**
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253 * @}
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254 */
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255
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256 /* Exported macro ------------------------------------------------------------*/
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257 /** @defgroup ADC_Exported_Macros ADC Exported Macros
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258 * @{
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259 */
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260 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
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261 /**
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262 * @brief Disable internal path of ADC channel Vbat
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263 * @note Use case of this macro:
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264 * On devices STM32F42x and STM32F43x, ADC internal channels
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265 * Vbat and VrefInt share the same internal path, only
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266 * one of them can be enabled.This macro is to be used when ADC
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267 * channels Vbat and VrefInt are selected, and must be called
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268 * before starting conversion of ADC channel VrefInt in order
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269 * to disable ADC channel Vbat.
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270 * @retval None
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271 */
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272 #define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))
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273 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
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274 /**
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275 * @}
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276 */
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277
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278 /* Exported functions --------------------------------------------------------*/
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279 /** @addtogroup ADCEx_Exported_Functions
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280 * @{
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281 */
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282
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283 /** @addtogroup ADCEx_Exported_Functions_Group1
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284 * @{
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285 */
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286
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287 /* I/O operation functions ******************************************************/
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288 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
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289 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
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290 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
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291 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
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292 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
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293 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
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294 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
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295 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
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296 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
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297 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
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298
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299 /* Peripheral Control functions *************************************************/
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300 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
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301 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
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302
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303 /**
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304 * @}
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305 */
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306
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307 /**
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308 * @}
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309 */
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310 /* Private types -------------------------------------------------------------*/
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311 /* Private variables ---------------------------------------------------------*/
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312 /* Private constants ---------------------------------------------------------*/
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313 /** @defgroup ADCEx_Private_Constants ADC Private Constants
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314 * @{
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315 */
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316
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317 /**
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318 * @}
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319 */
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320
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321 /* Private macros ------------------------------------------------------------*/
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322 /** @defgroup ADCEx_Private_Macros ADC Private Macros
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323 * @{
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324 */
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325 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
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326 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
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327 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
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328 defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
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329 #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)
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330 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||
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331 STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
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332
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333 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
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334 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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335 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \
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336 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))
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337 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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338
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339 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
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340 ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
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341 ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
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342 ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
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343 ((MODE) == ADC_DUALMODE_REGSIMULT) || \
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344 ((MODE) == ADC_DUALMODE_INTERL) || \
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345 ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
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346 ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
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347 ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
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348 ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
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349 ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
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350 ((MODE) == ADC_TRIPLEMODE_INTERL) || \
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351 ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
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352 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
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353 ((MODE) == ADC_DMAACCESSMODE_1) || \
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354 ((MODE) == ADC_DMAACCESSMODE_2) || \
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355 ((MODE) == ADC_DMAACCESSMODE_3))
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356 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
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357 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
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358 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
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359 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
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360 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
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361 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
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362 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
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363 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
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364 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
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365 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
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366 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
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367 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
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368 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
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369 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
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370 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
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371 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
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372 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
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373 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
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374 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
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375 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \
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376 ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))
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377 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))
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378 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))
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379
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380 /**
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381 * @brief Set the selected injected Channel rank.
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382 * @param _CHANNELNB_ Channel number.
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383 * @param _RANKNB_ Rank number.
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384 * @param _JSQR_JL_ Sequence length.
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385 * @retval None
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386 */
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387 #define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
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388
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389 /**
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390 * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
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391 * if available (ADC2, ADC3 availability depends on STM32 product)
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392 * @param __HANDLE__ ADC handle
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393 * @retval Common control register ADC123 or ADC1
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394 */
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395 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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396 #define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON
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397 #else
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398 #define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON
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399 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
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400 /**
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401 * @}
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402 */
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403
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404 /* Private functions ---------------------------------------------------------*/
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405 /** @defgroup ADCEx_Private_Functions ADC Private Functions
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406 * @{
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407 */
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408
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409 /**
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410 * @}
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411 */
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412
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413 /**
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414 * @}
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415 */
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416
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417 /**
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418 * @}
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419 */
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420
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421 #ifdef __cplusplus
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422 }
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423 #endif
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424
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425 #endif /*__STM32F4xx_ADC_EX_H */
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426
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427
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428 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/