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annotate Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c @ 537:0ad0b26ec56b

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Added center / right alignment option to custom text display: Per default custom text was shown left aligned. Using '^' for center and '?' for right alignment the display of the custom text may now be improved. For proper operation the alignment had to be set to common handling mode and the blank characters had to be removed from the transmitted string. To avoid display of special strings (e.g. multilanguage) the write text via com interface will now block special characters
author Ideenmodellierer
date Wed, 07 Oct 2020 18:07:10 +0200
parents c78bcbd5deda
children
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_pwr.c
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4 * @author MCD Application Team
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5 * @brief PWR HAL module driver.
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6 * This file provides firmware functions to manage the following
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7 * functionalities of the Power Controller (PWR) peripheral:
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8 * + Initialization and de-initialization functions
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9 * + Peripheral Control functions
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10 *
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11 ******************************************************************************
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12 * @attention
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13 *
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14 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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15 *
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16 * Redistribution and use in source and binary forms, with or without modification,
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17 * are permitted provided that the following conditions are met:
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18 * 1. Redistributions of source code must retain the above copyright notice,
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19 * this list of conditions and the following disclaimer.
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20 * 2. Redistributions in binary form must reproduce the above copyright notice,
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21 * this list of conditions and the following disclaimer in the documentation
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22 * and/or other materials provided with the distribution.
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23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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24 * may be used to endorse or promote products derived from this software
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25 * without specific prior written permission.
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26 *
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27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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37 *
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38 ******************************************************************************
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39 */
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40
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41 /* Includes ------------------------------------------------------------------*/
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42 #include "stm32f4xx_hal.h"
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43
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44 /** @addtogroup STM32F4xx_HAL_Driver
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45 * @{
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46 */
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47
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48 /** @defgroup PWR PWR
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49 * @brief PWR HAL module driver
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50 * @{
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51 */
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52
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53 #ifdef HAL_PWR_MODULE_ENABLED
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54
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55 /* Private typedef -----------------------------------------------------------*/
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56 /* Private define ------------------------------------------------------------*/
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57 /** @addtogroup PWR_Private_Constants
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58 * @{
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59 */
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60
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61 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
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62 * @{
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63 */
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64 #define PVD_MODE_IT 0x00010000U
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65 #define PVD_MODE_EVT 0x00020000U
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66 #define PVD_RISING_EDGE 0x00000001U
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67 #define PVD_FALLING_EDGE 0x00000002U
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68 /**
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69 * @}
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70 */
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71
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72 /**
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73 * @}
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74 */
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75 /* Private macro -------------------------------------------------------------*/
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76 /* Private variables ---------------------------------------------------------*/
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77 /* Private function prototypes -----------------------------------------------*/
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78 /* Private functions ---------------------------------------------------------*/
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79
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80 /** @defgroup PWR_Exported_Functions PWR Exported Functions
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81 * @{
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82 */
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83
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84 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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85 * @brief Initialization and de-initialization functions
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86 *
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87 @verbatim
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88 ===============================================================================
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89 ##### Initialization and de-initialization functions #####
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90 ===============================================================================
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91 [..]
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92 After reset, the backup domain (RTC registers, RTC backup data
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93 registers and backup SRAM) is protected against possible unwanted
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94 write accesses.
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95 To enable access to the RTC Domain and RTC registers, proceed as follows:
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96 (+) Enable the Power Controller (PWR) APB1 interface clock using the
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97 __HAL_RCC_PWR_CLK_ENABLE() macro.
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98 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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99
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100 @endverbatim
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101 * @{
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102 */
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103
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104 /**
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105 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
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106 * @retval None
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107 */
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108 void HAL_PWR_DeInit(void)
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109 {
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110 __HAL_RCC_PWR_FORCE_RESET();
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111 __HAL_RCC_PWR_RELEASE_RESET();
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112 }
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113
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114 /**
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115 * @brief Enables access to the backup domain (RTC registers, RTC
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116 * backup data registers and backup SRAM).
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117 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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118 * Backup Domain Access should be kept enabled.
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119 * @retval None
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120 */
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121 void HAL_PWR_EnableBkUpAccess(void)
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122 {
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123 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
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124 }
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125
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126 /**
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127 * @brief Disables access to the backup domain (RTC registers, RTC
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128 * backup data registers and backup SRAM).
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129 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
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130 * Backup Domain Access should be kept enabled.
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131 * @retval None
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132 */
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133 void HAL_PWR_DisableBkUpAccess(void)
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134 {
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135 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
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136 }
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137
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138 /**
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139 * @}
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140 */
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141
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142 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
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143 * @brief Low Power modes configuration functions
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144 *
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145 @verbatim
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146
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147 ===============================================================================
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148 ##### Peripheral Control functions #####
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149 ===============================================================================
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150
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151 *** PVD configuration ***
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152 =========================
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153 [..]
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154 (+) The PVD is used to monitor the VDD power supply by comparing it to a
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155 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
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156 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
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157 than the PVD threshold. This event is internally connected to the EXTI
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158 line16 and can generate an interrupt if enabled. This is done through
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159 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
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160 (+) The PVD is stopped in Standby mode.
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161
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162 *** Wake-up pin configuration ***
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163 ================================
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164 [..]
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165 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
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166 forced in input pull-down configuration and is active on rising edges.
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167 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
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168 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
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169 (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
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170
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171 *** Low Power modes configuration ***
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172 =====================================
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173 [..]
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174 The devices feature 3 low-power modes:
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175 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
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176 (+) Stop mode: all clocks are stopped, regulator running, regulator
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177 in low power mode
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178 (+) Standby mode: 1.2V domain powered off.
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179
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180 *** Sleep mode ***
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181 ==================
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182 [..]
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183 (+) Entry:
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184 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
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185 functions with
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186 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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187 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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188
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189 -@@- The Regulator parameter is not used for the STM32F4 family
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190 and is kept as parameter just to maintain compatibility with the
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191 lower power families (STM32L).
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192 (+) Exit:
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193 Any peripheral interrupt acknowledged by the nested vectored interrupt
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194 controller (NVIC) can wake up the device from Sleep mode.
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195
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196 *** Stop mode ***
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197 =================
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198 [..]
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199 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
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200 and the HSE RC oscillators are disabled. Internal SRAM and register contents
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201 are preserved.
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202 The voltage regulator can be configured either in normal or low-power mode.
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203 To minimize the consumption In Stop mode, FLASH can be powered off before
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204 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
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205 It can be switched on again by software after exiting the Stop mode using
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206 the HAL_PWREx_DisableFlashPowerDown() function.
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207
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208 (+) Entry:
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209 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
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210 function with:
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211 (++) Main regulator ON.
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212 (++) Low Power regulator ON.
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213 (+) Exit:
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214 Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
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215
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216 *** Standby mode ***
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217 ====================
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218 [..]
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219 (+)
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220 The Standby mode allows to achieve the lowest power consumption. It is based
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221 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
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222 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
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223 the HSE oscillator are also switched off. SRAM and register contents are lost
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224 except for the RTC registers, RTC backup registers, backup SRAM and Standby
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225 circuitry.
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226
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227 The voltage regulator is OFF.
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228
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229 (++) Entry:
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230 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
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231 (++) Exit:
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232 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
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233 tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
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234
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235 *** Auto-wake-up (AWU) from low-power mode ***
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236 =============================================
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237 [..]
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238
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239 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
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240 Wake-up event, a tamper event or a time-stamp event, without depending on
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241 an external interrupt (Auto-wake-up mode).
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242
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243 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
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244
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245 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
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246 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
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247
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248 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
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249 is necessary to configure the RTC to detect the tamper or time stamp event using the
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250 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
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251
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252 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
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253 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
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254
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255 @endverbatim
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256 * @{
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257 */
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258
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259 /**
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260 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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261 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
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262 * information for the PVD.
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263 * @note Refer to the electrical characteristics of your device datasheet for
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264 * more details about the voltage threshold corresponding to each
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265 * detection level.
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266 * @retval None
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267 */
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268 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
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269 {
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270 /* Check the parameters */
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271 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
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272 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
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273
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274 /* Set PLS[7:5] bits according to PVDLevel value */
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275 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
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276
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277 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
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278 __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
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279 __HAL_PWR_PVD_EXTI_DISABLE_IT();
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280 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
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281 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
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282
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283 /* Configure interrupt mode */
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284 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
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285 {
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286 __HAL_PWR_PVD_EXTI_ENABLE_IT();
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287 }
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288
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289 /* Configure event mode */
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290 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
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291 {
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292 __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
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293 }
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294
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295 /* Configure the edge */
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296 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
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297 {
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298 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
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299 }
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300
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301 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
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302 {
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303 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
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304 }
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305 }
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306
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307 /**
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308 * @brief Enables the Power Voltage Detector(PVD).
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309 * @retval None
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310 */
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311 void HAL_PWR_EnablePVD(void)
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312 {
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313 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
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314 }
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315
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316 /**
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317 * @brief Disables the Power Voltage Detector(PVD).
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318 * @retval None
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319 */
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320 void HAL_PWR_DisablePVD(void)
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321 {
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322 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
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323 }
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324
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325 /**
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326 * @brief Enables the Wake-up PINx functionality.
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327 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
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328 * This parameter can be one of the following values:
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329 * @arg PWR_WAKEUP_PIN1
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330 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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331 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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332 * @retval None
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333 */
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334 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
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335 {
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336 /* Check the parameter */
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337 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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338
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339 /* Enable the wake up pin */
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340 SET_BIT(PWR->CSR, WakeUpPinx);
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341 }
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342
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343 /**
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344 * @brief Disables the Wake-up PINx functionality.
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345 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
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346 * This parameter can be one of the following values:
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347 * @arg PWR_WAKEUP_PIN1
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348 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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349 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
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350 * @retval None
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351 */
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352 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
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353 {
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354 /* Check the parameter */
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355 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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356
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357 /* Disable the wake up pin */
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358 CLEAR_BIT(PWR->CSR, WakeUpPinx);
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359 }
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360
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361 /**
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362 * @brief Enters Sleep mode.
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363 *
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364 * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
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365 *
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366 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
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367 * systick interrupt when used as time base for Timeout
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368 *
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369 * @param Regulator Specifies the regulator state in SLEEP mode.
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370 * This parameter can be one of the following values:
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371 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
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372 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
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373 * @note This parameter is not used for the STM32F4 family and is kept as parameter
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374 * just to maintain compatibility with the lower power families.
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375 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
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376 * This parameter can be one of the following values:
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377 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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378 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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379 * @retval None
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380 */
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381 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
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382 {
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383 /* Check the parameters */
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384 assert_param(IS_PWR_REGULATOR(Regulator));
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385 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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386
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387 /* Clear SLEEPDEEP bit of Cortex System Control Register */
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388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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389
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390 /* Select SLEEP mode entry -------------------------------------------------*/
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391 if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
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392 {
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393 /* Request Wait For Interrupt */
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394 __WFI();
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395 }
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396 else
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397 {
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398 /* Request Wait For Event */
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399 __SEV();
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400 __WFE();
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401 __WFE();
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402 }
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403 }
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404
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405 /**
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406 * @brief Enters Stop mode.
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407 * @note In Stop mode, all I/O pins keep the same state as in Run mode.
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408 * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
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409 * the HSI RC oscillator is selected as system clock.
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410 * @note When the voltage regulator operates in low power mode, an additional
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411 * startup delay is incurred when waking up from Stop mode.
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412 * By keeping the internal regulator ON during Stop mode, the consumption
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413 * is higher although the startup time is reduced.
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414 * @param Regulator Specifies the regulator state in Stop mode.
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415 * This parameter can be one of the following values:
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416 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
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417 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
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418 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
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419 * This parameter can be one of the following values:
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420 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
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421 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
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422 * @retval None
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423 */
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424 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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425 {
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426 /* Check the parameters */
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427 assert_param(IS_PWR_REGULATOR(Regulator));
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428 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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429
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430 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
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431 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
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432
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433 /* Set SLEEPDEEP bit of Cortex System Control Register */
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434 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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435
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436 /* Select Stop mode entry --------------------------------------------------*/
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437 if(STOPEntry == PWR_STOPENTRY_WFI)
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438 {
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439 /* Request Wait For Interrupt */
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440 __WFI();
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441 }
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442 else
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443 {
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444 /* Request Wait For Event */
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445 __SEV();
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446 __WFE();
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447 __WFE();
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448 }
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449 /* Reset SLEEPDEEP bit of Cortex System Control Register */
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450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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451 }
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452
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453 /**
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454 * @brief Enters Standby mode.
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455 * @note In Standby mode, all I/O pins are high impedance except for:
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456 * - Reset pad (still available)
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457 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
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458 * Alarm out, or RTC clock calibration out.
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459 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
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460 * - WKUP pin 1 (PA0) if enabled.
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461 * @retval None
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462 */
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463 void HAL_PWR_EnterSTANDBYMode(void)
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464 {
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465 /* Select Standby mode */
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466 SET_BIT(PWR->CR, PWR_CR_PDDS);
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467
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468 /* Set SLEEPDEEP bit of Cortex System Control Register */
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469 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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470
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471 /* This option is used to ensure that store operations are completed */
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472 #if defined ( __CC_ARM)
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473 __force_stores();
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474 #endif
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475 /* Request Wait For Interrupt */
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476 __WFI();
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477 }
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478
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479 /**
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480 * @brief This function handles the PWR PVD interrupt request.
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481 * @note This API should be called under the PVD_IRQHandler().
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482 * @retval None
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483 */
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484 void HAL_PWR_PVD_IRQHandler(void)
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485 {
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486 /* Check PWR Exti flag */
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487 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
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488 {
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489 /* PWR PVD interrupt user callback */
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490 HAL_PWR_PVDCallback();
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491
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492 /* Clear PWR Exti pending bit */
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493 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
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494 }
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495 }
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496
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497 /**
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498 * @brief PWR PVD interrupt callback
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499 * @retval None
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500 */
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501 __weak void HAL_PWR_PVDCallback(void)
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502 {
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503 /* NOTE : This function Should not be modified, when the callback is needed,
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504 the HAL_PWR_PVDCallback could be implemented in the user file
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505 */
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506 }
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507
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508 /**
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509 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
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510 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
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511 * re-enters SLEEP mode when an interruption handling is over.
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512 * Setting this bit is useful when the processor is expected to run only on
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513 * interruptions handling.
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514 * @retval None
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515 */
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516 void HAL_PWR_EnableSleepOnExit(void)
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517 {
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518 /* Set SLEEPONEXIT bit of Cortex System Control Register */
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519 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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520 }
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521
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522 /**
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523 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
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524 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
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525 * re-enters SLEEP mode when an interruption handling is over.
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526 * @retval None
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527 */
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528 void HAL_PWR_DisableSleepOnExit(void)
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529 {
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530 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
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531 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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532 }
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533
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534 /**
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535 * @brief Enables CORTEX M4 SEVONPEND bit.
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536 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
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537 * WFE to wake up when an interrupt moves from inactive to pended.
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538 * @retval None
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539 */
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540 void HAL_PWR_EnableSEVOnPend(void)
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541 {
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542 /* Set SEVONPEND bit of Cortex System Control Register */
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543 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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544 }
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545
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546 /**
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547 * @brief Disables CORTEX M4 SEVONPEND bit.
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548 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
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549 * WFE to wake up when an interrupt moves from inactive to pended.
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550 * @retval None
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551 */
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552 void HAL_PWR_DisableSEVOnPend(void)
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553 {
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554 /* Clear SEVONPEND bit of Cortex System Control Register */
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555 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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556 }
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557
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558 /**
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559 * @}
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560 */
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561
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562 /**
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563 * @}
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564 */
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565
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566 #endif /* HAL_PWR_MODULE_ENABLED */
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567 /**
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568 * @}
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569 */
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570
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571 /**
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572 * @}
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573 */
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574
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575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/