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annotate Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_wwdg.h @ 513:0680975c39b8

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author heinrichsweikamp
date Mon, 31 Aug 2020 20:06:59 +0200
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_ll_wwdg.h
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4 * @author MCD Application Team
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5 * @brief Header file of WWDG LL module.
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6 ******************************************************************************
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7 * @attention
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8 *
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9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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10 *
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11 * Redistribution and use in source and binary forms, with or without modification,
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12 * are permitted provided that the following conditions are met:
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13 * 1. Redistributions of source code must retain the above copyright notice,
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14 * this list of conditions and the following disclaimer.
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15 * 2. Redistributions in binary form must reproduce the above copyright notice,
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16 * this list of conditions and the following disclaimer in the documentation
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17 * and/or other materials provided with the distribution.
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18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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19 * may be used to endorse or promote products derived from this software
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20 * without specific prior written permission.
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21 *
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22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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32 *
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33 ******************************************************************************
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34 */
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35
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36 /* Define to prevent recursive inclusion -------------------------------------*/
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37 #ifndef __STM32F4xx_LL_WWDG_H
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38 #define __STM32F4xx_LL_WWDG_H
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39
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40 #ifdef __cplusplus
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41 extern "C" {
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42 #endif
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43
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44 /* Includes ------------------------------------------------------------------*/
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45 #include "stm32f4xx.h"
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46
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47 /** @addtogroup STM32F4xx_LL_Driver
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48 * @{
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49 */
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50
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51 #if defined (WWDG)
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52
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53 /** @defgroup WWDG_LL WWDG
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54 * @{
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55 */
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56
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57 /* Private types -------------------------------------------------------------*/
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58 /* Private variables ---------------------------------------------------------*/
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59
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60 /* Private constants ---------------------------------------------------------*/
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61
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62 /* Private macros ------------------------------------------------------------*/
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63
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64 /* Exported types ------------------------------------------------------------*/
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65 /* Exported constants --------------------------------------------------------*/
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66 /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
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67 * @{
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68 */
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69
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70
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71 /** @defgroup WWDG_LL_EC_IT IT Defines
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72 * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
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73 * @{
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74 */
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75 #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
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76 /**
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77 * @}
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78 */
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79
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80 /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
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81 * @{
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82 */
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83 #define LL_WWDG_PRESCALER_1 (uint32_t)0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
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84 #define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
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85 #define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
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86 #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
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87 /**
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88 * @}
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89 */
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90
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91 /**
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92 * @}
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93 */
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94
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95 /* Exported macro ------------------------------------------------------------*/
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96 /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
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97 * @{
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98 */
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99 /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
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100 * @{
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101 */
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102 /**
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103 * @brief Write a value in WWDG register
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104 * @param __INSTANCE__ WWDG Instance
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105 * @param __REG__ Register to be written
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106 * @param __VALUE__ Value to be written in the register
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107 * @retval None
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108 */
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109 #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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110
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111 /**
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112 * @brief Read a value in WWDG register
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113 * @param __INSTANCE__ WWDG Instance
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114 * @param __REG__ Register to be read
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115 * @retval Register value
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116 */
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117 #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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118 /**
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119 * @}
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120 */
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121
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122
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123 /**
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124 * @}
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125 */
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126
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127 /* Exported functions --------------------------------------------------------*/
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128 /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
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129 * @{
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130 */
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131
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132 /** @defgroup WWDG_LL_EF_Configuration Configuration
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133 * @{
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134 */
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135 /**
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136 * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
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137 * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
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138 * then it cannot be disabled again except by a reset.
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139 * This bit is set by software and only cleared by hardware after a reset.
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140 * When WDGA = 1, the watchdog can generate a reset.
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141 * @rmtoll CR WDGA LL_WWDG_Enable
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142 * @param WWDGx WWDG Instance
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143 * @retval None
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144 */
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145 __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
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146 {
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147 SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
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148 }
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149
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150 /**
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151 * @brief Checks if Window Watchdog is enabled
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152 * @rmtoll CR WDGA LL_WWDG_IsEnabled
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153 * @param WWDGx WWDG Instance
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154 * @retval State of bit (1 or 0).
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155 */
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156 __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
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157 {
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158 return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
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159 }
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160
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161 /**
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162 * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
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163 * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
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164 * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
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165 * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
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166 * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
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167 * @rmtoll CR T LL_WWDG_SetCounter
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168 * @param WWDGx WWDG Instance
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169 * @param Counter 0..0x7F (7 bit counter value)
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170 * @retval None
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171 */
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172 __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
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173 {
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174 MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
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175 }
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176
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177 /**
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178 * @brief Return current Watchdog Counter Value (7 bits counter value)
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179 * @rmtoll CR T LL_WWDG_GetCounter
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180 * @param WWDGx WWDG Instance
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181 * @retval 7 bit Watchdog Counter value
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182 */
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183 __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
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184 {
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185 return (uint32_t)(READ_BIT(WWDGx->CR, WWDG_CR_T));
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186 }
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187
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188 /**
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189 * @brief Set the time base of the prescaler (WDGTB).
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190 * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
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191 * is decremented every (4096 x 2expWDGTB) PCLK cycles
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192 * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
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193 * @param WWDGx WWDG Instance
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194 * @param Prescaler This parameter can be one of the following values:
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195 * @arg @ref LL_WWDG_PRESCALER_1
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196 * @arg @ref LL_WWDG_PRESCALER_2
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197 * @arg @ref LL_WWDG_PRESCALER_4
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198 * @arg @ref LL_WWDG_PRESCALER_8
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199 * @retval None
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200 */
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201 __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
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202 {
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203 MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
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204 }
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205
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206 /**
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207 * @brief Return current Watchdog Prescaler Value
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208 * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
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209 * @param WWDGx WWDG Instance
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210 * @retval Returned value can be one of the following values:
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211 * @arg @ref LL_WWDG_PRESCALER_1
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212 * @arg @ref LL_WWDG_PRESCALER_2
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213 * @arg @ref LL_WWDG_PRESCALER_4
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214 * @arg @ref LL_WWDG_PRESCALER_8
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215 */
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216 __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
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217 {
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218 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
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219 }
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220
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221 /**
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222 * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
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223 * @note This window value defines when write in the WWDG_CR register
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224 * to program Watchdog counter is allowed.
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225 * Watchdog counter value update must occur only when the counter value
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226 * is lower than the Watchdog window register value.
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227 * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
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228 * (in the control register) is refreshed before the downcounter has reached
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229 * the watchdog window register value.
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230 * Physically is possible to set the Window lower then 0x40 but it is not recommended.
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231 * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
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232 * @rmtoll CFR W LL_WWDG_SetWindow
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233 * @param WWDGx WWDG Instance
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234 * @param Window 0x00..0x7F (7 bit Window value)
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235 * @retval None
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236 */
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237 __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
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238 {
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239 MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
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240 }
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241
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242 /**
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243 * @brief Return current Watchdog Window Value (7 bits value)
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244 * @rmtoll CFR W LL_WWDG_GetWindow
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245 * @param WWDGx WWDG Instance
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246 * @retval 7 bit Watchdog Window value
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247 */
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248 __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
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249 {
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250 return (uint32_t)(READ_BIT(WWDGx->CFR, WWDG_CFR_W));
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251 }
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252
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253 /**
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254 * @}
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255 */
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256
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257 /** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
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258 * @{
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259 */
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260 /**
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261 * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
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262 * @note This bit is set by hardware when the counter has reached the value 0x40.
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263 * It must be cleared by software by writing 0.
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264 * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
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265 * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
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266 * @param WWDGx WWDG Instance
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267 * @retval State of bit (1 or 0).
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268 */
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269 __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
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270 {
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271 return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
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272 }
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273
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274 /**
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275 * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
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276 * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
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277 * @param WWDGx WWDG Instance
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278 * @retval None
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279 */
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280 __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
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281 {
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282 WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
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283 }
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284
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285 /**
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286 * @}
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287 */
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288
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289 /** @defgroup WWDG_LL_EF_IT_Management IT_Management
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290 * @{
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291 */
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292 /**
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293 * @brief Enable the Early Wakeup Interrupt.
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294 * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
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295 * This interrupt is only cleared by hardware after a reset
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296 * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
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297 * @param WWDGx WWDG Instance
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298 * @retval None
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299 */
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300 __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
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301 {
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302 SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
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303 }
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304
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305 /**
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306 * @brief Check if Early Wakeup Interrupt is enabled
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307 * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
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308 * @param WWDGx WWDG Instance
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309 * @retval State of bit (1 or 0).
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310 */
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311 __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
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312 {
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313 return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
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314 }
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315
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316 /**
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317 * @}
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318 */
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319
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320 /**
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321 * @}
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322 */
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323
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324 /**
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325 * @}
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326 */
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327
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328 #endif /* WWDG */
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329
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330 /**
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331 * @}
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332 */
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333
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334 #ifdef __cplusplus
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335 }
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336 #endif
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337
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338 #endif /* __STM32F4xx_LL_WWDG_H */
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339
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340 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/