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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_rcc.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief RCC HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of the Reset and Clock Control (RCC) peripheral:
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10 * + Initialization and de-initialization functions
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11 * + Peripheral Control functions
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12 *
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13 @verbatim
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14 ==============================================================================
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15 ##### RCC specific features #####
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16 ==============================================================================
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17 [..]
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18 After reset the device is running from Internal High Speed oscillator
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19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
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20 and I-Cache are disabled, and all peripherals are off except internal
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21 SRAM, Flash and JTAG.
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22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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23 all peripherals mapped on these busses are running at HSI speed.
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24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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25 (+) All GPIOs are in input floating state, except the JTAG pins which
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26 are assigned to be used for debug purpose.
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27
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28 [..]
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29 Once the device started from reset, the user application has to:
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30 (+) Configure the clock source to be used to drive the System clock
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31 (if the application needs higher frequency/performance)
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32 (+) Configure the System clock frequency and Flash settings
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33 (+) Configure the AHB and APB busses prescalers
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34 (+) Enable the clock for the peripheral(s) to be used
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35 (+) Configure the clock source(s) for peripherals which clocks are not
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36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
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37
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38 ##### RCC Limitations #####
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39 ==============================================================================
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40 [..]
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41 A delay between an RCC peripheral clock enable and the effective peripheral
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42 enabling should be taken into account in order to manage the peripheral read/write
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43 from/to registers.
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44 (+) This delay depends on the peripheral mapping.
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45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
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46 after the clock enable bit is set on the hardware register
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47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
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48 after the clock enable bit is set on the hardware register
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49
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50 [..]
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51 Possible Workarounds:
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52 (#) Enable the peripheral clock sometimes before the peripheral read/write
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53 register is required.
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54 (#) For AHB peripheral, insert two dummy read to the peripheral register.
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55 (#) For APB peripheral, insert a dummy read to the peripheral register.
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56
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57 @endverbatim
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58 ******************************************************************************
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59 * @attention
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60 *
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61 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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62 *
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63 * Redistribution and use in source and binary forms, with or without modification,
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64 * are permitted provided that the following conditions are met:
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65 * 1. Redistributions of source code must retain the above copyright notice,
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66 * this list of conditions and the following disclaimer.
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67 * 2. Redistributions in binary form must reproduce the above copyright notice,
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68 * this list of conditions and the following disclaimer in the documentation
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69 * and/or other materials provided with the distribution.
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70 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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71 * may be used to endorse or promote products derived from this software
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72 * without specific prior written permission.
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73 *
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74 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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75 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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76 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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77 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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78 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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79 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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80 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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81 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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82 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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84 *
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85 ******************************************************************************
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86 */
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87
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88 /* Includes ------------------------------------------------------------------*/
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89 #include "stm32f4xx_hal.h"
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90
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91 /** @addtogroup STM32F4xx_HAL_Driver
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92 * @{
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93 */
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94
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95 /** @defgroup RCC RCC
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96 * @brief RCC HAL module driver
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97 * @{
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98 */
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99
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100 #ifdef HAL_RCC_MODULE_ENABLED
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101
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102 /* Private typedef -----------------------------------------------------------*/
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103 /* Private define ------------------------------------------------------------*/
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104 /** @addtogroup RCC_Private_Constants
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105 * @{
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106 */
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107 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
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108 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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109 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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110 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
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111 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
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112
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113 /* Private macro -------------------------------------------------------------*/
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114 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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115 #define MCO1_GPIO_PORT GPIOA
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116 #define MCO1_PIN GPIO_PIN_8
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117
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118 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
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119 #define MCO2_GPIO_PORT GPIOC
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120 #define MCO2_PIN GPIO_PIN_9
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121 /**
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122 * @}
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123 */
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124
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125 /* Private variables ---------------------------------------------------------*/
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126 /** @defgroup RCC_Private_Variables RCC Private Variables
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127 * @{
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128 */
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129 const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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130 /**
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131 * @}
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132 */
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133
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134 /* Private function prototypes -----------------------------------------------*/
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135 /* Private functions ---------------------------------------------------------*/
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136
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137 /** @defgroup RCC_Exported_Functions RCC Exported Functions
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138 * @{
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139 */
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140
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141 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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142 * @brief Initialization and Configuration functions
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143 *
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144 @verbatim
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145 ===============================================================================
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146 ##### Initialization and de-initialization functions #####
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147 ===============================================================================
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148 [..]
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149 This section provides functions allowing to configure the internal/external oscillators
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150 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
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151 and APB2).
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152
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153 [..] Internal/external clock and PLL configuration
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154 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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155 the PLL as System clock source.
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156
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157 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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158 clock source.
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159
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160 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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161 through the PLL as System clock source. Can be used also as RTC clock source.
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162
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163 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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164
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165 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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166 (++) The first output is used to generate the high speed system clock (up to 168 MHz)
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167 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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168 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
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169
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170 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
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171 and if a HSE clock failure occurs(HSE used directly or through PLL as System
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172 clock source), the System clocks automatically switched to HSI and an interrupt
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173 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
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174 (Non-Maskable Interrupt) exception vector.
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175
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176 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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177 clock (through a configurable prescaler) on PA8 pin.
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178
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179 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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180 clock (through a configurable prescaler) on PC9 pin.
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181
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182 [..] System, AHB and APB busses clocks configuration
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183 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
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184 HSE and PLL.
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185 The AHB clock (HCLK) is derived from System clock through configurable
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186 prescaler and used to clock the CPU, memory and peripherals mapped
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187 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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188 from AHB clock through configurable prescalers and used to clock
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189 the peripherals mapped on these busses. You can use
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190 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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191
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192 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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193 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
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194 from an external clock mapped on the I2S_CKIN pin.
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195 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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196 (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
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197 from an external clock mapped on the I2S_CKIN pin.
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198 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
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199 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
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200 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
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201 macros to configure this clock.
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202 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
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203 to work correctly, while the SDIO require a frequency equal or lower than
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204 to 48. This clock is derived of the main PLL through PLLQ divider.
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205 (+@) IWDG clock which is always the LSI clock.
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206
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207 (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
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208 frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
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209 Depending on the device voltage range, the maximum frequency should
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210 be adapted accordingly (refer to the product datasheets for more details).
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211
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212 (#) For the STM32F42xxx and STM32F43xxx devices, the maximum frequency
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213 of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
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214 Depending on the device voltage range, the maximum frequency should
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215 be adapted accordingly (refer to the product datasheets for more details).
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216
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217 (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
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218 PCLK2 84 MHz and PCLK1 42 MHz.
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219 Depending on the device voltage range, the maximum frequency should
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220 be adapted accordingly (refer to the product datasheets for more details).
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221 @endverbatim
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222 * @{
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223 */
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224
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225 /**
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226 * @brief Resets the RCC clock configuration to the default reset state.
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227 * @note The default reset state of the clock configuration is given below:
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228 * - HSI ON and used as system clock source
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229 * - HSE, PLL and PLLI2S OFF
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230 * - AHB, APB1 and APB2 prescaler set to 1.
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231 * - CSS, MCO1 and MCO2 OFF
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232 * - All interrupts disabled
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233 * @note This function doesn't modify the configuration of the
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234 * - Peripheral clocks
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235 * - LSI, LSE and RTC clocks
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236 * @retval None
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237 */
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238 void HAL_RCC_DeInit(void)
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239 {
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240 /* Set HSION bit */
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241 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
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242
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243 /* Reset CFGR register */
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244 CLEAR_REG(RCC->CFGR);
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245
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246 /* Reset HSEON, CSSON, PLLON, PLLI2S */
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247 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
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248
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249 /* Reset PLLCFGR register */
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250 CLEAR_REG(RCC->PLLCFGR);
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251 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
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252
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253 /* Reset PLLI2SCFGR register */
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254 CLEAR_REG(RCC->PLLI2SCFGR);
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255 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
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256
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257 /* Reset HSEBYP bit */
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258 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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259
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260 /* Disable all interrupts */
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261 CLEAR_REG(RCC->CIR);
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262 }
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263
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264 /**
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265 * @brief Initializes the RCC Oscillators according to the specified parameters in the
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266 * RCC_OscInitTypeDef.
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267 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
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268 * contains the configuration information for the RCC Oscillators.
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269 * @note The PLL is not disabled when used as system clock.
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270 * @retval HAL status
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271 */
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272 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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273 {
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274 uint32_t tickstart = 0;
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275
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276 /* Check the parameters */
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277 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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278 /*------------------------------- HSE Configuration ------------------------*/
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279 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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280 {
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281 /* Check the parameters */
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282 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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283 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
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284 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
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285 {
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286 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
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287 {
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288 return HAL_ERROR;
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289 }
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290 }
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291 else
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292 {
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293 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
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294 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
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295
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296 /* Get Start Tick*/
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297 tickstart = HAL_GetTick();
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298
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299 /* Wait till HSE is disabled */
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300 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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301 {
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302 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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303 {
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304 return HAL_TIMEOUT;
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305 }
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306 }
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307
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308 /* Set the new HSE configuration ---------------------------------------*/
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309 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
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310
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311 /* Check the HSE State */
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312 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
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313 {
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314 /* Get Start Tick*/
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315 tickstart = HAL_GetTick();
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316
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317 /* Wait till HSE is ready */
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318 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
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319 {
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320 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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321 {
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322 return HAL_TIMEOUT;
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323 }
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324 }
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325 }
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326 else
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327 {
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328 /* Get Start Tick*/
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329 tickstart = HAL_GetTick();
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330
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331 /* Wait till HSE is bypassed or disabled */
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332 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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333 {
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334 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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335 {
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336 return HAL_TIMEOUT;
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337 }
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338 }
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339 }
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340 }
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341 }
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342 /*----------------------------- HSI Configuration --------------------------*/
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343 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
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344 {
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345 /* Check the parameters */
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346 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
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347 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
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348
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349 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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350 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
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351 {
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352 /* When HSI is used as system clock it will not disabled */
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353 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
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354 {
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355 return HAL_ERROR;
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356 }
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357 /* Otherwise, just the calibration is allowed */
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358 else
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359 {
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360 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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361 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
362 }
|
|
|
363 }
|
|
|
364 else
|
|
|
365 {
|
|
|
366 /* Check the HSI State */
|
|
|
367 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
|
|
|
368 {
|
|
|
369 /* Enable the Internal High Speed oscillator (HSI). */
|
|
|
370 __HAL_RCC_HSI_ENABLE();
|
|
|
371
|
|
|
372 /* Get Start Tick*/
|
|
|
373 tickstart = HAL_GetTick();
|
|
|
374
|
|
|
375 /* Wait till HSI is ready */
|
|
|
376 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
377 {
|
|
|
378 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
|
379 {
|
|
|
380 return HAL_TIMEOUT;
|
|
|
381 }
|
|
|
382 }
|
|
|
383
|
|
|
384 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
|
385 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
|
386 }
|
|
|
387 else
|
|
|
388 {
|
|
|
389 /* Disable the Internal High Speed oscillator (HSI). */
|
|
|
390 __HAL_RCC_HSI_DISABLE();
|
|
|
391
|
|
|
392 /* Get Start Tick*/
|
|
|
393 tickstart = HAL_GetTick();
|
|
|
394
|
|
|
395 /* Wait till HSI is ready */
|
|
|
396 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
|
|
397 {
|
|
|
398 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
|
|
|
399 {
|
|
|
400 return HAL_TIMEOUT;
|
|
|
401 }
|
|
|
402 }
|
|
|
403 }
|
|
|
404 }
|
|
|
405 }
|
|
|
406 /*------------------------------ LSI Configuration -------------------------*/
|
|
|
407 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
|
408 {
|
|
|
409 /* Check the parameters */
|
|
|
410 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
411
|
|
|
412 /* Check the LSI State */
|
|
|
413 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
|
|
|
414 {
|
|
|
415 /* Enable the Internal Low Speed oscillator (LSI). */
|
|
|
416 __HAL_RCC_LSI_ENABLE();
|
|
|
417
|
|
|
418 /* Get Start Tick*/
|
|
|
419 tickstart = HAL_GetTick();
|
|
|
420
|
|
|
421 /* Wait till LSI is ready */
|
|
|
422 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
|
|
|
423 {
|
|
|
424 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
|
425 {
|
|
|
426 return HAL_TIMEOUT;
|
|
|
427 }
|
|
|
428 }
|
|
|
429 }
|
|
|
430 else
|
|
|
431 {
|
|
|
432 /* Disable the Internal Low Speed oscillator (LSI). */
|
|
|
433 __HAL_RCC_LSI_DISABLE();
|
|
|
434
|
|
|
435 /* Get Start Tick*/
|
|
|
436 tickstart = HAL_GetTick();
|
|
|
437
|
|
|
438 /* Wait till LSI is ready */
|
|
|
439 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
|
|
|
440 {
|
|
|
441 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
|
|
|
442 {
|
|
|
443 return HAL_TIMEOUT;
|
|
|
444 }
|
|
|
445 }
|
|
|
446 }
|
|
|
447 }
|
|
|
448 /*------------------------------ LSE Configuration -------------------------*/
|
|
|
449 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
|
450 {
|
|
|
451 /* Check the parameters */
|
|
|
452 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
453
|
|
|
454 /* Enable Power Clock*/
|
|
|
455 __HAL_RCC_PWR_CLK_ENABLE();
|
|
|
456
|
|
|
457 /* Enable write access to Backup domain */
|
|
|
458 PWR->CR |= PWR_CR_DBP;
|
|
|
459
|
|
|
460 /* Wait for Backup domain Write protection disable */
|
|
|
461 tickstart = HAL_GetTick();
|
|
|
462
|
|
|
463 while((PWR->CR & PWR_CR_DBP) == RESET)
|
|
|
464 {
|
|
|
465 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
|
|
|
466 {
|
|
|
467 return HAL_TIMEOUT;
|
|
|
468 }
|
|
|
469 }
|
|
|
470
|
|
|
471 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
|
|
|
472 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
|
|
|
473
|
|
|
474 /* Get Start Tick*/
|
|
|
475 tickstart = HAL_GetTick();
|
|
|
476
|
|
|
477 /* Wait till LSE is ready */
|
|
|
478 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
479 {
|
|
|
480 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
481 {
|
|
|
482 return HAL_TIMEOUT;
|
|
|
483 }
|
|
|
484 }
|
|
|
485
|
|
|
486 /* Set the new LSE configuration -----------------------------------------*/
|
|
|
487 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
|
488 /* Check the LSE State */
|
|
|
489 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
|
|
|
490 {
|
|
|
491 /* Get Start Tick*/
|
|
|
492 tickstart = HAL_GetTick();
|
|
|
493
|
|
|
494 /* Wait till LSE is ready */
|
|
|
495 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
|
|
|
496 {
|
|
|
497 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
498 {
|
|
|
499 return HAL_TIMEOUT;
|
|
|
500 }
|
|
|
501 }
|
|
|
502 }
|
|
|
503 else
|
|
|
504 {
|
|
|
505 /* Get Start Tick*/
|
|
|
506 tickstart = HAL_GetTick();
|
|
|
507
|
|
|
508 /* Wait till LSE is ready */
|
|
|
509 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
|
510 {
|
|
|
511 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
|
512 {
|
|
|
513 return HAL_TIMEOUT;
|
|
|
514 }
|
|
|
515 }
|
|
|
516 }
|
|
|
517 }
|
|
|
518 /*-------------------------------- PLL Configuration -----------------------*/
|
|
|
519 /* Check the parameters */
|
|
|
520 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
521 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
|
522 {
|
|
|
523 /* Check if the PLL is used as system clock or not */
|
|
|
524 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
|
525 {
|
|
|
526 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
|
527 {
|
|
|
528 /* Check the parameters */
|
|
|
529 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
|
530 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
|
|
|
531 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
|
|
|
532 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
|
|
|
533 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
|
534
|
|
|
535 /* Disable the main PLL. */
|
|
|
536 __HAL_RCC_PLL_DISABLE();
|
|
|
537
|
|
|
538 /* Get Start Tick*/
|
|
|
539 tickstart = HAL_GetTick();
|
|
|
540
|
|
|
541 /* Wait till PLL is ready */
|
|
|
542 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
543 {
|
|
|
544 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
|
545 {
|
|
|
546 return HAL_TIMEOUT;
|
|
|
547 }
|
|
|
548 }
|
|
|
549
|
|
|
550 /* Configure the main PLL clock source, multiplication and division factors. */
|
|
|
551 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
|
552 RCC_OscInitStruct->PLL.PLLM,
|
|
|
553 RCC_OscInitStruct->PLL.PLLN,
|
|
|
554 RCC_OscInitStruct->PLL.PLLP,
|
|
|
555 RCC_OscInitStruct->PLL.PLLQ);
|
|
|
556 /* Enable the main PLL. */
|
|
|
557 __HAL_RCC_PLL_ENABLE();
|
|
|
558
|
|
|
559 /* Get Start Tick*/
|
|
|
560 tickstart = HAL_GetTick();
|
|
|
561
|
|
|
562 /* Wait till PLL is ready */
|
|
|
563 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
564 {
|
|
|
565 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
|
566 {
|
|
|
567 return HAL_TIMEOUT;
|
|
|
568 }
|
|
|
569 }
|
|
|
570 }
|
|
|
571 else
|
|
|
572 {
|
|
|
573 /* Disable the main PLL. */
|
|
|
574 __HAL_RCC_PLL_DISABLE();
|
|
|
575
|
|
|
576 /* Get Start Tick*/
|
|
|
577 tickstart = HAL_GetTick();
|
|
|
578
|
|
|
579 /* Wait till PLL is ready */
|
|
|
580 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
|
581 {
|
|
|
582 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
|
583 {
|
|
|
584 return HAL_TIMEOUT;
|
|
|
585 }
|
|
|
586 }
|
|
|
587 }
|
|
|
588 }
|
|
|
589 else
|
|
|
590 {
|
|
|
591 return HAL_ERROR;
|
|
|
592 }
|
|
|
593 }
|
|
|
594 return HAL_OK;
|
|
|
595 }
|
|
|
596
|
|
|
597 /**
|
|
|
598 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
|
|
|
599 * parameters in the RCC_ClkInitStruct.
|
|
|
600 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
|
|
|
601 * contains the configuration information for the RCC peripheral.
|
|
|
602 * @param FLatency: FLASH Latency, this parameter depend on device selected
|
|
|
603 *
|
|
|
604 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
|
605 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
|
|
|
606 *
|
|
|
607 * @note The HSI is used (enabled by hardware) as system clock source after
|
|
|
608 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
|
|
|
609 * of failure of the HSE used directly or indirectly as system clock
|
|
|
610 * (if the Clock Security System CSS is enabled).
|
|
|
611 *
|
|
|
612 * @note A switch from one clock source to another occurs only if the target
|
|
|
613 * clock source is ready (clock stable after startup delay or PLL locked).
|
|
|
614 * If a clock source which is not yet ready is selected, the switch will
|
|
|
615 * occur when the clock source will be ready.
|
|
|
616 *
|
|
|
617 * @note Depending on the device voltage range, the software has to set correctly
|
|
|
618 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
|
619 * (for more details refer to section above "Initialization/de-initialization functions")
|
|
|
620 * @retval None
|
|
|
621 */
|
|
|
622 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
|
623 {
|
|
|
624 uint32_t tickstart = 0;
|
|
|
625
|
|
|
626 /* Check the parameters */
|
|
|
627 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
|
|
|
628 assert_param(IS_FLASH_LATENCY(FLatency));
|
|
|
629
|
|
|
630 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
|
631 must be correctly programmed according to the frequency of the CPU clock
|
|
|
632 (HCLK) and the supply voltage of the device. */
|
|
|
633
|
|
|
634 /* Increasing the CPU frequency */
|
|
|
635 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
|
|
|
636 {
|
|
|
637 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
638 __HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
639
|
|
|
640 /* Check that the new number of wait states is taken into account to access the Flash
|
|
|
641 memory by reading the FLASH_ACR register */
|
|
|
642 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
|
643 {
|
|
|
644 return HAL_ERROR;
|
|
|
645 }
|
|
|
646
|
|
|
647 /*-------------------------- HCLK Configuration --------------------------*/
|
|
|
648 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
649 {
|
|
|
650 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
651 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
652 }
|
|
|
653
|
|
|
654 /*------------------------- SYSCLK Configuration ---------------------------*/
|
|
|
655 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
|
656 {
|
|
|
657 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
658
|
|
|
659 /* HSE is selected as System Clock Source */
|
|
|
660 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
661 {
|
|
|
662 /* Check the HSE ready flag */
|
|
|
663 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
664 {
|
|
|
665 return HAL_ERROR;
|
|
|
666 }
|
|
|
667 }
|
|
|
668 /* PLL is selected as System Clock Source */
|
|
|
669 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
670 {
|
|
|
671 /* Check the PLL ready flag */
|
|
|
672 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
673 {
|
|
|
674 return HAL_ERROR;
|
|
|
675 }
|
|
|
676 }
|
|
|
677 /* HSI is selected as System Clock Source */
|
|
|
678 else
|
|
|
679 {
|
|
|
680 /* Check the HSI ready flag */
|
|
|
681 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
682 {
|
|
|
683 return HAL_ERROR;
|
|
|
684 }
|
|
|
685 }
|
|
|
686 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
|
687
|
|
|
688 /* Get Start Tick*/
|
|
|
689 tickstart = HAL_GetTick();
|
|
|
690
|
|
|
691 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
692 {
|
|
|
693 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
|
|
|
694 {
|
|
|
695 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
696 {
|
|
|
697 return HAL_TIMEOUT;
|
|
|
698 }
|
|
|
699 }
|
|
|
700 }
|
|
|
701 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
702 {
|
|
|
703 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
|
704 {
|
|
|
705 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
706 {
|
|
|
707 return HAL_TIMEOUT;
|
|
|
708 }
|
|
|
709 }
|
|
|
710 }
|
|
|
711 else
|
|
|
712 {
|
|
|
713 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
|
|
|
714 {
|
|
|
715 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
716 {
|
|
|
717 return HAL_TIMEOUT;
|
|
|
718 }
|
|
|
719 }
|
|
|
720 }
|
|
|
721 }
|
|
|
722 }
|
|
|
723 /* Decreasing the CPU frequency */
|
|
|
724 else
|
|
|
725 {
|
|
|
726 /*-------------------------- HCLK Configuration --------------------------*/
|
|
|
727 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
|
728 {
|
|
|
729 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
730 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
|
731 }
|
|
|
732
|
|
|
733 /*------------------------- SYSCLK Configuration -------------------------*/
|
|
|
734 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
|
735 {
|
|
|
736 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
737
|
|
|
738 /* HSE is selected as System Clock Source */
|
|
|
739 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
740 {
|
|
|
741 /* Check the HSE ready flag */
|
|
|
742 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
|
743 {
|
|
|
744 return HAL_ERROR;
|
|
|
745 }
|
|
|
746 }
|
|
|
747 /* PLL is selected as System Clock Source */
|
|
|
748 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
749 {
|
|
|
750 /* Check the PLL ready flag */
|
|
|
751 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
|
752 {
|
|
|
753 return HAL_ERROR;
|
|
|
754 }
|
|
|
755 }
|
|
|
756 /* HSI is selected as System Clock Source */
|
|
|
757 else
|
|
|
758 {
|
|
|
759 /* Check the HSI ready flag */
|
|
|
760 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
|
761 {
|
|
|
762 return HAL_ERROR;
|
|
|
763 }
|
|
|
764 }
|
|
|
765 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
|
766
|
|
|
767 /* Get Start Tick*/
|
|
|
768 tickstart = HAL_GetTick();
|
|
|
769
|
|
|
770 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
|
771 {
|
|
|
772 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
|
|
|
773 {
|
|
|
774 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
775 {
|
|
|
776 return HAL_TIMEOUT;
|
|
|
777 }
|
|
|
778 }
|
|
|
779 }
|
|
|
780 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
|
781 {
|
|
|
782 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
|
|
|
783 {
|
|
|
784 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
785 {
|
|
|
786 return HAL_TIMEOUT;
|
|
|
787 }
|
|
|
788 }
|
|
|
789 }
|
|
|
790 else
|
|
|
791 {
|
|
|
792 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
|
|
|
793 {
|
|
|
794 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
|
795 {
|
|
|
796 return HAL_TIMEOUT;
|
|
|
797 }
|
|
|
798 }
|
|
|
799 }
|
|
|
800 }
|
|
|
801
|
|
|
802 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
|
803 __HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
804
|
|
|
805 /* Check that the new number of wait states is taken into account to access the Flash
|
|
|
806 memory by reading the FLASH_ACR register */
|
|
|
807 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
|
808 {
|
|
|
809 return HAL_ERROR;
|
|
|
810 }
|
|
|
811 }
|
|
|
812
|
|
|
813 /*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
|
814 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
|
815 {
|
|
|
816 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
|
817 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
|
818 }
|
|
|
819
|
|
|
820 /*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
|
821 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
|
822 {
|
|
|
823 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
|
824 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
|
825 }
|
|
|
826
|
|
|
827 /* Configure the source of time base considering new system clocks settings*/
|
|
|
828 HAL_InitTick (TICK_INT_PRIORITY);
|
|
|
829
|
|
|
830 return HAL_OK;
|
|
|
831 }
|
|
|
832
|
|
|
833 /**
|
|
|
834 * @}
|
|
|
835 */
|
|
|
836
|
|
|
837 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
|
|
838 * @brief RCC clocks control functions
|
|
|
839 *
|
|
|
840 @verbatim
|
|
|
841 ===============================================================================
|
|
|
842 ##### Peripheral Control functions #####
|
|
|
843 ===============================================================================
|
|
|
844 [..]
|
|
|
845 This subsection provides a set of functions allowing to control the RCC Clocks
|
|
|
846 frequencies.
|
|
|
847
|
|
|
848 @endverbatim
|
|
|
849 * @{
|
|
|
850 */
|
|
|
851
|
|
|
852 /**
|
|
|
853 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
|
|
|
854 * @note PA8/PC9 should be configured in alternate function mode.
|
|
|
855 * @param RCC_MCOx: specifies the output direction for the clock source.
|
|
|
856 * This parameter can be one of the following values:
|
|
|
857 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
|
|
|
858 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
|
|
|
859 * @param RCC_MCOSource: specifies the clock source to output.
|
|
|
860 * This parameter can be one of the following values:
|
|
|
861 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
|
|
|
862 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
|
|
|
863 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
|
|
|
864 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
|
|
|
865 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
|
|
|
866 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
|
|
|
867 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
|
|
|
868 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
|
|
|
869 * @param RCC_MCODiv: specifies the MCOx prescaler.
|
|
|
870 * This parameter can be one of the following values:
|
|
|
871 * @arg RCC_MCODIV_1: no division applied to MCOx clock
|
|
|
872 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
|
|
|
873 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
|
|
|
874 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
|
|
|
875 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
|
|
|
876 * @retval None
|
|
|
877 */
|
|
|
878 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
|
|
879 {
|
|
|
880 GPIO_InitTypeDef GPIO_InitStruct;
|
|
|
881 /* Check the parameters */
|
|
|
882 assert_param(IS_RCC_MCO(RCC_MCOx));
|
|
|
883 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
|
|
884 /* RCC_MCO1 */
|
|
|
885 if(RCC_MCOx == RCC_MCO1)
|
|
|
886 {
|
|
|
887 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
|
|
888
|
|
|
889 /* MCO1 Clock Enable */
|
|
|
890 __MCO1_CLK_ENABLE();
|
|
|
891
|
|
|
892 /* Configure the MCO1 pin in alternate function mode */
|
|
|
893 GPIO_InitStruct.Pin = MCO1_PIN;
|
|
|
894 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
895 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
|
|
896 GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
897 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
|
|
898 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
|
|
|
899
|
|
|
900 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
|
|
|
901 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
|
|
|
902 }
|
|
|
903 else
|
|
|
904 {
|
|
|
905 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
|
|
|
906
|
|
|
907 /* MCO2 Clock Enable */
|
|
|
908 __MCO2_CLK_ENABLE();
|
|
|
909
|
|
|
910 /* Configure the MCO2 pin in alternate function mode */
|
|
|
911 GPIO_InitStruct.Pin = MCO2_PIN;
|
|
|
912 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
|
913 GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
|
|
|
914 GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
|
915 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
|
|
|
916 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
|
|
|
917
|
|
|
918 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
|
|
|
919 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
|
|
|
920 }
|
|
|
921 }
|
|
|
922
|
|
|
923 /**
|
|
|
924 * @brief Enables the Clock Security System.
|
|
|
925 * @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
|
926 * is automatically disabled and an interrupt is generated to inform the
|
|
|
927 * software about the failure (Clock Security System Interrupt, CSSI),
|
|
|
928 * allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
|
929 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
|
|
|
930 * @retval None
|
|
|
931 */
|
|
|
932 void HAL_RCC_EnableCSS(void)
|
|
|
933 {
|
|
|
934 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
|
|
|
935 }
|
|
|
936
|
|
|
937 /**
|
|
|
938 * @brief Disables the Clock Security System.
|
|
|
939 * @retval None
|
|
|
940 */
|
|
|
941 void HAL_RCC_DisableCSS(void)
|
|
|
942 {
|
|
|
943 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
|
|
|
944 }
|
|
|
945
|
|
|
946 /**
|
|
|
947 * @brief Returns the SYSCLK frequency
|
|
|
948 *
|
|
|
949 * @note The system frequency computed by this function is not the real
|
|
|
950 * frequency in the chip. It is calculated based on the predefined
|
|
|
951 * constant and the selected clock source:
|
|
|
952 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
|
953 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
|
|
|
954 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
|
|
|
955 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
|
|
956 * @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
|
|
957 * 16 MHz) but the real value may vary depending on the variations
|
|
|
958 * in voltage and temperature.
|
|
|
959 * @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
|
|
|
960 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
|
961 * frequency of the crystal used. Otherwise, this function may
|
|
|
962 * have wrong result.
|
|
|
963 *
|
|
|
964 * @note The result of this function could be not correct when using fractional
|
|
|
965 * value for HSE crystal.
|
|
|
966 *
|
|
|
967 * @note This function can be used by the user application to compute the
|
|
|
968 * baudrate for the communication peripherals or configure other parameters.
|
|
|
969 *
|
|
|
970 * @note Each time SYSCLK changes, this function must be called to update the
|
|
|
971 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
972 *
|
|
|
973 *
|
|
|
974 * @retval SYSCLK frequency
|
|
|
975 */
|
|
|
976 uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
|
977 {
|
|
|
978 uint32_t pllm = 0, pllvco = 0, pllp = 0;
|
|
|
979 uint32_t sysclockfreq = 0;
|
|
|
980
|
|
|
981 /* Get SYSCLK source -------------------------------------------------------*/
|
|
|
982 switch (RCC->CFGR & RCC_CFGR_SWS)
|
|
|
983 {
|
|
|
984 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
|
|
985 {
|
|
|
986 sysclockfreq = HSI_VALUE;
|
|
|
987 break;
|
|
|
988 }
|
|
|
989 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
|
|
990 {
|
|
|
991 sysclockfreq = HSE_VALUE;
|
|
|
992 break;
|
|
|
993 }
|
|
|
994 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
|
|
|
995 {
|
|
|
996 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
|
|
|
997 SYSCLK = PLL_VCO / PLLP */
|
|
|
998 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
|
|
999 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
|
|
1000 {
|
|
|
1001 /* HSE used as PLL clock source */
|
|
|
1002 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
|
|
1003 }
|
|
|
1004 else
|
|
|
1005 {
|
|
|
1006 /* HSI used as PLL clock source */
|
|
|
1007 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
|
|
|
1008 }
|
|
|
1009 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
|
|
|
1010
|
|
|
1011 sysclockfreq = pllvco/pllp;
|
|
|
1012 break;
|
|
|
1013 }
|
|
|
1014 default:
|
|
|
1015 {
|
|
|
1016 sysclockfreq = HSI_VALUE;
|
|
|
1017 break;
|
|
|
1018 }
|
|
|
1019 }
|
|
|
1020 return sysclockfreq;
|
|
|
1021 }
|
|
|
1022
|
|
|
1023 /**
|
|
|
1024 * @brief Returns the HCLK frequency
|
|
|
1025 * @note Each time HCLK changes, this function must be called to update the
|
|
|
1026 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
1027 *
|
|
|
1028 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
|
1029 * and updated within this function
|
|
|
1030 * @retval HCLK frequency
|
|
|
1031 */
|
|
|
1032 uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
|
1033 {
|
|
|
1034 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
|
|
|
1035 return SystemCoreClock;
|
|
|
1036 }
|
|
|
1037
|
|
|
1038 /**
|
|
|
1039 * @brief Returns the PCLK1 frequency
|
|
|
1040 * @note Each time PCLK1 changes, this function must be called to update the
|
|
|
1041 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
1042 * @retval PCLK1 frequency
|
|
|
1043 */
|
|
|
1044 uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
|
1045 {
|
|
|
1046 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
|
1047 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
|
|
|
1048 }
|
|
|
1049
|
|
|
1050 /**
|
|
|
1051 * @brief Returns the PCLK2 frequency
|
|
|
1052 * @note Each time PCLK2 changes, this function must be called to update the
|
|
|
1053 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
|
1054 * @retval PCLK2 frequency
|
|
|
1055 */
|
|
|
1056 uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
|
1057 {
|
|
|
1058 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
|
1059 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
|
|
|
1060 }
|
|
|
1061
|
|
|
1062 /**
|
|
|
1063 * @brief Configures the RCC_OscInitStruct according to the internal
|
|
|
1064 * RCC configuration registers.
|
|
|
1065 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
|
|
|
1066 * will be configured.
|
|
|
1067 * @retval None
|
|
|
1068 */
|
|
|
1069 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
|
1070 {
|
|
|
1071 /* Set all possible values for the Oscillator type parameter ---------------*/
|
|
|
1072 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
|
|
1073
|
|
|
1074 /* Get the HSE configuration -----------------------------------------------*/
|
|
|
1075 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
|
|
1076 {
|
|
|
1077 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
|
|
1078 }
|
|
|
1079 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
|
|
|
1080 {
|
|
|
1081 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
|
|
1082 }
|
|
|
1083 else
|
|
|
1084 {
|
|
|
1085 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
|
|
1086 }
|
|
|
1087
|
|
|
1088 /* Get the HSI configuration -----------------------------------------------*/
|
|
|
1089 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
|
|
|
1090 {
|
|
|
1091 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
|
|
1092 }
|
|
|
1093 else
|
|
|
1094 {
|
|
|
1095 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
|
|
1096 }
|
|
|
1097
|
|
|
1098 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
|
|
|
1099
|
|
|
1100 /* Get the LSE configuration -----------------------------------------------*/
|
|
|
1101 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
|
|
1102 {
|
|
|
1103 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
|
|
1104 }
|
|
|
1105 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
|
|
1106 {
|
|
|
1107 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
|
|
1108 }
|
|
|
1109 else
|
|
|
1110 {
|
|
|
1111 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
|
|
1112 }
|
|
|
1113
|
|
|
1114 /* Get the LSI configuration -----------------------------------------------*/
|
|
|
1115 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
|
1116 {
|
|
|
1117 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
|
|
1118 }
|
|
|
1119 else
|
|
|
1120 {
|
|
|
1121 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
|
|
1122 }
|
|
|
1123
|
|
|
1124 /* Get the PLL configuration -----------------------------------------------*/
|
|
|
1125 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
|
|
|
1126 {
|
|
|
1127 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
|
|
1128 }
|
|
|
1129 else
|
|
|
1130 {
|
|
|
1131 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
|
|
1132 }
|
|
|
1133 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
|
|
1134 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
|
|
|
1135 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
|
|
|
1136 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
|
|
|
1137 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
|
|
|
1138 }
|
|
|
1139
|
|
|
1140 /**
|
|
|
1141 * @brief Configures the RCC_ClkInitStruct according to the internal
|
|
|
1142 * RCC configuration registers.
|
|
|
1143 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
|
|
|
1144 * will be configured.
|
|
|
1145 * @param pFLatency: Pointer on the Flash Latency.
|
|
|
1146 * @retval None
|
|
|
1147 */
|
|
|
1148 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
|
1149 {
|
|
|
1150 /* Set all possible values for the Clock type parameter --------------------*/
|
|
|
1151 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
|
1152
|
|
|
1153 /* Get the SYSCLK configuration --------------------------------------------*/
|
|
|
1154 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
|
1155
|
|
|
1156 /* Get the HCLK configuration ----------------------------------------------*/
|
|
|
1157 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
|
1158
|
|
|
1159 /* Get the APB1 configuration ----------------------------------------------*/
|
|
|
1160 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
|
1161
|
|
|
1162 /* Get the APB2 configuration ----------------------------------------------*/
|
|
|
1163 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
|
|
|
1164
|
|
|
1165 /* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
|
1166 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
|
1167 }
|
|
|
1168
|
|
|
1169 /**
|
|
|
1170 * @brief This function handles the RCC CSS interrupt request.
|
|
|
1171 * @note This API should be called under the NMI_Handler().
|
|
|
1172 * @retval None
|
|
|
1173 */
|
|
|
1174 void HAL_RCC_NMI_IRQHandler(void)
|
|
|
1175 {
|
|
|
1176 /* Check RCC CSSF flag */
|
|
|
1177 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
|
|
|
1178 {
|
|
|
1179 /* RCC Clock Security System interrupt user callback */
|
|
|
1180 HAL_RCC_CSSCallback();
|
|
|
1181
|
|
|
1182 /* Clear RCC CSS pending bit */
|
|
|
1183 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
|
|
|
1184 }
|
|
|
1185 }
|
|
|
1186
|
|
|
1187 /**
|
|
|
1188 * @brief RCC Clock Security System interrupt callback
|
|
|
1189 * @retval None
|
|
|
1190 */
|
|
|
1191 __weak void HAL_RCC_CSSCallback(void)
|
|
|
1192 {
|
|
|
1193 /* NOTE : This function Should not be modified, when the callback is needed,
|
|
|
1194 the HAL_RCC_CSSCallback could be implemented in the user file
|
|
|
1195 */
|
|
|
1196 }
|
|
|
1197
|
|
|
1198 /**
|
|
|
1199 * @}
|
|
|
1200 */
|
|
|
1201
|
|
|
1202 /**
|
|
|
1203 * @}
|
|
|
1204 */
|
|
|
1205
|
|
|
1206 #endif /* HAL_RCC_MODULE_ENABLED */
|
|
|
1207 /**
|
|
|
1208 * @}
|
|
|
1209 */
|
|
|
1210
|
|
|
1211 /**
|
|
|
1212 * @}
|
|
|
1213 */
|
|
|
1214
|
|
|
1215 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
