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1 /**************************************************************************//**
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2 * @file core_cmInstr.h
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3 * @brief CMSIS Cortex-M Core Instruction Access Header File
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4 * @version V2.10
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5 * @date 19. July 2011
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6 *
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7 * @note
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8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
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9 *
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10 * @par
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11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
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12 * processor based microcontrollers. This file can be freely distributed
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13 * within development tools that are supporting such ARM based processors.
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14 *
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15 * @par
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16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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21 *
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22 ******************************************************************************/
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23
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24 #ifndef __CORE_CMINSTR_H
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25 #define __CORE_CMINSTR_H
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26
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27
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28 /* ########################## Core Instruction Access ######################### */
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29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
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30 Access to dedicated instructions
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31 @{
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32 */
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33
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34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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35 /* ARM armcc specific functions */
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36
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37 #if (__ARMCC_VERSION < 400677)
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38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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39 #endif
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40
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41
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42 /** \brief No Operation
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43
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44 No Operation does nothing. This instruction can be used for code alignment purposes.
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45 */
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46 #define __NOP __nop
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47
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48
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49 /** \brief Wait For Interrupt
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50
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51 Wait For Interrupt is a hint instruction that suspends execution
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52 until one of a number of events occurs.
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53 */
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54 #define __WFI __wfi
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55
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56
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57 /** \brief Wait For Event
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58
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59 Wait For Event is a hint instruction that permits the processor to enter
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60 a low-power state until one of a number of events occurs.
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61 */
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62 #define __WFE __wfe
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63
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64
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65 /** \brief Send Event
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66
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67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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68 */
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69 #define __SEV __sev
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70
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71
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72 /** \brief Instruction Synchronization Barrier
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73
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74 Instruction Synchronization Barrier flushes the pipeline in the processor,
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75 so that all instructions following the ISB are fetched from cache or
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76 memory, after the instruction has been completed.
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77 */
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78 #define __ISB() __isb(0xF)
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79
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80
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81 /** \brief Data Synchronization Barrier
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82
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83 This function acts as a special kind of Data Memory Barrier.
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84 It completes when all explicit memory accesses before this instruction complete.
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85 */
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86 #define __DSB() __dsb(0xF)
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87
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88
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89 /** \brief Data Memory Barrier
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90
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91 This function ensures the apparent order of the explicit memory operations before
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92 and after the instruction, without ensuring their completion.
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93 */
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94 #define __DMB() __dmb(0xF)
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95
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96
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97 /** \brief Reverse byte order (32 bit)
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98
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99 This function reverses the byte order in integer value.
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100
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101 \param [in] value Value to reverse
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102 \return Reversed value
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103 */
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104 #define __REV __rev
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105
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106
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107 /** \brief Reverse byte order (16 bit)
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108
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109 This function reverses the byte order in two unsigned short values.
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110
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111 \param [in] value Value to reverse
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112 \return Reversed value
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113 */
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114 static __INLINE __ASM uint32_t __REV16(uint32_t value)
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115 {
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116 rev16 r0, r0
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117 bx lr
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118 }
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119
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120
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121 /** \brief Reverse byte order in signed short value
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122
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123 This function reverses the byte order in a signed short value with sign extension to integer.
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124
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125 \param [in] value Value to reverse
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126 \return Reversed value
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127 */
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128 static __INLINE __ASM int32_t __REVSH(int32_t value)
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129 {
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130 revsh r0, r0
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131 bx lr
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132 }
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133
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134
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135 #if (__CORTEX_M >= 0x03)
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136
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137 /** \brief Reverse bit order of value
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138
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139 This function reverses the bit order of the given value.
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140
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141 \param [in] value Value to reverse
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142 \return Reversed value
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143 */
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144 #define __RBIT __rbit
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145
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146
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147 /** \brief LDR Exclusive (8 bit)
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148
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149 This function performs a exclusive LDR command for 8 bit value.
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150
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151 \param [in] ptr Pointer to data
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152 \return value of type uint8_t at (*ptr)
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153 */
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154 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
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155
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156
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157 /** \brief LDR Exclusive (16 bit)
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158
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159 This function performs a exclusive LDR command for 16 bit values.
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160
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161 \param [in] ptr Pointer to data
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162 \return value of type uint16_t at (*ptr)
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163 */
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164 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
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165
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166
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167 /** \brief LDR Exclusive (32 bit)
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168
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169 This function performs a exclusive LDR command for 32 bit values.
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170
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171 \param [in] ptr Pointer to data
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172 \return value of type uint32_t at (*ptr)
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173 */
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174 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
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175
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176
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177 /** \brief STR Exclusive (8 bit)
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178
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179 This function performs a exclusive STR command for 8 bit values.
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180
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181 \param [in] value Value to store
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182 \param [in] ptr Pointer to location
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183 \return 0 Function succeeded
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184 \return 1 Function failed
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185 */
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186 #define __STREXB(value, ptr) __strex(value, ptr)
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187
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188
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189 /** \brief STR Exclusive (16 bit)
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190
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191 This function performs a exclusive STR command for 16 bit values.
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192
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193 \param [in] value Value to store
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194 \param [in] ptr Pointer to location
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195 \return 0 Function succeeded
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196 \return 1 Function failed
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197 */
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198 #define __STREXH(value, ptr) __strex(value, ptr)
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199
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200
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201 /** \brief STR Exclusive (32 bit)
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202
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203 This function performs a exclusive STR command for 32 bit values.
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204
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205 \param [in] value Value to store
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206 \param [in] ptr Pointer to location
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207 \return 0 Function succeeded
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208 \return 1 Function failed
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209 */
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210 #define __STREXW(value, ptr) __strex(value, ptr)
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211
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212
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213 /** \brief Remove the exclusive lock
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214
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215 This function removes the exclusive lock which is created by LDREX.
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216
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217 */
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218 #define __CLREX __clrex
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219
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220
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221 /** \brief Signed Saturate
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222
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223 This function saturates a signed value.
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224
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225 \param [in] value Value to be saturated
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226 \param [in] sat Bit position to saturate to (1..32)
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227 \return Saturated value
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228 */
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229 #define __SSAT __ssat
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230
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231
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232 /** \brief Unsigned Saturate
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233
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234 This function saturates an unsigned value.
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235
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236 \param [in] value Value to be saturated
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237 \param [in] sat Bit position to saturate to (0..31)
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238 \return Saturated value
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239 */
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240 #define __USAT __usat
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241
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242
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243 /** \brief Count leading zeros
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244
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245 This function counts the number of leading zeros of a data value.
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246
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247 \param [in] value Value to count the leading zeros
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248 \return number of leading zeros in value
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249 */
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250 #define __CLZ __clz
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251
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252 #endif /* (__CORTEX_M >= 0x03) */
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253
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254
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255
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256 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
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257 /* IAR iccarm specific functions */
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258
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259 #include <cmsis_iar.h>
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260
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261
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262 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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263 /* GNU gcc specific functions */
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264
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265 /** \brief No Operation
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266
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267 No Operation does nothing. This instruction can be used for code alignment purposes.
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268 */
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269 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
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270 {
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271 __ASM volatile ("nop");
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272 }
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273
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274
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275 /** \brief Wait For Interrupt
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276
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277 Wait For Interrupt is a hint instruction that suspends execution
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278 until one of a number of events occurs.
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279 */
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280 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
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281 {
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282 __ASM volatile ("wfi");
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283 }
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284
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285
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286 /** \brief Wait For Event
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287
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288 Wait For Event is a hint instruction that permits the processor to enter
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289 a low-power state until one of a number of events occurs.
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290 */
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291 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
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292 {
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293 __ASM volatile ("wfe");
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294 }
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295
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296
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297 /** \brief Send Event
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298
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299 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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300 */
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301 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
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302 {
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303 __ASM volatile ("sev");
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304 }
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305
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306
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307 /** \brief Instruction Synchronization Barrier
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308
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309 Instruction Synchronization Barrier flushes the pipeline in the processor,
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310 so that all instructions following the ISB are fetched from cache or
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311 memory, after the instruction has been completed.
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312 */
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313 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
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314 {
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315 __ASM volatile ("isb");
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316 }
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317
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318
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319 /** \brief Data Synchronization Barrier
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320
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321 This function acts as a special kind of Data Memory Barrier.
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322 It completes when all explicit memory accesses before this instruction complete.
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323 */
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324 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
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325 {
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326 __ASM volatile ("dsb");
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327 }
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328
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329
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330 /** \brief Data Memory Barrier
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331
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332 This function ensures the apparent order of the explicit memory operations before
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333 and after the instruction, without ensuring their completion.
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334 */
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335 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
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336 {
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337 __ASM volatile ("dmb");
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338 }
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339
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340
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341 /** \brief Reverse byte order (32 bit)
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342
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343 This function reverses the byte order in integer value.
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344
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345 \param [in] value Value to reverse
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346 \return Reversed value
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347 */
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348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
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349 {
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350 uint32_t result;
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351
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352 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
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353 return(result);
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354 }
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355
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356
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357 /** \brief Reverse byte order (16 bit)
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358
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359 This function reverses the byte order in two unsigned short values.
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360
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361 \param [in] value Value to reverse
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362 \return Reversed value
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363 */
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364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
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365 {
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366 uint32_t result;
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367
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368 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
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369 return(result);
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370 }
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371
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372
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373 /** \brief Reverse byte order in signed short value
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374
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375 This function reverses the byte order in a signed short value with sign extension to integer.
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376
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377 \param [in] value Value to reverse
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378 \return Reversed value
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379 */
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380 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
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381 {
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382 uint32_t result;
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383
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384 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
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385 return(result);
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386 }
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387
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388
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389 #if (__CORTEX_M >= 0x03)
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390
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391 /** \brief Reverse bit order of value
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392
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393 This function reverses the bit order of the given value.
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394
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395 \param [in] value Value to reverse
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396 \return Reversed value
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397 */
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398 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
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399 {
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400 uint32_t result;
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401
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402 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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403 return(result);
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404 }
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405
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406
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407 /** \brief LDR Exclusive (8 bit)
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408
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409 This function performs a exclusive LDR command for 8 bit value.
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410
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411 \param [in] ptr Pointer to data
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412 \return value of type uint8_t at (*ptr)
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413 */
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414 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
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415 {
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416 uint8_t result;
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417
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418 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
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419 return(result);
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420 }
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421
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422
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423 /** \brief LDR Exclusive (16 bit)
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424
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425 This function performs a exclusive LDR command for 16 bit values.
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426
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427 \param [in] ptr Pointer to data
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428 \return value of type uint16_t at (*ptr)
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429 */
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430 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
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431 {
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432 uint16_t result;
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433
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434 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
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435 return(result);
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436 }
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437
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438
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439 /** \brief LDR Exclusive (32 bit)
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440
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441 This function performs a exclusive LDR command for 32 bit values.
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442
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443 \param [in] ptr Pointer to data
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444 \return value of type uint32_t at (*ptr)
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445 */
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446 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
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447 {
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448 uint32_t result;
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449
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450 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
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451 return(result);
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452 }
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453
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454
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455 /** \brief STR Exclusive (8 bit)
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456
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457 This function performs a exclusive STR command for 8 bit values.
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458
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459 \param [in] value Value to store
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460 \param [in] ptr Pointer to location
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461 \return 0 Function succeeded
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462 \return 1 Function failed
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463 */
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464 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
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465 {
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466 uint32_t result;
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467
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468 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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469 return(result);
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470 }
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471
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472
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473 /** \brief STR Exclusive (16 bit)
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474
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475 This function performs a exclusive STR command for 16 bit values.
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476
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477 \param [in] value Value to store
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478 \param [in] ptr Pointer to location
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479 \return 0 Function succeeded
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480 \return 1 Function failed
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481 */
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482 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
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483 {
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484 uint32_t result;
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485
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486 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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487 return(result);
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488 }
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489
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490
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491 /** \brief STR Exclusive (32 bit)
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492
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493 This function performs a exclusive STR command for 32 bit values.
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494
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495 \param [in] value Value to store
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496 \param [in] ptr Pointer to location
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497 \return 0 Function succeeded
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498 \return 1 Function failed
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499 */
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500 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
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501 {
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502 uint32_t result;
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503
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504 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
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505 return(result);
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506 }
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507
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508
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509 /** \brief Remove the exclusive lock
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510
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511 This function removes the exclusive lock which is created by LDREX.
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512
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513 */
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514 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
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515 {
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516 __ASM volatile ("clrex");
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517 }
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518
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519
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520 /** \brief Signed Saturate
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521
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522 This function saturates a signed value.
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523
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524 \param [in] value Value to be saturated
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525 \param [in] sat Bit position to saturate to (1..32)
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526 \return Saturated value
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527 */
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528 #define __SSAT(ARG1,ARG2) \
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529 ({ \
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530 uint32_t __RES, __ARG1 = (ARG1); \
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531 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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532 __RES; \
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533 })
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534
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535
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536 /** \brief Unsigned Saturate
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537
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538 This function saturates an unsigned value.
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539
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540 \param [in] value Value to be saturated
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541 \param [in] sat Bit position to saturate to (0..31)
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542 \return Saturated value
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543 */
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544 #define __USAT(ARG1,ARG2) \
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545 ({ \
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546 uint32_t __RES, __ARG1 = (ARG1); \
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547 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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548 __RES; \
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549 })
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550
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551
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552 /** \brief Count leading zeros
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553
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554 This function counts the number of leading zeros of a data value.
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555
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556 \param [in] value Value to count the leading zeros
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557 \return number of leading zeros in value
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558 */
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559 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
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560 {
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561 uint8_t result;
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562
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563 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
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564 return(result);
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565 }
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566
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567 #endif /* (__CORTEX_M >= 0x03) */
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568
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569
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570
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571
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572 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
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573 /* TASKING carm specific functions */
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574
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575 /*
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576 * The CMSIS functions have been implemented as intrinsics in the compiler.
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577 * Please use "carm -?i" to get an up to date list of all intrinsics,
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578 * Including the CMSIS ones.
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579 */
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580
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581 #endif
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582
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583 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
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584
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585 #endif /* __CORE_CMINSTR_H */
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