changeset 463:86fc79735d3b

Experimental 32MHz mode
author heinrichsweikamp
date Tue, 27 Sep 2011 22:23:12 +0200 (2011-09-27)
parents 32e1174fb89e
children 915e0d38edec
files code_part1/OSTC_code_asm_part1/definitions.asm code_part1/OSTC_code_asm_part1/eeprom_rs232.asm code_part1/OSTC_code_asm_part1/start.asm
diffstat 3 files changed, 22 insertions(+), 8 deletions(-) [+]
line wrap: on
line diff
--- a/code_part1/OSTC_code_asm_part1/definitions.asm	Sun Sep 25 10:30:53 2011 +0200
+++ b/code_part1/OSTC_code_asm_part1/definitions.asm	Tue Sep 27 22:23:12 2011 +0200
@@ -41,6 +41,19 @@
 #DEFINE	logbook_profile_version	0x21        ; Do not touch!
 #DEFINE	T0CON_debounce	b'00000000'         ; Timer0 Switch Debounce
 
+
+; CPU Speed Settings
+; Standard 16MHz mode
+;	#DEFINE	SPBRG_VALUE 	d'34'
+;  	#DEFINE	OSCCON_VALUE  	b'01101100'		; 4MHz (x4 PLL)
+;	#DEFINE	SSPADD_VALUE	d'8'			; 400kHz I2C clock @ 16MHz Fcy
+;	#DEFINE	T0CON_VALUE		b'00011111'		; Timer0
+; Experimental 32MHz mode
+	#DEFINE	SPBRG_VALUE 	d'68'
+  	#DEFINE	OSCCON_VALUE  	b'01111100'		; 8MHz (x4 PLL)
+	#DEFINE	SSPADD_VALUE	d'16'			; 400kHz I2C clock @ 32MHz Fcy
+	#DEFINE	T0CON_VALUE 	b'00010000'		; Timer0
+
 #DEFINE		FT_SMALL		.0
 #DEFINE		FT_MEDIUM		.1
 #DEFINE		FT_LARGE		.2
@@ -97,8 +110,8 @@
 
 ;=============================================================================
 
-;#include "../OSTC_code_c_part2/shared_definitions.h"
-#include "shared_definitions.h"
+#include "../OSTC_code_c_part2/shared_definitions.h"
+;#include "shared_definitions.h"
 
 ;=============================================================================
 ; Reserve space for C-code data space. Eg.when calling log.
--- a/code_part1/OSTC_code_asm_part1/eeprom_rs232.asm	Sun Sep 25 10:30:53 2011 +0200
+++ b/code_part1/OSTC_code_asm_part1/eeprom_rs232.asm	Tue Sep 27 22:23:12 2011 +0200
@@ -126,7 +126,7 @@
 	movlw	b'00001000'
 	movwf	BAUDCON
 	clrf	SPBRGH
-	movlw	d'34'				; Take care of the baud rate when changing Fosc!
+	movlw	SPBRG_VALUE			; Take care of the baud rate when changing Fosc!
 	movwf	SPBRG
 	clrf	RCREG
 	clrf	PIR1
--- a/code_part1/OSTC_code_asm_part1/start.asm	Sun Sep 25 10:30:53 2011 +0200
+++ b/code_part1/OSTC_code_asm_part1/start.asm	Tue Sep 27 22:23:12 2011 +0200
@@ -395,9 +395,8 @@
 	bra		start3					; continue with normal start
 
 init:						
-	movlw	b'01101100'		; 4MHz (x4 PLL)
+	movlw	OSCCON_VALUE
 	movwf	OSCCON
-
 	movlw	b'00010001'		; I/O Ports
 	movwf	TRISA
 	clrf	PORTA
@@ -417,7 +416,7 @@
 	movlw	b'01000000'		; Bit6: PPL enable
 	movwf	OSCTUNE
 
-	movlw	b'00011111'		; Timer0
+	movlw	T0CON_VALUE		; Timer0
 	movwf	T0CON
 
 	movlw	b'00000111'		; Timer1
@@ -449,7 +448,8 @@
 	movwf	SSPCON1
 	movlw	b'00000000'
 	movwf	SSPCON2
-	movlw	d'8'			; 400kHz I2C clock @ 16MHz Fcy
+
+	movlw	SSPADD_VALUE	; I²C Speed
 	movwf	SSPADD
 
 	clrf	CCP1CON			; PWM Module off
@@ -468,7 +468,8 @@
 	movlw	b'00001000'
 	movwf	BAUDCON
 	clrf	SPBRGH
-	movlw	d'34'
+
+	movlw	SPBRG_VALUE
 	movwf	SPBRG
 	clrf	RCREG
 	clrf	PIR1