annotate code_part1/OSTC_code_asm_part1/sync_clock.asm @ 670:92e1690ecc84

2.57beta release
author heinrichsweikamp
date Tue, 04 Dec 2012 16:41:38 +0100
parents 73014f788032
children c50296c3059e
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
21
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
1
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
2 ; OSTC - diving computer code
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
3 ; Copyright (C) 2008 HeinrichsWeikamp GbR
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
4
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
5 ; This program is free software: you can redistribute it and/or modify
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
6 ; it under the terms of the GNU General Public License as published by
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
7 ; the Free Software Foundation, either version 3 of the License, or
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
8 ; (at your option) any later version.
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
9
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
10 ; This program is distributed in the hope that it will be useful,
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
11 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
12 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
13 ; GNU General Public License for more details.
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
14
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
15 ; You should have received a copy of the GNU General Public License
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
16 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
17
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
18
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
19 ; Syncs RTC with PC
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
20 ; written by: Matthias Heinrichs, info@heinrichsweikamp.com
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
21 ; written: 13/10/07
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
22 ; last updated: 08/08/31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
23 ; known bugs:
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
24 ; ToDo:
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
25
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
26 ; routine echoes the "b" command as ready signal
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
27 ; PC has to send 6 bytes
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
28 ; Byte1: hours
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
29 ; Byte2: minutes
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
30 ; Byte3: seconds
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
31 ; Byte4: month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
32 ; Byte5: day
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
33 ; Byte6: year
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
34 ; All bytes will be checked for plausibility and the clock will be set
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
35 ; after a timeout of about 20ms, the routine ends
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
36
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
37 sync_clock:
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
38 bcf uart_settime ; clear flag
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
39 bcf PIE1,RCIE ; no interrupt for UART
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
40 bsf LED_blue ; LEDusb ON
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
41 bcf PIR1,RCIF ; clear flag
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
42
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
43 movlw "b" ; send echo
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
44 movwf TXREG
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
45 call rs232_wait_tx ; wait for UART
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
46
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
47 call rs232_get_byte ; hours
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
48 movff RCREG, hours
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
49
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
50 movlw d'24'
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
51 cpfslt hours
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
52 clrf hours
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
53
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
54 call rs232_get_byte ; minutes
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
55 movff RCREG, mins
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
56
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
57 movlw d'60'
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
58 cpfslt mins
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
59 clrf mins
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
60
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
61 call rs232_get_byte ; seconds
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
62 movff RCREG, secs
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
63
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
64 movlw d'60'
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
65 cpfslt secs
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
66 clrf secs
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
67
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
68 call rs232_get_byte ; month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
69 movff RCREG, month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
70
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
71 movlw d'12'
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
72 cpfsgt month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
73 bra sync_clock0
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
74 movwf month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
75
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
76 sync_clock0:
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
77 call rs232_get_byte ; day
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
78 movff RCREG, day
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
79
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
80 movff month,lo ; new month
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
81 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
82 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
83 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
84 movlw .28
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
85 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
86 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
87 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
88 movlw .30
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
89 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
90 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
91 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
92 movlw .30
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
93 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
94 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
95 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
96 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
97 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
98 movlw .30
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
99 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
100 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
101 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
102 movlw .30
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
103 dcfsnz lo,F
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
104 movlw .31
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
105 cpfsgt day ; day ok?
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
106 bra sync_clock1 ; OK
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
107 movlw .1 ; not OK, set to 1st
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
108 movwf day
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
109
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
110 sync_clock1:
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
111 call rs232_get_byte ; year
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
112 movff RCREG, year
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
113
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
114 movlw d'100'
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
115 cpfslt year
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
116 clrf year
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
117
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
118 bcf LED_blue ; LEDusb OFF
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
119 bcf PIR1,RCIF ; clear flag
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
120 bsf oneminupdate ; set flag, so new time and date will be updated in surfacemode at once
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
121 bsf PIE1,RCIE ; enable interrupt for UART
73014f788032 1.60 stable rc1
heinrichsweikamp
parents: 0
diff changeset
122 goto surfloop_loop ; return to surface loop