mk2: code_part1/OSTC_code_asm_part1/eeprom

annotate code_part1/OSTC_code_asm_part1/eeprom_rs232.asm @ 842:454ef5c2e6aa default tip

Bugfix: Auto-SP did not show >9m for some 2C hardware versions in German language firmware Make year settings until 2040 possible (This is likely the final release for this model)

author	heinrichsweikamp
date	Sat, 29 Nov 2025 14:11:07 +0100
parents	2a0e5d884fc3
children

rev	line source
815 2a0e5d884fc3 BUGFIX: Fix licence in German heinrichsweikamp parents: 807 diff changeset	1 ; OSTC Mk.2, 2N and 2C - diving computer code
807 c50296c3059e BUGFIX: Divetime had unwanted "." behind the minutes heinrichsweikamp parents: 720 diff changeset	2 ; Copyright (C) 2015 HeinrichsWeikamp GbR
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	3
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	4 ; This program is free software: you can redistribute it and/or modify
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	5 ; it under the terms of the GNU General Public License as published by
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	6 ; the Free Software Foundation, either version 3 of the License, or
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	7 ; (at your option) any later version.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	8
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	9 ; This program is distributed in the hope that it will be useful,
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	10 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	11 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	12 ; GNU General Public License for more details.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	13
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	14 ; You should have received a copy of the GNU General Public License
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	15 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	16
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	17
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	18 ; internal EEPROM and RS232 UART interface
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	19 ; written by: Matthias Heinrichs, info@heinrichsweikamp.com
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	20 ; written: 02/01/06
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	21 ; last updated: 090109
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	22 ; known bugs:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	23 ; ToDo:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	24
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	25 write_int_eeprom macro eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	26 movlw eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	27 call write_int_eeprom_1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	28 endm
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	29
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	30 write_int_eeprom_1:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	31 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	32 bra write_eeprom ; writes and "returns" after write
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	33
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	34 read_int_eeprom macro eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	35 movlw eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	36 call read_int_eeprom_1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	37 endm
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	38
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	39 read_int_eeprom_1:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	40 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	41 bra read_eeprom ; reads and "returns" after write
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	42
578 fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	43 internal_eeprom_access_b2: ; accesses internal EEPROM BANK 2 via the UART
fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	44 bcf internal_eeprom_write3 ; clear flag!
fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	45 movlw d'2'
703 39e02673db4c some cleanup heinrichsweikamp parents: 681 diff changeset	46 movwf EEADRH ;BANK2
578 fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	47 movlw "n"
fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	48 bra internal_eeprom_access1 ; Continue with common routines
fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	49
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	50 internal_eeprom_access_b1: ; accesses internal EEPROM BANK 1 via the UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	51 bcf internal_eeprom_write2 ; clear flag!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	52 movlw d'1'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	53 movwf EEADRH ;BANK1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	54 movlw "i"
578 fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	55 bra internal_eeprom_access1 ; Continue with common routines
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	56
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	57 internal_eeprom_access_b0: ; accesses internal EEPROM BANK 0 via the UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	58 bcf internal_eeprom_write ; clear flag!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	59 clrf EEADRH ; Bank0
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	60 movlw "d"
578 fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	61 ; bra internal_eeprom_access1 ; Continue with common routines
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	62 internal_eeprom_access1:
578 fbd5e2b75a63 adding access to CF64-CF95 heinrichsweikamp parents: 537 diff changeset	63 movwf TXREG ; Send command echo ("i", "d" or "n")
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	64 bsf no_sensor_int ; No Sensor Interrupt
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	65 movlw d'4'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	66 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	67 bcf PIE1,RCIE ; no interrupt for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	68 bcf PIR1,RCIF ; clear flag
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	69 bsf LED_blue ; LEDusb ON
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	70
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	71 internal_eeprom_access2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	72 rcall rs232_get_byte ; Get byte to write...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	73 movff RCREG,EEDATA ; copy to write register
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	74 bsf LED_red ; show activity
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	75
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	76 btfsc rs232_recieve_overflow ; overflow recieved?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	77 bra internal_eeprom_access3 ; Yes, abort!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	78
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	79 rcall write_eeprom ; No, write one byte
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	80 bcf LED_red
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	81 movff EEDATA,TXREG ; Send echo!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	82 rcall rs232_wait_tx ; Wait for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	83 incfsz EEADR,F ; Do until EEADR rolls to zero
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	84 bra internal_eeprom_access2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	85 internal_eeprom_access2a:
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	86 bcf LED_blue ; LEDusb OFF
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	87 bcf PIR1,RCIF ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	88 bsf PIE1,RCIE ; re-enable interrupt for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	89 clrf EEADRH ; Point to Bank0 again
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	90 bcf rs232_recieve_overflow ; Clear Flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	91 bcf no_sensor_int ; Renable Sensor Interrupt
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	92 goto restart
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	93
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	94 internal_eeprom_access3: ; Overflow! Abort writing
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	95 movlw 0xFF
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	96 movwf TXREG ; Error Byte
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	97 bra internal_eeprom_access2a ; Quit
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	98
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	99 read_eeprom: ; reads from internal eeprom
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	100 bcf EECON1,EEPGD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	101 bcf EECON1,CFGS
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	102 bsf EECON1,RD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	103 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	104
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	105 write_eeprom: ; writes into internal eeprom
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	106 bcf EECON1,EEPGD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	107 bcf EECON1,CFGS
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	108 bsf EECON1,WREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	109
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	110 bcf INTCON,GIE ; even the RTC will be delayed for the next 5 instructions...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	111 movlw 0x55
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	112 movwf EECON2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	113 movlw 0xAA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	114 movwf EECON2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	115 bsf EECON1,WR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	116 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	117
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	118 write_eep2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	119 btfsc EECON1,WR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	120 bra write_eep2 ; wait about 4ms...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	121 bcf EECON1,WREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	122 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	123
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	124 enable_rs232: ;IO Ports must be input in order to activate the module
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	125 bsf TRISC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	126 bsf TRISC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	127
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	128 movlw b'00100100' ; BRGH=1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	129 movwf TXSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	130 movlw b'10010000'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	131 movwf RCSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	132 movlw b'00001000'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	133 movwf BAUDCON
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	134 clrf SPBRGH
463 86fc79735d3b Experimental 32MHz mode heinrichsweikamp parents: 284 diff changeset	135 movlw SPBRG_VALUE ; Take care of the baud rate when changing Fosc!
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	136 movwf SPBRG
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	137 clrf RCREG
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	138 clrf PIR1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	139 bsf PIE1,RCIE ; enable interrupt for RS232
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	140 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	141
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	142 disable_rs232:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	143 clrf TXSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	144 clrf RCSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	145 bcf PIE1,RCIE ; disable interrupt for RS232
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	146 bcf TRISC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	147 bcf TRISC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	148 bcf PORTC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	149 bcf PORTC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	150 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	151
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	152 rs232_wait_tx:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	153 btfss RCSTA,SPEN ; Transmitter active?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	154 return ; No, return!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	155 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	156 btfss TXSTA,TRMT ; RS232 Busy?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	157 bra rs232_wait_tx ; yes, wait...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	158 return ; Done.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	159
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	160
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	161 rs232_get_byte:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	162 bcf PIR1,RCIF ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	163 bcf rs232_recieve_overflow ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	164 clrf uart1_temp
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	165 rs232_get_byte2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	166 clrf uart2_temp
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	167 rs232_get_byte3:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	168 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	169 return ; data received
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	170
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	171 nop ; Wait 1us * 255 * 255 = 65ms+x Timeout/Byte
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	172 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	173 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	174 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	175 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	176 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	177 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	178 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	179 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	180 return
529 e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	181 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	182 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	183 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	184 nop
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	185 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	186 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	187 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	188 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	189 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	190 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	191 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	192 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	193 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	194 nop
529 e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	195 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	196 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	197 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	198 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	199 btfsc PIR1,RCIF ; data arrived?
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	200 return
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	201 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	202 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	203 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	204 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	205 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	206 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	207 nop
e2acb601504c some cleanup heinrichsweikamp parents: 463 diff changeset	208 nop
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	209 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	210 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	211
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	212 decfsz uart2_temp,F
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	213 bra rs232_get_byte3
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	214 decfsz uart1_temp,F
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	215 bra rs232_get_byte2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	216 ; timeout occoured (about 20ms)
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	217 bcf RCSTA,CREN ; Clear receiver status
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	218 bsf RCSTA,CREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	219 bsf rs232_recieve_overflow ; set flag
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	220 return ; and return anyway
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	221
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	222 uart_115k_bootloader:
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	223 bcf PIE1,RCIE ; disable interrupt for RS232
681 6e456a6398e0 Hardware4 support heinrichsweikamp parents: 578 diff changeset	224 call DISP_ClearScreen ; Clear screen
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	225 movlw color_red
681 6e456a6398e0 Hardware4 support heinrichsweikamp parents: 578 diff changeset	226 call DISP_set_color ; Set to Red
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	227 DISPLAYTEXTH d'302' ; Bootloader
537 3091628b2742 BUGFIX: Spurious logbook read issue heinrichsweikamp parents: 529 diff changeset	228 bcf RCSTA,CREN ; Clear receiver status
3091628b2742 BUGFIX: Spurious logbook read issue heinrichsweikamp parents: 529 diff changeset	229 bsf RCSTA,CREN
3091628b2742 BUGFIX: Spurious logbook read issue heinrichsweikamp parents: 529 diff changeset	230 bcf PIR1,RCIF ; clear flag
3091628b2742 BUGFIX: Spurious logbook read issue heinrichsweikamp parents: 529 diff changeset	231 movlw d'200' ; one second
284 908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	232 movwf uart1_temp
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	233 uart_115k_bootloader0:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	234 btfsc PIR1,RCIF ; New byte in UART?
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	235 bra uart_115k_bootloader1 ; Yes, Check if 0xC1
537 3091628b2742 BUGFIX: Spurious logbook read issue heinrichsweikamp parents: 529 diff changeset	236 WAITMS d'5'
284 908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	237 decfsz uart1_temp,F
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	238 bra uart_115k_bootloader0
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	239 uart_115k_bootloader2:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	240 DISPLAYTEXTH d'304' ; Aborted!
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	241 movlw d'8' ; Two seconds
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	242 movwf uart1_temp
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	243 uart_115k_bootloader3:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	244 WAITMS d'250'
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	245 decfsz uart1_temp,F
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	246 bra uart_115k_bootloader3
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	247 goto restart
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	248
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	249 uart_115k_bootloader1:
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	250 movlw 0xC1
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	251 cpfseq RCREG ; 115200Baud Bootloader request?
720 4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	252 bra uart_115k_bootloader2 ; No, Abort
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	253
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	254 ; Vault date and time during update
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	255 ; EEPROM Bank1
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	256 ; Byte 5: =0xAA -> reload time and date in "restart:"
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	257 ; Byte 6-11: YYMMDDHHMMSS
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	258 movlw .1
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	259 movwf EEADRH
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	260 movff year,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	261 write_int_eeprom d'6'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	262 movff month,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	263 write_int_eeprom d'7'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	264 movff day,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	265 write_int_eeprom d'8'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	266 movff hours,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	267 write_int_eeprom d'9'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	268 movff mins,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	269 write_int_eeprom d'10'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	270 movff secs,EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	271 write_int_eeprom d'11'
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	272 movlw 0xAA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	273 movwf EEDATA
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	274 write_int_eeprom d'5' ; Set flag
4452837aff37 Vault date and time during update heinrichsweikamp parents: 703 diff changeset	275 clrf EEADRH
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	276 DISPLAYTEXTH d'303' ; Yes, "Please wait!"
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	277 clrf INTCON ; Interrupts disabled
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	278 bcf PIR1,RCIF ; clear flag
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	279 goto 0x17F56 ; Enter straight into bootloader. Good luck!

Mercurial > public > mk2

annotate code_part1/OSTC_code_asm_part1/eeprom_rs232.asm @ 842:454ef5c2e6aa default tip