annotate code_part1/OSTC_code_asm_part1/eeprom_rs232.asm @ 9:395230c28023

Added CF36: Divemask color
author heinrichsweikamp
date Tue, 09 Mar 2010 13:06:26 +0100
parents 96a35aeda5f2
children 73014f788032
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0
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1 ; OSTC - diving computer code
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2 ; Copyright (C) 2008 HeinrichsWeikamp GbR
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3
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4 ; This program is free software: you can redistribute it and/or modify
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5 ; it under the terms of the GNU General Public License as published by
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6 ; the Free Software Foundation, either version 3 of the License, or
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7 ; (at your option) any later version.
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8
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9 ; This program is distributed in the hope that it will be useful,
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10 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 ; GNU General Public License for more details.
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13
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14 ; You should have received a copy of the GNU General Public License
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15 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
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16
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17
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18 ; internal EEPROM and RS232 UART interface
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19 ; written by: Matthias Heinrichs, info@heinrichsweikamp.com
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20 ; written: 02/01/06
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21 ; last updated: 090109
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22 ; known bugs:
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23 ; ToDo:
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24
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25 write_int_eeprom macro eeprom_address
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26 movlw eeprom_address
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27 call write_int_eeprom_1
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28 endm
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29
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30 write_int_eeprom_1:
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31 movwf EEADR
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32 bra write_eeprom ; writes and "returns" after write
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33
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34 read_int_eeprom macro eeprom_address
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35 movlw eeprom_address
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36 call read_int_eeprom_1
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37 endm
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38
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39 read_int_eeprom_1:
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40 movwf EEADR
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41 bra read_eeprom ; reads and "returns" after write
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42
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43 internal_eeprom_access_b1: ; accesses internal EEPROM BANK 1 via the UART
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44 bcf internal_eeprom_write2 ; clear flag!
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45 movlw d'1'
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46 movwf EEADRH ;BANK1
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47 movlw "i"
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48 bra internal_eeprom_access1 ; Continue with bank1 and bank0 common routines
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49
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50 internal_eeprom_access_b0: ; accesses internal EEPROM BANK 0 via the UART
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51 bcf internal_eeprom_write ; clear flag!
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52 clrf EEADRH ; Bank0
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53 movlw "d"
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54 ; bra internal_eeprom_access1 ; Continue with bank1 and bank0 common routines
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55
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56 internal_eeprom_access1:
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57 movwf TXREG ; Send command echo ("i" or "d")
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58 bsf no_sensor_int ; No Sensor Interrupt
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59 movlw d'4'
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60 movwf EEADR
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61 bcf PIE1,RCIE ; no interrupt for UART
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62 bcf PIR1,RCIF ; clear flag
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63 call set_LEDusb ; LEDusb ON
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64
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65 internal_eeprom_access2:
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66 rcall rs232_get_byte ; Get byte to write...
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67 movff RCREG,EEDATA ; copy to write register
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68 call set_LEDy ; show activity
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69
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70 btfsc rs232_recieve_overflow ; overflow recieved?
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71 bra internal_eeprom_access3 ; Yes, abort!
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72
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73 rcall write_eeprom ; No, write one byte
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74 call clear_LEDy
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75 movff EEDATA,TXREG ; Send echo!
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76 rcall rs232_wait_tx ; Wait for UART
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77 incfsz EEADR,F ; Do until EEADR rolls to zero
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78 bra internal_eeprom_access2
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79 internal_eeprom_access2a:
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80 call clear_LEDusb ; LEDusb OFF
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81 bcf PIR1,RCIF ; clear flag
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82 bsf PIE1,RCIE ; re-enable interrupt for UART
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83 clrf EEADRH ; Point to Bank0 again
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84 bcf rs232_recieve_overflow ; Clear Flag
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85 bcf no_sensor_int ; Renable Sensor Interrupt
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86 goto restart
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87
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88 internal_eeprom_access3: ; Overflow! Abort writing
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89 movlw 0xFF
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90 movwf TXREG ; Error Byte
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91 bra internal_eeprom_access2a ; Quit
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92
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93 read_eeprom: ; reads from internal eeprom
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94 bcf EECON1,EEPGD
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95 bcf EECON1,CFGS
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96 bsf EECON1,RD
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97 return
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98
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99 write_eeprom: ; writes into internal eeprom
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100 bcf EECON1,EEPGD
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101 bcf EECON1,CFGS
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102 bsf EECON1,WREN
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103
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104 bcf INTCON,GIE ; even the RTC will be delayed for the next 5 instructions...
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105 movlw 0x55
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106 movwf EECON2
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107 movlw 0xAA
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108 movwf EECON2
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109 bsf EECON1,WR
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110 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
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111
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112 write_eep2:
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113 btfsc EECON1,WR
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114 bra write_eep2 ; wait about 4ms...
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115 bcf EECON1,WREN
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116 return
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117
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118
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119
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120 ; RS232 Routines:
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121 ;enable_rs232_19k2_tx:
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122 ; bsf TRISC,6 ; TX Pin
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123 ; movlw b'00100100' ; initialise serial port for 19200/8/N/1 BRGH=1
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124 ; movwf TXSTA
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125 ; return
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126 ;
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127 ;disable_rs232_19k2_tx:
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128 ; bcf TRISC,6 ; TX Pin
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129 ; movlw b'00000100' ; Only receiver mode, BRGH=1
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130 ; movwf TXSTA
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131 ; bsf PORTC,6 ; TX PIN
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132 ; return
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133 ;
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134 ;enable_rs232_19k2:
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135 ; bsf TRISC,6 ; TX Pin IO Ports must be input in order to activate the module
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136 ; bsf TRISC,7 ; RX Pin
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137 ;
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138 ; movlw b'00100100' ; initialise serial port for 19200/8/N/1 BRGH=1
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139 ; movwf TXSTA
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140 ; movlw b'10000000'
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141 ; movwf RCSTA
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142 ; movlw b'00001000' ; BRG16=1
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143 ; movwf BAUDCON
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144 ; bsf RCSTA,CREN ; Enable
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145 ; movlw d'0'
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146 ; movwf SPBRGH
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147 ; movlw d'207' ; Take care of the baud rate when changing Fosc!
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148 ; movwf SPBRG
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149 ; clrf RCREG
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150 ; bcf PIE1,RCIE ; disable interrupt for RS232
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151 ; clrf PIR1
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152 ; return
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153 ;
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154
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155 enable_rs232: ;IO Ports must be input in order to activate the module
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156 bsf TRISC,6 ; TX Pin
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157 bsf TRISC,7 ; RX Pin
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158
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159 movlw b'00100100' ; BRGH=1
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160 movwf TXSTA
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161 movlw b'10010000'
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162 movwf RCSTA
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163 movlw b'00001000'
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164 movwf BAUDCON
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165 clrf SPBRGH
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166 movlw d'34' ; Take care of the baud rate when changing Fosc!
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167 movwf SPBRG
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168 clrf RCREG
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169 clrf PIR1
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170 bsf PIE1,RCIE ; enable interrupt for RS232
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171 return
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172
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173 disable_rs232:
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174 clrf TXSTA
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175 clrf RCSTA
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176 bcf PIE1,RCIE ; disable interrupt for RS232
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177 bcf TRISC,6 ; TX Pin
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178 bcf TRISC,7 ; RX Pin
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179 bcf PORTC,6 ; TX Pin
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180 bcf PORTC,7 ; RX Pin
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181 return
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182
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183 rs232_wait_tx:
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184 btfss RCSTA,SPEN ; Transmitter active?
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185 return ; No, return!
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186 nop
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187 btfss TXSTA,TRMT ; RS232 Busy?
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188 bra rs232_wait_tx ; yes, wait...
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189 return ; Done.
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190
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191
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192 rs232_get_byte:
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193 bcf PIR1,RCIF ; clear flag
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194 bcf rs232_recieve_overflow ; clear flag
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195 clrf uart1_temp
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196 rs232_get_byte2:
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197 clrf uart2_temp
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198 rs232_get_byte3:
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199 btfsc PIR1,RCIF ; data arrived?
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200 return ; data received
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201
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202 nop ; Wait 1us * 255 * 255 = 65ms+x Timeout/Byte
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203 nop
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204 nop
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205 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
206 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
207 return
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
208
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
209 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
210 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
211 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
212 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
213 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
214 return
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
215
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
216 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
217 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
218 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
219 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
220 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
221 return
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
222 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
223 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
224 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
225 nop
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
226 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
227 return
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
228
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
229 decfsz uart2_temp,F
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
230 bra rs232_get_byte3
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
231 decfsz uart1_temp,F
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
232 bra rs232_get_byte2
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
233 ; timeout occoured (about 20ms)
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
234 bcf RCSTA,CREN ; Clear receiver status
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
235 bsf RCSTA,CREN
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
236 bsf rs232_recieve_overflow ; set flag
96a35aeda5f2 Initial setup
heinrichsweikamp
parents:
diff changeset
237 return ; and return anyway