mk2: code_part1/OSTC_code_asm_part1/eeprom

annotate code_part1/OSTC_code_asm_part1/eeprom_rs232.asm @ 521:33abbc08f01e

Minor cleanups for TESTING=1 emulator mode.

author	JeanDo
date	Fri, 09 Dec 2011 20:43:39 +0100
parents	86fc79735d3b
children	e2acb601504c

rev	line source
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	1 ; OSTC - diving computer code
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	2 ; Copyright (C) 2008 HeinrichsWeikamp GbR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	3
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	4 ; This program is free software: you can redistribute it and/or modify
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	5 ; it under the terms of the GNU General Public License as published by
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	6 ; the Free Software Foundation, either version 3 of the License, or
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	7 ; (at your option) any later version.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	8
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	9 ; This program is distributed in the hope that it will be useful,
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	10 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	11 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	12 ; GNU General Public License for more details.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	13
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	14 ; You should have received a copy of the GNU General Public License
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	15 ; along with this program. If not, see <http://www.gnu.org/licenses/>.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	16
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	17
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	18 ; internal EEPROM and RS232 UART interface
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	19 ; written by: Matthias Heinrichs, info@heinrichsweikamp.com
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	20 ; written: 02/01/06
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	21 ; last updated: 090109
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	22 ; known bugs:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	23 ; ToDo:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	24
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	25 write_int_eeprom macro eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	26 movlw eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	27 call write_int_eeprom_1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	28 endm
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	29
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	30 write_int_eeprom_1:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	31 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	32 bra write_eeprom ; writes and "returns" after write
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	33
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	34 read_int_eeprom macro eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	35 movlw eeprom_address
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	36 call read_int_eeprom_1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	37 endm
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	38
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	39 read_int_eeprom_1:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	40 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	41 bra read_eeprom ; reads and "returns" after write
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	42
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	43 internal_eeprom_access_b1: ; accesses internal EEPROM BANK 1 via the UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	44 bcf internal_eeprom_write2 ; clear flag!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	45 movlw d'1'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	46 movwf EEADRH ;BANK1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	47 movlw "i"
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	48 bra internal_eeprom_access1 ; Continue with bank1 and bank0 common routines
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	49
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	50 internal_eeprom_access_b0: ; accesses internal EEPROM BANK 0 via the UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	51 bcf internal_eeprom_write ; clear flag!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	52 clrf EEADRH ; Bank0
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	53 movlw "d"
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	54 ; bra internal_eeprom_access1 ; Continue with bank1 and bank0 common routines
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	55
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	56 internal_eeprom_access1:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	57 movwf TXREG ; Send command echo ("i" or "d")
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	58 bsf no_sensor_int ; No Sensor Interrupt
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	59 movlw d'4'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	60 movwf EEADR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	61 bcf PIE1,RCIE ; no interrupt for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	62 bcf PIR1,RCIF ; clear flag
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	63 bsf LED_blue ; LEDusb ON
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	64
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	65 internal_eeprom_access2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	66 rcall rs232_get_byte ; Get byte to write...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	67 movff RCREG,EEDATA ; copy to write register
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	68 bsf LED_red ; show activity
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	69
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	70 btfsc rs232_recieve_overflow ; overflow recieved?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	71 bra internal_eeprom_access3 ; Yes, abort!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	72
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	73 rcall write_eeprom ; No, write one byte
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	74 bcf LED_red
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	75 movff EEDATA,TXREG ; Send echo!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	76 rcall rs232_wait_tx ; Wait for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	77 incfsz EEADR,F ; Do until EEADR rolls to zero
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	78 bra internal_eeprom_access2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	79 internal_eeprom_access2a:
21 73014f788032 1.60 stable rc1 heinrichsweikamp parents: 0 diff changeset	80 bcf LED_blue ; LEDusb OFF
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	81 bcf PIR1,RCIF ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	82 bsf PIE1,RCIE ; re-enable interrupt for UART
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	83 clrf EEADRH ; Point to Bank0 again
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	84 bcf rs232_recieve_overflow ; Clear Flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	85 bcf no_sensor_int ; Renable Sensor Interrupt
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	86 goto restart
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	87
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	88 internal_eeprom_access3: ; Overflow! Abort writing
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	89 movlw 0xFF
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	90 movwf TXREG ; Error Byte
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	91 bra internal_eeprom_access2a ; Quit
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	92
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	93 read_eeprom: ; reads from internal eeprom
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	94 bcf EECON1,EEPGD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	95 bcf EECON1,CFGS
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	96 bsf EECON1,RD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	97 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	98
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	99 write_eeprom: ; writes into internal eeprom
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	100 bcf EECON1,EEPGD
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	101 bcf EECON1,CFGS
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	102 bsf EECON1,WREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	103
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	104 bcf INTCON,GIE ; even the RTC will be delayed for the next 5 instructions...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	105 movlw 0x55
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	106 movwf EECON2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	107 movlw 0xAA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	108 movwf EECON2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	109 bsf EECON1,WR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	110 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	111
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	112 write_eep2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	113 btfsc EECON1,WR
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	114 bra write_eep2 ; wait about 4ms...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	115 bcf EECON1,WREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	116 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	117
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	118 enable_rs232: ;IO Ports must be input in order to activate the module
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	119 bsf TRISC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	120 bsf TRISC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	121
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	122 movlw b'00100100' ; BRGH=1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	123 movwf TXSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	124 movlw b'10010000'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	125 movwf RCSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	126 movlw b'00001000'
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	127 movwf BAUDCON
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	128 clrf SPBRGH
463 86fc79735d3b Experimental 32MHz mode heinrichsweikamp parents: 284 diff changeset	129 movlw SPBRG_VALUE ; Take care of the baud rate when changing Fosc!
0 96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	130 movwf SPBRG
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	131 clrf RCREG
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	132 clrf PIR1
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	133 bsf PIE1,RCIE ; enable interrupt for RS232
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	134 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	135
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	136 disable_rs232:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	137 clrf TXSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	138 clrf RCSTA
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	139 bcf PIE1,RCIE ; disable interrupt for RS232
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	140 bcf TRISC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	141 bcf TRISC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	142 bcf PORTC,6 ; TX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	143 bcf PORTC,7 ; RX Pin
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	144 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	145
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	146 rs232_wait_tx:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	147 btfss RCSTA,SPEN ; Transmitter active?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	148 return ; No, return!
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	149 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	150 btfss TXSTA,TRMT ; RS232 Busy?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	151 bra rs232_wait_tx ; yes, wait...
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	152 return ; Done.
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	153
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	154
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	155 rs232_get_byte:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	156 bcf PIR1,RCIF ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	157 bcf rs232_recieve_overflow ; clear flag
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	158 clrf uart1_temp
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	159 rs232_get_byte2:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	160 clrf uart2_temp
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	161 rs232_get_byte3:
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	162 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	163 return ; data received
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	164
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	165 nop ; Wait 1us * 255 * 255 = 65ms+x Timeout/Byte
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	166 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	167 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	168 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	169 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	170 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	171
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	172 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	173 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	174 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	175 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	176 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	177 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	178
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	179 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	180 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	181 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	182 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	183 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	184 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	185 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	186 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	187 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	188 nop
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	189 btfsc PIR1,RCIF ; data arrived?
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	190 return
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	191
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	192 decfsz uart2_temp,F
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	193 bra rs232_get_byte3
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	194 decfsz uart1_temp,F
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	195 bra rs232_get_byte2
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	196 ; timeout occoured (about 20ms)
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	197 bcf RCSTA,CREN ; Clear receiver status
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	198 bsf RCSTA,CREN
96a35aeda5f2 Initial setup heinrichsweikamp parents: diff changeset	199 bsf rs232_recieve_overflow ; set flag
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	200 return ; and return anyway
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	201
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	202 uart_115k_bootloader:
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	203 bcf PIE1,RCIE ; disable interrupt for RS232
284 908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	204 ; bcf PIR1,RCIF ; clear flag
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	205 call PLED_ClearScreen ; Clear screen
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	206 movlw color_red
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	207 call PLED_set_color ; Set to Red
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	208 DISPLAYTEXTH d'302' ; Bootloader
284 908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	209 movlw d'4' ; one second
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	210 movwf uart1_temp
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	211 uart_115k_bootloader0:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	212 btfsc PIR1,RCIF ; New byte in UART?
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	213 bra uart_115k_bootloader1 ; Yes, Check if 0xC1
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	214 WAITMS d'250'
284 908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	215 decfsz uart1_temp,F
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	216 bra uart_115k_bootloader0
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	217 uart_115k_bootloader2:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	218 DISPLAYTEXTH d'304' ; Aborted!
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	219 movlw d'8' ; Two seconds
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	220 movwf uart1_temp
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	221 uart_115k_bootloader3:
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	222 WAITMS d'250'
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	223 decfsz uart1_temp,F
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	224 bra uart_115k_bootloader3
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	225 goto restart
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	226
908d0013727e 115200 baud bootloader tested and debugged heinrichsweikamp parents: 283 diff changeset	227 uart_115k_bootloader1:
283 4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	228 movlw 0xC1
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	229 cpfseq RCREG ; 115200Baud Bootloader request?
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	230 bra uart_115k_bootloader2 ; No, Abort
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	231 DISPLAYTEXTH d'303' ; Yes, "Please wait!"
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	232 clrf INTCON ; Interrupts disabled
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	233 bcf PIR1,RCIF ; clear flag
4ec488f046f4 Battery sign color coded, work on new uart-started 115200Baud bootloader (Do NOT use yet!) heinrichsweikamp parents: 50 diff changeset	234 goto 0x17F56 ; Enter straight into bootloader. Good luck!

Mercurial > public > mk2

annotate code_part1/OSTC_code_asm_part1/eeprom_rs232.asm @ 521:33abbc08f01e