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comparison src/ostc3.asm @ 1:e4e662746c02

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init2
author heinrichsweikamp
date Wed, 24 Apr 2013 19:39:39 +0200
parents 11d4fc797f74
children fcaf94b913db
comparison
equal deleted inserted replaced
0:11d4fc797f74 1:e4e662746c02
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code. 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
11 ; 2011-06-24 : [MH] Added clock speeds. 11 ; 2011-06-24 : [MH] Added clock speeds.
12 #include "ostc3.inc" 12 #include "ostc3.inc"
13 13
14 ;============================================================================= 14 ;=============================================================================
15 ;
16 ;----------------------------- CONFIG --------------------------------- 15 ;----------------------------- CONFIG ---------------------------------
17 ; CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit 16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
18 ; CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected 17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
19 ; CONFIG XINST = OFF ;Code won't excute in extended mode... 18 CONFIG XINST = OFF ;Code won't excute in extended mode...
20 ; CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out 19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out
21 ; CONFIG PLLCFG = OFF 20 CONFIG PLLCFG = OFF
22 ; CONFIG IESO = OFF ;Disabled 21 CONFIG IESO = OFF ;Disabled
23 ; CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400) 22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400)
24 ; CONFIG BOREN = ON ;Controlled with SBOREN bit 23 CONFIG BOREN = ON ;Controlled with SBOREN bit
25 ; CONFIG BORV = 2 ;2.0V 24 CONFIG BORV = 2 ;2.0V
26 ; CONFIG BORPWR = MEDIUM ;BORMV set to medium power level 25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
27 ; CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting 26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
28 ; CONFIG WDTPS = 128 ;1:128 27 CONFIG WDTPS = 128 ;1:128
29 ; CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC 28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
30 ; CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled 29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
31 ; CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes 30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
32 ;============================================================================= 31 ;=============================================================================
33 boot CODE 32 boot CODE
34 global init_ostc3 33 global init_ostc3
35 34
36 init_ostc3: 35 init_ostc3: