Mercurial > public > hwos_code

comparison src/hwos.asm @ 608:d866684249bd

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
work on 2.99 stable
author heinrichsweikamp
date Mon, 07 Jan 2019 21:13:43 +0100
parents ca4556fb60b9
children 2ce43f09586e
comparison
equal deleted inserted replaced
607:c5151a490d88 608:d866684249bd
1 ;============================================================================= 1 ;=============================================================================
2 ; 2 ;
3 ; File hwos.asm V2.98c 3 ; File hwos.asm V2.98f
4 ; 4 ;
5 ; Definition of the hwOS dive computer platform. 5 ; Definition of the hwOS dive computer platform.
6 ; 6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;============================================================================= 8 ;=============================================================================
35 35
36 ;============================================================================= 36 ;=============================================================================
37 37
38 global init_ostc 38 global init_ostc
39 init_ostc: 39 init_ostc:
40 ; init oscillator
40 banksel common ; bank 1 41 banksel common ; bank 1
41 ; init oscillator
42 movlw b'01110010' 42 movlw b'01110010'
43 movwf OSCCON ; 16 MHz INTOSC 43 movwf OSCCON ; 16 MHz INTOSC
44 movlw b'00001000' 44 movlw b'00001000'
45 movwf OSCCON2 ; secondary oscillator running 45 movwf OSCCON2 ; secondary oscillator running
46 movlw b'00000000' 46 movlw b'00000000'
47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) 47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
48 bcf RCON,SBOREN ; bown-out off 48
49 movlw d'2' ; coding for speed normal
50 movff WREG,cpu_speed_request ; CPU shall run with normal speed
51 movff WREG,cpu_speed_state ; CPU does run with normal speed
52
53 bcf RCON,SBOREN ; brown-out off
49 bcf RCON,IPEN ; priority interrupts off 54 bcf RCON,IPEN ; priority interrupts off
50 clrf CM1CON ; disable 55
51 banksel WDTCON 56 banksel WDTCON
52 movlw b'10000000' 57 movlw b'10000000'
53 movwf WDTCON ; setup watchdog 58 movwf WDTCON ; setup watchdog
59
54 60
55 ; I/O Ports 61 ; I/O Ports
56 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM 62 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
57 63
58 clrf REFOCON ; no reference oscillator active on REFO pin 64 clrf REFOCON ; no reference oscillator active on REFO pin
59 clrf ODCON1 ; disable open drain capability 65 clrf ODCON1 ; disable open drain capability
60 clrf ODCON2 ; disable open drain capability 66 clrf ODCON2 ; disable open drain capability
61 clrf ODCON3 ; disable open drain capability 67 clrf ODCON3 ; disable open drain capability
68 clrf CM1CON ; disable
62 clrf CM2CON ; disable 69 clrf CM2CON ; disable
63 clrf CM3CON ; disable 70 clrf CM3CON ; disable
64 71
65 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital 72 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital
66 movwf ANCON0 73 movwf ANCON0
123 130
124 ; Timer 1 - Button hold-down timer 131 ; Timer 1 - Button hold-down timer
125 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H 132 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H
126 movwf T1CON 133 movwf T1CON
127 134
128 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
129
130 ; RTCC 135 ; RTCC
131 movlw 0x55 136 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
132 movwf EECON2 137 movlw 0x55
133 movlw 0xAA 138 movwf EECON2
134 movwf EECON2 139 movlw 0xAA
135 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN 140 movwf EECON2
141 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
136 bsf RTCCFG,RTCPTR1 142 bsf RTCCFG,RTCPTR1
137 bsf RTCCFG,RTCPTR0 143 bsf RTCCFG,RTCPTR0
138 bsf RTCCFG,RTCEN ; module enable 144 bsf RTCCFG,RTCEN ; Module enable
139 bsf RTCCFG,RTCOE ; output enable 145 bsf RTCCFG,RTCOE ; Output enable
140 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pullups for Port D, E and J 146 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J
141 movwf PADCFG1 147 movwf PADCFG1
142 movlw b'11000100' 148 movlw b'11000100'
143 movwf ALRMCFG ; 1 second alarm 149 movwf ALRMCFG ; 1 second alarm
144 movlw d'1' 150 movlw d'1'
145 movwf ALRMRPT ; alarm repeat counter 151 movwf ALRMRPT ; Alarm repeat counter
146 movlw 0x55 152 movlw 0x55
147 movwf EECON2 153 movwf EECON2
148 movlw 0xAA 154 movlw 0xAA
149 movwf EECON2 155 movwf EECON2
150 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN 156 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
151
152 banksel common 157 banksel common
158
153 ; A/D Converter 159 ; A/D Converter
154 movlw b'00011000' ; power off ADC, select AN6 160 movlw b'00011000' ; power off ADC, select AN6
155 movwf ADCON0 161 movwf ADCON0
156 movlw b'00100000' ; 2.048V Vref+ 162 movlw b'00100000' ; 2.048V Vref+
157 movwf ADCON1 163 movwf ADCON1
234 movwf T7CON 240 movwf T7CON
235 clrf TMR7L 241 clrf TMR7L
236 movlw .248 242 movlw .248
237 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms 243 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
238 244
245 ; Turn off unused timer
246 movlw b'11000000'
247 movwf PMD0
248 movlw b'11010001'
249 movwf PMD1
250 movlw b'11010111'
251 movwf PMD2
252 movlw b'11111111'
253 movwf PMD3
254
255 ; CTMU
256 clrf CTMUCONH
257 clrf CTMUCONL
258 clrf CTMUICON
239 banksel common 259 banksel common
260
240 ; Interrupts 261 ; Interrupts
241 movlw b'11010000' 262 movlw b'11010000'
242 movwf INTCON 263 movwf INTCON
243 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled 264 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled
244 movwf INTCON2 265 movwf INTCON2
260 bra $-4 281 bra $-4
261 bsf power_sw2 282 bsf power_sw2
262 btfss power_sw2 283 btfss power_sw2
263 bra $-4 284 bra $-4
264 285
265 movlw d'2'
266 movff WREG,speed_setting ; normal
267
268 bcf active_reset_ostc_rx ; start RX from RESET 286 bcf active_reset_ostc_rx ; start RX from RESET
269 287
270 return 288 return
271 289
272 ;============================================================================= 290 ;=============================================================================
273 global speed_eco 291 global speed_eco
274 speed_eco: 292 speed_eco:
275 movlw d'1' 293 movlw d'1'
276 movff WREG,speed_setting ; bank-independent 294 movff WREG,cpu_speed_request ; bank-independent
277 ; Done in ISR 295 ; Done in ISR
278 return 296 return
279 ;============================================================================= 297 ;=============================================================================
280 global speed_normal 298 global speed_normal
281 speed_normal: 299 speed_normal:
282 movlw d'2' 300 movlw d'2'
283 movff WREG,speed_setting ; bank-independent 301 movff WREG,cpu_speed_request ; bank-independent
284 ; Done in ISR 302 ; Done in ISR
285 return 303 return
286 ;============================================================================= 304 ;=============================================================================
287 global speed_fastest 305 global speed_fastest
288 speed_fastest: 306 speed_fastest:
289 movlw d'3' 307 movlw d'3'
290 movff WREG,speed_setting ; bank-independent 308 movff WREG,cpu_speed_request ; bank-independent
291 ; Done in ISR 309 ; Done in ISR
292 return 310 return
293 ;============================================================================= 311 ;=============================================================================
294 312
295 END 313 END