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BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
author heinrichsweikamp
date Tue, 08 Mar 2016 11:42:58 +0100
parents 7faa688db105
children aadfe9f2edaf
comparison
equal deleted inserted replaced
409:f141018d66b0 410:d3087a8ed7e1
11 11
12 #include "hwos.inc" 12 #include "hwos.inc"
13 #include "shared_definitions.h" ; Mailbox from/to p2_deco.c 13 #include "shared_definitions.h" ; Mailbox from/to p2_deco.c
14 #include "ms5541.inc" 14 #include "ms5541.inc"
15 #include "adc_lightsensor.inc" 15 #include "adc_lightsensor.inc"
16 #include "eeprom_rs232.inc"
16 17
17 ;============================================================================= 18 ;=============================================================================
18 19
19 extern start 20 extern start
20 21
59 rcall isr_rtcc ; May return in bank common! 60 rcall isr_rtcc ; May return in bank common!
60 61
61 movff isr_prod+1,PRODH 62 movff isr_prod+1,PRODH
62 movff isr_prod+0,PRODL 63 movff isr_prod+0,PRODL
63 retfie FAST ; Restores BSR, STATUS and WREG 64 retfie FAST ; Restores BSR, STATUS and WREG
65
66 isr_set_speed_to_normal:
67 ; Set Speed to normal
68 movlw b'01110010'
69 movwf OSCCON ; 16MHz INTOSC
70 movlw b'00000000'
71 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
72 movlw b'00001101' ; 1:2 Postscaler, 1:4 Prescaler, Timer 2 start -> 1960Hz (no-flicker)
73 movwf T2CON
74 btfss OSCCON,HFIOFS
75 bra $-2 ; Wait until clock is stable
76 return
77
78 isr_dimm_tft: ; Adjust until max_CCPR1L=CCPR1L !
79 banksel common
80 btfsc tft_is_dimming ; Ignore while dimming
81 return
82 banksel isr_backup
83 movf max_CCPR1L,W
84 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L?
85 bra isr_dimm_tft2 ; No, dimm up
86 ; dimm down
87 decf CCPR1L,F ; -1
88 return
89 isr_dimm_tft2:
90 movf max_CCPR1L,W
91 sublw ambient_light_min_eco
92 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L-ambient_light_min_eco?
93 bra isr_dimm_tft3 ; No, dimm up slow
94 ; dimm up faster
95 movlw .10
96 addwf CCPR1L,F
97 isr_dimm_tft3:
98 incf CCPR1L,F ; +1
99 return
100 nop
101 nop ; block flash here
102
103 isr_restore CODE 0x00080 ; Restore first flash page from EEPROM
104 restore_flash_0x00080:
105 goto restore_flash
106
64 107
65 ;============================================================================= 108 ;=============================================================================
66 109
67 isr_uart2: ; IR/S8-Link 110 isr_uart2: ; IR/S8-Link
68 banksel RCREG2 111 banksel RCREG2
317 banksel common 360 banksel common
318 btfss no_sensor_int ; No sensor interrupt (because it's addressed during sleep) 361 btfss no_sensor_int ; No sensor interrupt (because it's addressed during sleep)
319 bra isr_sensor_state2 ; No, continue 362 bra isr_sensor_state2 ; No, continue
320 banksel isr_backup ; Back to Bank0 ISR data 363 banksel isr_backup ; Back to Bank0 ISR data
321 return 364 return
322
323 isr_set_speed_to_normal:
324 ; Set Speed to normal
325 movlw b'01110010'
326 movwf OSCCON ; 16MHz INTOSC
327 movlw b'00000000'
328 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
329 movlw b'00001101' ; 1:2 Postscaler, 1:4 Prescaler, Timer 2 start -> 1960Hz (no-flicker)
330 movwf T2CON
331 btfss OSCCON,HFIOFS
332 bra $-2 ; Wait until clock is stable
333 return
334 365
335 isr_sensor_state2: 366 isr_sensor_state2:
336 banksel common 367 banksel common
337 movff sensor_state_counter,WREG 368 movff sensor_state_counter,WREG
338 btfss WREG,0 ; every 1/4 second 369 btfss WREG,0 ; every 1/4 second
484 sensor_int_state_exit: 515 sensor_int_state_exit:
485 rcall isr_restore_clock ; Restore clock 516 rcall isr_restore_clock ; Restore clock
486 return 517 return
487 ;============================================================================= 518 ;=============================================================================
488 519
489 isr_dimm_tft: ; Adjust until max_CCPR1L=CCPR1L !
490 banksel common
491 btfsc tft_is_dimming ; Ignore while dimming
492 return
493 banksel isr_backup
494 movf max_CCPR1L,W
495 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L?
496 bra isr_dimm_tft2 ; No, dimm up
497 ; dimm down
498 decf CCPR1L,F ; -1
499 return
500 isr_dimm_tft2:
501 movf max_CCPR1L,W
502 sublw ambient_light_min_eco
503 cpfsgt CCPR1L ; CCPR1L>max_CCPR1L-ambient_light_min_eco?
504 bra isr_dimm_tft3 ; No, dimm up slow
505 ; dimm up faster
506 movlw .10
507 addwf CCPR1L,F
508 isr_dimm_tft3:
509 incf CCPR1L,F ; +1
510 return
511 520
512 521
513 isr_rtcc: ; each second 522 isr_rtcc: ; each second
514 bcf PIR3,RTCCIF ; clear flag 523 bcf PIR3,RTCCIF ; clear flag
515 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. 524 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
850 isr_restore_exit: 859 isr_restore_exit:
851 btfss OSCCON,HFIOFS 860 btfss OSCCON,HFIOFS
852 bra isr_restore_exit ; loop until PLL is stable 861 bra isr_restore_exit ; loop until PLL is stable
853 return 862 return
854 863
864
865 restore_flash: ; Restore first flash page from eeprom
866 banksel common
867 ; Start address in internal flash
868 movlw 0x00
869 movwf TBLPTRL
870 movwf TBLPTRH
871 movwf TBLPTRU
872
873 movlw b'10010100' ; Setup erase
874 rcall Write ; Write!
875
876 movlw .128
877 movwf lo ; Byte counter
878 clrf EEADR
879 movlw .3
880 movwf EEADRH ; Setup backup address
881
882 TBLRD*- ; Dummy read to be in 128 byte block
883 restore_flash_loop:
884 call read_eeprom
885 incf EEADR,F
886 movff EEDATA,TABLAT ; put 1 byte
887 tblwt+* ; Table Write with Pre-Increment
888 decfsz lo,F ; 128byte done?
889 bra restore_flash_loop ; No
890
891 movlw b'10000100' ; Setup writes
892 rcall Write ; Write!
893
894 reset ; Done, reset CPU
895
896 Write:
897 movwf EECON1 ; Type of memory to write in
898 movlw 0x55
899 movwf EECON2
900 movlw 0xAA
901 movwf EECON2
902 bsf EECON1,WR ; Write
903 nop
904 nop
905 return
906
907
855 END 908 END