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comparison src/varargs.inc @ 604:ca4556fb60b9

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bump to 2.99beta, work on 3.00 stable
author heinrichsweikamp
date Thu, 22 Nov 2018 19:47:26 +0100
parents 11d4fc797f74
children c40025d8e750
comparison
equal deleted inserted replaced
603:00b24fb4324d 604:ca4556fb60b9
8 ;============================================================================= 8 ;=============================================================================
9 ; HISTORY 9 ; HISTORY
10 ; 2011-05-27 : [jDG] Creation. 10 ; 2011-05-27 : [jDG] Creation.
11 ; 11 ;
12 12
13 VARARGS_BEGIN macro 13 VARARGS_BEGIN macro
14 movff TOSL, TBLPTRL 14 movff TOSL, TBLPTRL
15 movff TOSH, TBLPTRH 15 movff TOSH, TBLPTRH
16 movff TOSU, TBLPTRU 16 movff TOSU, TBLPTRU
17 endm 17 endm
18 18
19 VARARGS_GET8 macro register 19 VARARGS_GET8 macro register
20 tblrd*+ 20 tblrd*+
21 movff TABLAT, register 21 movff TABLAT, register
22 endm 22 endm
23 23
24 VARARGS_GET16 macro register 24 VARARGS_GET16 macro register
25 tblrd*+ 25 tblrd*+
26 movff TABLAT, register+0 26 movff TABLAT, register+0
27 tblrd*+ 27 tblrd*+
28 movff TABLAT, register+1 28 movff TABLAT, register+1
29 endm 29 endm
30 30
31 VARARGS_GET24 macro register 31 VARARGS_GET24 macro register
32 tblrd*+ 32 tblrd*+
33 movff TABLAT, register+0 33 movff TABLAT, register+0
34 tblrd*+ 34 tblrd*+
35 movff TABLAT, register+1 35 movff TABLAT, register+1
36 tblrd*+ 36 tblrd*+
37 movff TABLAT, register+2 37 movff TABLAT, register+2
38 endm 38 endm
39 39
40 VARARGS_ALIGN macro 40 VARARGS_ALIGN macro
41 local no_tblptr_align 41 local no_tblptr_align
42 42
43 btfss TBLPTRL,0 43 btfss TBLPTRL,0
44 bra no_tblptr_align 44 bra no_tblptr_align
45 incf TBLPTRL 45 incf TBLPTRL
46 movlw 0 46 movlw 0
47 addwfc TBLPTRH 47 addwfc TBLPTRH
48 addwfc TBLPTRU 48 addwfc TBLPTRU
49 no_tblptr_align: 49 no_tblptr_align:
50 endm 50 endm
51 51
52 VARARGS_END macro 52 VARARGS_END macro
53 ; Compute string length (modulo 256): 53 ; compute string length (modulo 256):
54 movf TOSL,W 54 movf TOSL,W
55 subwf TBLPTRL,W 55 subwf TBLPTRL,W
56
57 ; Then 24bit add to return address
58 addwf TOSL,F
59 movlw 0 ; Clear WREG, but keep carry
60 addwfc TOSH,F
61 addwfc TOSU,F
62 endm
63 56
57 ; then 24 bit add to return address
58 addwf TOSL,F
59 movlw 0 ; clear WREG, but keep carry
60 addwfc TOSH,F
61 addwfc TOSU,F
62 endm
63