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bump to 2.99beta, work on 3.00 stable
author heinrichsweikamp
date Thu, 22 Nov 2018 19:47:26 +0100
parents 69a98f3f3b84
children d866684249bd
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603:00b24fb4324d 604:ca4556fb60b9
1 ;============================================================================= 1 ;=============================================================================
2 ; 2 ;
3 ; File hwos.asm 3 ; File hwos.asm V2.98c
4 ; 4 ;
5 ; Definition of the hwOS dive computer platform. 5 ; Definition of the hwOS dive computer platform.
6 ; 6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;============================================================================= 8 ;=============================================================================
9 ; HISTORY 9 ; HISTORY
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code. 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code
11 ; 2011-06-24 : [MH] Added clock speeds. 11 ; 2011-06-24 : [MH] Added clock speeds
12
13
12 #include "hwos.inc" 14 #include "hwos.inc"
13 15
14 ;============================================================================= 16 ;=============================================================================
15 ;----------------------------- CONFIG --------------------------------- 17 ;----------------------------- CONFIG ---------------------------------
16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit 18 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit
17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected 19 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected
18 CONFIG XINST = OFF ;Code won't excute in extended mode... 20 CONFIG XINST = OFF ; code won't execute in extended mode
19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out 21 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out
20 CONFIG PLLCFG = OFF 22 CONFIG PLLCFG = OFF
21 CONFIG IESO = OFF ;Disabled 23 CONFIG IESO = OFF ; disabled
22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400) 24 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400)
23 CONFIG BOREN = ON ;Controlled with SBOREN bit 25 CONFIG BOREN = ON ; controlled with SBOREN bit
24 CONFIG BORV = 2 ;2.0V 26 CONFIG BORV = 2 ; 2.0V
25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level 27 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level
26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting 28 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting
27 CONFIG WDTPS = 128 ;1:128 29 CONFIG WDTPS = 128 ; 1:128
28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC 30 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC
29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled 31 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled
30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes 32 CONFIG CCP2MX = PORTBE ; RE7-microcontroller mode/RB3-all other modes
31 ;============================================================================= 33
32 boot CODE 34 hwos CODE
33 global init_ostc 35
34 36 ;=============================================================================
37
38 global init_ostc
35 init_ostc: 39 init_ostc:
36 banksel common ; Bank1 40 banksel common ; bank 1
37 ;init oscillator 41 ; init oscillator
38 movlw b'01110010' 42 movlw b'01110010'
39 movwf OSCCON ; 16MHz INTOSC 43 movwf OSCCON ; 16 MHz INTOSC
40 movlw b'00001000' 44 movlw b'00001000'
41 movwf OSCCON2 ; Secondary Oscillator running 45 movwf OSCCON2 ; secondary oscillator running
42 movlw b'00000000' 46 movlw b'00000000'
43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz) 47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
44 bcf RCON,SBOREN ; Bown-Out off 48 bcf RCON,SBOREN ; bown-out off
45 bcf RCON,IPEN ; Priority Interrupts off 49 bcf RCON,IPEN ; priority interrupts off
46 clrf CM1CON ; Disable 50 clrf CM1CON ; disable
47 banksel WDTCON 51 banksel WDTCON
48 movlw b'10000000' 52 movlw b'10000000'
49 movwf WDTCON ; Setup Watchdog 53 movwf WDTCON ; setup watchdog
50 54
51 ; I/O Ports 55 ; I/O Ports
52 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. 56 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
53 57
54 clrf REFOCON ; No reference oscillator active on REFO pin 58 clrf REFOCON ; no reference oscillator active on REFO pin
55 clrf ODCON1 ; Disable Open Drain capability 59 clrf ODCON1 ; disable open drain capability
56 clrf ODCON2 ; Disable Open Drain capability 60 clrf ODCON2 ; disable open drain capability
57 clrf ODCON3 ; Disable Open Drain capability 61 clrf ODCON3 ; disable open drain capability
58 clrf CM2CON ; Disable 62 clrf CM2CON ; disable
59 clrf CM3CON ; Disable 63 clrf CM3CON ; disable
60 64
61 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital. 65 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital
62 movwf ANCON0 66 movwf ANCON0
63 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in 67 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input
64 movwf ANCON1 68 movwf ANCON1
65 movlw b'00000010' ; ANSEL, AN17 -> Analog input 69 movlw b'00000010' ; ANSEL, AN17 -> Analog input
66 movwf ANCON2 70 movwf ANCON2
67 71
68 banksel common 72 banksel common
69 73
70 ; movlw b'00000000' ; 1= Input -> Data TFT_high 74 ; movlw b'00000000' ; 1= input -> Data TFT_high
71 clrf TRISA 75 clrf TRISA
72 ; movlw b'00000000' ; Init port 76 ; movlw b'00000000' ; init port
73 clrf PORTA 77 clrf PORTA
74 78
75 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER 79 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER
76 movwf TRISB 80 movwf TRISB
77 movlw b'00101000' ; Init port 81 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX
78 movwf PORTB 82 movwf PORTB
79 83
80 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 84 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
81 movwf TRISC 85 movwf TRISC
82 ; movlw b'00000000' ; Init port 86 ; movlw b'00000000' ; init port
83 clrf PORTC 87 clrf PORTC
84 88
85 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET 89 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
86 movwf TRISD 90 movwf TRISD
87 ; movlw b'00000000' ; Init port 91 ; movlw b'00000000' ; init port
88 clrf PORTD 92 clrf PORTD
89 93
90 ; movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware 94 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware
91 clrf TRISE 95 clrf TRISE
92 movlw b'00110001' ; Init port 96 movlw b'00110001' ; init port
93 movwf PORTE 97 movwf PORTE
94 98
95 movlw b'01111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog 99 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
96 movwf TRISF 100 movwf TRISF
97 ; movlw b'00000000' ; Init port 101 ; movlw b'00000000' ; init port
98 clrf PORTF 102 clrf PORTF
99 103
100 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET 104 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
101 movwf TRISG 105 movwf TRISG
102 movlw b'00000001' ; Init port 106 movlw b'00000001' ; init port
103 movwf PORTG 107 movwf PORTG
104 108
105 ; movlw b'00000000' ; 1= Input -> Data TFT_low 109 ; movlw b'00000000' ; 1= input -> Data TFT_low
106 clrf TRISH 110 clrf TRISH
107 ; movlw b'00000000' ; Init port 111 ; movlw b'00000000' ; init port
108 clrf PORTH 112 clrf PORTH
109 113
110 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 114 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
111 movwf TRISJ 115 movwf TRISJ
112 movlw b'00100000' ; Init port 116 movlw b'00100000' ; init port
113 movwf PORTJ 117 movwf PORTJ
114 118
115 119
116 ; Timer 0 120 ; Timer 0
117 movlw b'00000001' ; Timer0 with 1:4 prescaler 121 movlw b'00000001' ; timer0 with 1:4 prescaler
118 movwf T0CON 122 movwf T0CON
119 123
120 ; Timer 1 - Button hold-down timer 124 ; Timer 1 - Button hold-down timer
121 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H 125 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H
122 movwf T1CON 126 movwf T1CON
123 127
124 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. 128 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
125 129
126 ; RTCC 130 ; RTCC
127 movlw 0x55 131 movlw 0x55
128 movwf EECON2 132 movwf EECON2
129 movlw 0xAA 133 movlw 0xAA
130 movwf EECON2 134 movwf EECON2
131 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN 135 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN
132 bsf RTCCFG,RTCPTR1 136 bsf RTCCFG,RTCPTR1
133 bsf RTCCFG,RTCPTR0 137 bsf RTCCFG,RTCPTR0
134 bsf RTCCFG,RTCEN ; Module enable 138 bsf RTCCFG,RTCEN ; module enable
135 bsf RTCCFG,RTCOE ; Output enable 139 bsf RTCCFG,RTCOE ; output enable
136 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J 140 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pullups for Port D, E and J
137 movwf PADCFG1 141 movwf PADCFG1
138 movlw b'11000100' 142 movlw b'11000100'
139 movwf ALRMCFG ; 1 second alarm 143 movwf ALRMCFG ; 1 second alarm
140 movlw d'1' 144 movlw d'1'
141 movwf ALRMRPT ; Alarm repeat counter 145 movwf ALRMRPT ; alarm repeat counter
142 movlw 0x55 146 movlw 0x55
143 movwf EECON2 147 movwf EECON2
144 movlw 0xAA 148 movlw 0xAA
145 movwf EECON2 149 movwf EECON2
146 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN 150 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN
147 151
148 banksel common 152 banksel common
149 ; A/D Converter 153 ; A/D Converter
150 movlw b'00011000' ; power off ADC, select AN6 154 movlw b'00011000' ; power off ADC, select AN6
151 movwf ADCON0 155 movwf ADCON0
152 movlw b'00100000' ; 2.048V Vref+ 156 movlw b'00100000' ; 2.048V Vref+
153 movwf ADCON1 157 movwf ADCON1
154 movlw b'10001101' ; Right justified 158 movlw b'10001101' ; right aligned
155 movwf ADCON2 159 movwf ADCON2
156 160
157 161
158 ;init serial port1 (TRISC6/7) 162 ; init serial port1 (TRISC6/7)
159 movlw b'00001000' ; BRG16=1 163 movlw b'00001000' ; BRG16=1
160 movwf BAUDCON1 164 movwf BAUDCON1
161 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD) 165 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error to 115200 BAUD)
162 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD) 166 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error to 19200 BAUD)
163 clrf SPBRGH1 ; 167 clrf SPBRGH1 ;
164 168
165 clrf RCSTA1 169 clrf RCSTA1
166 clrf TXSTA1 ; UART disable 170 clrf TXSTA1 ; UART disable
167 bcf PORTC,6 ; TX hard to GND 171 bcf PORTC,6 ; TX hard to GND
168 172
169 ;init serial port2 (TRISG2) 173 ; init serial port2 (TRISG2)
170 banksel BAUDCON2 174 banksel BAUDCON2
171 movlw b'00100000' ; BRG16=0 ; inverted for IR 175 movlw b'00100000' ; BRG16=0 ; inverted for IR
172 movwf BAUDCON2 176 movwf BAUDCON2
173 movlw b'00100000' ; BRGH=0, SYNC=0 177 movlw b'00100000' ; BRGH=0, SYNC=0
174 movwf TXSTA2 178 movwf TXSTA2
175 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz 179 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
176 movwf SPBRG2 180 movwf SPBRG2
177 clrf SPBRGH2 181 clrf SPBRGH2
178 movlw b'10010000' 182 movlw b'10010000'
179 movwf RCSTA2 183 movwf RCSTA2
180 banksel common 184 banksel common
181 185
182 ; Timer3 for IR-RX Timeout 186 ; Timer3 for IR-RX Timeout
183 clrf T3GCON ; Reset Timer3 Gate Control register 187 clrf T3GCON ; reset Timer3 gate control register
184 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced 188 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced
185 ; 30,51757813µs/bit in TMR3L:TMR3H 189 ; 30,51757813µs/bit in TMR3L:TMR3H
186 movwf T3CON 190 movwf T3CON
187 191
188 ; SPI Module(s) 192 ; SPI Module(s)
189 ; SPI2: External Flash 193 ; SPI2: External Flash
194 ; ->0,25MHz Bit clock @1MHz mode (Eco) 198 ; ->0,25MHz Bit clock @1MHz mode (Eco)
195 ; -> 4MHz Bit clock @16MHz mode (Normal) 199 ; -> 4MHz Bit clock @16MHz mode (Normal)
196 ; -> 16MHz Bit clock @64MHz mode (Fastest) 200 ; -> 16MHz Bit clock @64MHz mode (Fastest)
197 201
198 ; MSSP1 Module: I2C Master 202 ; MSSP1 Module: I2C Master
199 movlw b'00101000' ; I2C Master Mode 203 movlw b'00101000' ; I2C master mode
200 movwf SSP1CON1 204 movwf SSP1CON1
201 ; movlw b'00000000' 205 ; movlw b'00000000'
202 clrf SSP1CON2 206 clrf SSP1CON2
203 movlw 0x27 207 movlw 0x27
204 movwf SSP1ADD ; 100kHz @ 16MHz Fosc 208 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
205 209
206 ; PWM Module(s) 210 ; PWM Module(s)
207 ; PWM1 for LED dimming 211 ; PWM1 for LED dimming
208 movlw b'00001100' 212 movlw b'00001100'
209 movwf CCP1CON 213 movwf CCP1CON
210 movlw b'00000001' 214 movlw b'00000001'
211 movwf PSTR1CON ; Pulse steering disabled 215 movwf PSTR1CON ; pulse steering disabled
212 movlw d'255' 216 movlw d'255'
213 movwf PR2 ; Period 217 movwf PR2 ; period
214 ; 255 is max brightness (300mW) 218 ; 255 is max brightness (300 mW)
215 clrf CCPR1L ; Duty cycle 219 clrf CCPR1L ; duty cycle
216 clrf CCPR1H ; Duty cycle 220 clrf CCPR1H ; duty cycle
217 movlw T2CON_NORMAL 221 movlw T2CON_NORMAL
218 movwf T2CON 222 movwf T2CON
219 223
220 ; Timer5 for ISR-independent wait routines 224 ; Timer5 for ISR-independent wait routines
221 clrf T5GCON ; Reset Timer5 Gate Control register 225 clrf T5GCON ; reset Timer5 gate control register
222 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced 226 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced
223 ; 30,51757813µs/bit in TMR5L:TMR5H 227 ; 30,51757813µs/bit in TMR5L:TMR5H
224 movwf T5CON 228 movwf T5CON
225 229
226 ; Timer7 for 62,5ms Interrupt (Sensor states) 230 ; Timer7 for 62,5ms Interrupt (Sensor states)
227 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. 231 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
228 clrf T7GCON ; Reset Timer7 Gate Control register 232 clrf T7GCON ; reset Timer7 gate control register
229 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced 233 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced
230 movwf T7CON 234 movwf T7CON
231 clrf TMR7L 235 clrf TMR7L
232 movlw .248 236 movlw .248
233 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms 237 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
234 238
235 banksel common 239 banksel common
236 ; Interrupts 240 ; Interrupts
237 movlw b'11010000' 241 movlw b'11010000'
238 movwf INTCON 242 movwf INTCON
239 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled 243 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled
240 movwf INTCON2 244 movwf INTCON2
241 movlw b'00000000' 245 movlw b'00000000'
242 movwf INTCON3 246 movwf INTCON3
243 movlw b'00000001' ; Bit0: TMR1 247 movlw b'00000001' ; Bit0: TMR1
244 movwf PIE1 248 movwf PIE1
245 movlw b'00000010' ; Bit1: TMR3 249 movlw b'00000010' ; Bit1: TMR3
246 movwf PIE2 250 movwf PIE2
247 movlw b'00000000' ; Bit1: TMR5 251 movlw b'00000000' ; Bit1: TMR5
248 movwf PIE5 252 movwf PIE5
249 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 253 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
250 movwf PIE3 254 movwf PIE3
251 movlw b'00001000' ; Bit3: TMR7 255 movlw b'00001000' ; Bit3: TMR7
252 movwf PIE5 256 movwf PIE5
253 257
254 bsf power_sw1 258 bsf power_sw1
255 btfss power_sw1 259 btfss power_sw1
256 bra $-4 260 bra $-4
257 bsf power_sw2 261 bsf power_sw2
258 btfss power_sw2 262 btfss power_sw2
259 bra $-4 263 bra $-4
260 264
261 movlw d'2' 265 movlw d'2'
262 movff WREG,speed_setting ; Normal 266 movff WREG,speed_setting ; normal
263 267
268 bcf active_reset_ostc_rx ; start RX from RESET
264 269
265 return 270 return
266 271
267 ;============================================================================= 272 ;=============================================================================
268 global speed_eco 273 global speed_eco
269 speed_eco: 274 speed_eco:
270 movlw d'1' 275 movlw d'1'
271 movff WREG,speed_setting ; Bank-independent 276 movff WREG,speed_setting ; bank-independent
272 ; Done in ISR 277 ; Done in ISR
273 return 278 return
274 ;============================================================================= 279 ;=============================================================================
275 global speed_normal 280 global speed_normal
276 speed_normal: 281 speed_normal:
277 movlw d'2' 282 movlw d'2'
278 movff WREG,speed_setting ; Bank-independent 283 movff WREG,speed_setting ; bank-independent
279 ; Done in ISR 284 ; Done in ISR
280 return 285 return
281 ;============================================================================= 286 ;=============================================================================
282 global speed_fastest 287 global speed_fastest
283 speed_fastest: 288 speed_fastest:
284 movlw d'3' 289 movlw d'3'
285 movff WREG,speed_setting ; Bank-independent 290 movff WREG,speed_setting ; bank-independent
286 ; Done in ISR 291 ; Done in ISR
287 return 292 return
288 ;============================================================================= 293 ;=============================================================================
289 294
290 END 295 END