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comparison src/hwos.asm @ 275:653a3ab08062

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rename into hwOS
author heinrichsweikamp
date Thu, 07 May 2015 13:11:14 +0200
parents src/ostc3.asm@56276a2418f9
children cf929551d31c
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274:9347893b74ce 275:653a3ab08062
1 ;=============================================================================
2 ;
3 ; File hwos.asm
4 ;
5 ; Definition of the hwOS dive computer platform.
6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;=============================================================================
9 ; HISTORY
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
11 ; 2011-06-24 : [MH] Added clock speeds.
12 #include "hwos.inc"
13
14 ;=============================================================================
15 ;----------------------------- CONFIG ---------------------------------
16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
18 CONFIG XINST = OFF ;Code won't excute in extended mode...
19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out
20 CONFIG PLLCFG = OFF
21 CONFIG IESO = OFF ;Disabled
22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400)
23 CONFIG BOREN = ON ;Controlled with SBOREN bit
24 CONFIG BORV = 2 ;2.0V
25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
27 CONFIG WDTPS = 128 ;1:128
28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
31 ;=============================================================================
32 boot CODE
33 global init_ostc
34
35 init_ostc:
36 banksel common ; Bank1
37 ;init oscillator
38 movlw b'01110010'
39 movwf OSCCON ; 16MHz INTOSC
40 movlw b'00001000'
41 movwf OSCCON2 ; Secondary Oscillator running
42 movlw b'00000000'
43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
44 bcf RCON,SBOREN ; Bown-Out off
45 bcf RCON,IPEN ; Priority Interrupts off
46 clrf CM1CON ; Disable
47 banksel WDTCON
48 movlw b'10000000'
49 movwf WDTCON ; Setup Watchdog
50
51 ; I/O Ports
52 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
53
54 clrf REFOCON ; No reference oscillator active on REFO pin
55 clrf ODCON1 ; Disable Open Drain capability
56 clrf ODCON2 ; Disable Open Drain capability
57 clrf ODCON3 ; Disable Open Drain capability
58 clrf CM2CON ; Disable
59 clrf CM3CON ; Disable
60
61 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital.
62 movwf ANCON0
63 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in
64 movwf ANCON1
65 movlw b'00000010' ; ANSEL, AN17 -> Analog input
66 movwf ANCON2
67
68 banksel common
69
70 movlw b'00000000' ; 1= Input -> Data TFT_high
71 movwf TRISA
72 movlw b'00000000' ; Init port
73 movwf PORTA
74
75 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER
76 movwf TRISB
77 movlw b'00101000' ; Init port
78 movwf PORTB
79
80 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
81 movwf TRISC
82 movlw b'00000000' ; Init port
83 movwf PORTC
84
85 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
86 movwf TRISD
87 movlw b'00000000' ; Init port
88 movwf PORTD
89
90 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware
91 movwf TRISE
92 movlw b'00110001' ; Init port
93 movwf PORTE
94
95 movlw b'01111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog
96 movwf TRISF
97 movlw b'00000000' ; Init port
98 movwf PORTF
99
100 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
101 movwf TRISG
102 movlw b'00000001' ; Init port
103 movwf PORTG
104
105 movlw b'00000000' ; 1= Input -> Data TFT_low
106 movwf TRISH
107 movlw b'00000000' ; Init port
108 movwf PORTH
109
110 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
111 movwf TRISJ
112 movlw b'00100000' ; Init port
113 movwf PORTJ
114
115
116 ; Timer 0
117 movlw b'00000001' ; Timer0 with 1:4 prescaler
118 ; movlw b'00001000' ; Timer0 with 1:1 prescaler
119 movwf T0CON
120
121 ; Timer 1 - Button hold-down timer
122 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H
123 movwf T1CON
124
125 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
126
127 ; RTCC
128 movlw 0x55
129 movwf EECON2
130 movlw 0xAA
131 movwf EECON2
132 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
133 bsf RTCCFG,RTCPTR1
134 bsf RTCCFG,RTCPTR0
135 bsf RTCCFG,RTCEN ; Module enable
136 bsf RTCCFG,RTCOE ; Output enable
137 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J
138 movwf PADCFG1
139 movlw b'11000100'
140 movwf ALRMCFG ; 1 second alarm
141 movlw d'1'
142 movwf ALRMRPT ; Alarm repeat counter
143 movlw 0x55
144 movwf EECON2
145 movlw 0xAA
146 movwf EECON2
147 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
148
149 banksel common
150 ; A/D Converter
151 movlw b'00011000' ; power off ADC, select AN6
152 movwf ADCON0
153 movlw b'00100000' ; 2.048V Vref+
154 movwf ADCON1
155 movlw b'10001101' ; Right justified
156 movwf ADCON2
157
158
159 ;init serial port1 (TRISC6/7)
160 movlw b'00001000' ; BRG16=1
161 movwf BAUDCON1
162 ; movlw b'00100100' ; BRGH=1, SYNC=0
163 ; movwf TXSTA1
164 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD)
165 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD)
166 clrf SPBRGH1 ;
167 ; movlw b'10010000'
168 ; movwf RCSTA1
169
170 clrf RCSTA1
171 clrf TXSTA1 ; UART disable
172 bcf PORTC,6 ; TX hard to GND
173
174 ;init serial port2 (TRISG2)
175 banksel BAUDCON2
176 movlw b'00100000' ; BRG16=0 ; inverted for IR
177 movwf BAUDCON2
178 movlw b'00100000' ; BRGH=0, SYNC=0
179 movwf TXSTA2
180 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
181 movwf SPBRG2
182 clrf SPBRGH2
183 movlw b'10010000'
184 movwf RCSTA2
185 banksel common
186
187 ; Timer3 for IR-RX Timeout
188 clrf T3GCON ; Reset Timer3 Gate Control register
189 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
190 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
191 ; 30,51757813µs/bit in TMR3L:TMR3H
192 movwf T3CON
193
194 ; SPI Module(s)
195 ; SPI2: External Flash
196 movlw b'00110000'
197 movwf SSP2CON1
198 movlw b'00000000'
199 movwf SSP2STAT
200 ; ->0,25MHz Bit clock @1MHz mode (Eco)
201 ; -> 4MHz Bit clock @16MHz mode (Normal)
202 ; -> 16MHz Bit clock @64MHz mode (Fastest)
203
204 ; MSSP1 Module: I2C Master
205 movlw b'00101000' ; I2C Master Mode
206 movwf SSP1CON1
207 movlw b'00000000'
208 movwf SSP1CON2
209 movlw 0x27
210 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
211
212 ; PWM Module(s)
213 ; PWM1 for LED dimming
214 movlw b'00001100'
215 movwf CCP1CON
216 movlw b'00000001'
217 movwf PSTR1CON ; Pulse steering disabled
218 movlw d'255'
219 movwf PR2 ; Period
220 ; 255 is max brightness (300mW)
221 clrf CCPR1L ; Duty cycle
222 clrf CCPR1H ; Duty cycle
223 movlw T2CON_NORMAL
224 movwf T2CON
225
226 ; Timer5 for ISR-independent wait routines
227 clrf T5GCON ; Reset Timer5 Gate Control register
228 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
229 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
230 ; 30,51757813µs/bit in TMR5L:TMR5H
231 movwf T5CON
232
233 ; Timer7 for 62,5ms Interrupt (Sensor states)
234 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
235 clrf T7GCON ; Reset Timer7 Gate Control register
236 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
237 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
238 movwf T7CON
239 clrf TMR7L
240 movlw .248
241 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
242
243 banksel common
244 ; Interrupts
245 movlw b'11010000'
246 movwf INTCON
247 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled
248 movwf INTCON2
249 movlw b'00000000'
250 movwf INTCON3
251 movlw b'00000001' ; Bit0: TMR1
252 movwf PIE1
253 movlw b'00000010' ; Bit1: TMR3
254 movwf PIE2
255 movlw b'00000000' ; Bit1: TMR5
256 movwf PIE5
257 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
258 movwf PIE3
259 movlw b'00001000' ; Bit3: TMR7
260 movwf PIE5
261
262 bsf power_sw1
263 btfss power_sw1
264 bra $-4
265 bsf power_sw2
266 btfss power_sw2
267 bra $-4
268
269 movlw d'2'
270 movwf speed_setting ; Normal
271
272
273 return
274
275 ;=============================================================================
276 global speed_eco
277 speed_eco:
278 movlw d'1'
279 movff WREG,speed_setting ; Bank-independent
280 ; Done in ISR
281 return
282 ;=============================================================================
283 global speed_normal
284 speed_normal:
285 movlw d'2'
286 movff WREG,speed_setting ; Bank-independent
287 ; Done in ISR
288 return
289 ;=============================================================================
290 global speed_fastest
291 speed_fastest:
292 movlw d'3'
293 movff WREG,speed_setting ; Bank-independent
294 ; Done in ISR
295 return
296 ;=============================================================================
297
298 END