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comparison src/mcp.asm @ 98:24b3fd59e61f
add event "bailout" in profile
author | heinrichsweikamp |
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date | Thu, 01 May 2014 21:16:31 +0200 (2014-05-01) |
parents | fcaf94b913db |
children | 653a3ab08062 |
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97:53a99a2dc6a1 | 98:24b3fd59e61f |
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11 | 11 |
12 | 12 |
13 #include "ostc3.inc" | 13 #include "ostc3.inc" |
14 #include "wait.inc" | 14 #include "wait.inc" |
15 | 15 |
16 mcp_writebyte_1st macro char | |
17 movlw char | |
18 rcall mcp_write_one_byte | |
19 endm | |
20 | |
21 mcp_writebyte_2nd macro char | |
22 movlw char | |
23 rcall mcp_write_one_byte2 | |
24 endm | |
25 | |
26 ; Writes mcp_temp+0 to config reg | |
27 mcp_write_config macro char | |
28 movlw char | |
29 rcall mcp_write_config_reg | |
30 endm | |
31 | |
32 mcp code | 16 mcp code |
33 | |
34 mcp_write_one_byte: | |
35 movwf mcp_temp+0 ; save one byte | |
36 bcf TRISG,0 ; CLK output | |
37 nop | |
38 bcf mcp_clk ; clk=0 | |
39 bsf mcp_ncs ; cs=1 | |
40 nop | |
41 bcf mcp_ncs ; cs=0 | |
42 bcf TRISB,3 ; mcp_lf_data output | |
43 movlw .8 | |
44 movwf mcp_temp+1 ; Bit counter | |
45 mcp_write_one_byte_loop: | |
46 btfss mcp_temp+0,7 | |
47 bcf mcp_lf_data | |
48 btfsc mcp_temp+0,7 | |
49 bsf mcp_lf_data | |
50 bsf mcp_clk ; clk=1 | |
51 rlncf mcp_temp+0,F ; shift byte left no carry | |
52 bcf mcp_clk ; clk=0 | |
53 decfsz mcp_temp+1,F ; 8Bit done? | |
54 bra mcp_write_one_byte_loop ; Not yet... | |
55 return | |
56 | |
57 mcp_write_one_byte2: | |
58 movwf mcp_temp+0 ; save one byte | |
59 movlw .8 | |
60 movwf mcp_temp+1 ; Bit counter | |
61 mcp_write_one_byte_loop2: | |
62 btfss mcp_temp+0,7 | |
63 bcf mcp_lf_data | |
64 btfsc mcp_temp+0,7 | |
65 bsf mcp_lf_data | |
66 bsf mcp_clk ; clk=1 | |
67 rlncf mcp_temp+0,F ; shift byte left no carry | |
68 bcf mcp_clk ; clk=0 | |
69 decfsz mcp_temp+1,F ; 8Bit done? | |
70 bra mcp_write_one_byte_loop2; Not yet... | |
71 bsf TRISB,3 ; mcp_lf_data input again | |
72 bsf mcp_ncs ; cs=1 | |
73 bsf TRISG,0 ; CLK input | |
74 return | |
75 | |
76 mcp_readbyte: | |
77 bcf TRISG,0 ; CLK output | |
78 nop | |
79 bcf mcp_clk ; clk=0 | |
80 bcf mcp_ncs ; cs=0 | |
81 movlw .7 | |
82 movwf mcp_temp+1 ; Bit counter | |
83 nop | |
84 nop | |
85 mcp_readloop: | |
86 bsf mcp_clk ; clk=1 | |
87 bcf mcp_clk ; clk=0 | |
88 decfsz mcp_temp+1,F ; 7 Bit done? | |
89 bra mcp_readloop ; Not yet... | |
90 | |
91 movlw .8 | |
92 movwf mcp_temp+1 ; Bit counter | |
93 mcp_readloop2: | |
94 bsf mcp_clk ; clk=1 | |
95 bcf mcp_clk ; clk=0 | |
96 btfss mcp_lf_data | |
97 bcf mcp_temp+0,7 | |
98 btfsc mcp_lf_data | |
99 bsf mcp_temp+0,7 | |
100 rlncf mcp_temp+0 ; MSB first | |
101 decfsz mcp_temp+1,F ; 8 Bit done? | |
102 bra mcp_readloop2 ; Not yet... | |
103 | |
104 ; Dummy clk for parity bit | |
105 bsf mcp_clk ; clk=1 | |
106 nop | |
107 bcf mcp_clk ; clk=0 | |
108 bsf mcp_ncs ; cs=1 | |
109 bsf TRISG,0 ; CLK input | |
110 return | |
111 | |
112 mcp_write_config_reg: ; Writes mcp_temp+0 to config #WREG | |
113 movwf mcp_temp+2 ; Save config# | |
114 bcf TRISG,0 ; CLK output | |
115 clrf mcp_temp+3 ; for parity | |
116 bcf mcp_clk ; clk=0 | |
117 bsf mcp_ncs ; cs=1 | |
118 nop | |
119 bcf mcp_ncs ; cs=0 | |
120 bcf TRISB,3 ; mcp_lf_data output | |
121 bsf mcp_lf_data | |
122 bsf mcp_clk ; clk=1 | |
123 bcf mcp_clk ; clk=0 | |
124 bsf mcp_clk ; clk=1 | |
125 bcf mcp_clk ; clk=0 | |
126 bsf mcp_clk ; clk=1 | |
127 bcf mcp_clk ; clk=0 ; Write command done. | |
128 | |
129 ; Now, 4Bit register address | |
130 movlw .4 | |
131 movwf mcp_temp+1 ; Bit counter | |
132 mcp_write_config_reg1: | |
133 btfss mcp_temp+2,3 | |
134 bcf mcp_lf_data | |
135 btfsc mcp_temp+2,3 | |
136 bsf mcp_lf_data | |
137 bsf mcp_clk ; clk=1 | |
138 rlncf mcp_temp+2,F ; shift byte left no carry | |
139 bcf mcp_clk ; clk=0 | |
140 decfsz mcp_temp+1,F ; 4Bit done? | |
141 bra mcp_write_config_reg1 ; Not yet... | |
142 | |
143 ; 8Bit data | |
144 movlw .8 | |
145 movwf mcp_temp+1 ; Bit counter | |
146 mcp_write_config_reg2: | |
147 btfss mcp_temp+0,7 | |
148 bcf mcp_lf_data | |
149 btfsc mcp_temp+0,7 | |
150 bsf mcp_lf_data | |
151 btfsc mcp_temp+0,7 | |
152 incf mcp_temp+3,F ; count 1's... | |
153 bsf mcp_clk ; clk=1 | |
154 rlncf mcp_temp+0,F ; shift byte left no carry | |
155 bcf mcp_clk ; clk=0 | |
156 decfsz mcp_temp+1,F ; 8Bit done? | |
157 bra mcp_write_config_reg2 ; Not yet... | |
158 | |
159 ; 1bit parity | |
160 btfss mcp_temp+3,0 | |
161 bsf mcp_lf_data ; Set row parity bit | |
162 btfsc mcp_temp+3,0 | |
163 bcf mcp_lf_data ; clear row parity bit | |
164 bsf mcp_clk ; clk=1 | |
165 bcf mcp_clk ; clk=0 ; Parity bit done. | |
166 | |
167 bsf TRISB,3 ; mcp_lf_data input again | |
168 bsf mcp_ncs ; cs=1 | |
169 bsf TRISG,0 ; CLK input | |
170 return | |
171 | |
172 global mcp_reset | |
173 mcp_reset: ; reset RX chip# (Normal mode) | |
174 ; Make sure row parity bit is correct | |
175 ; yyyaaaa01234567P | |
176 ; yyy: Command | |
177 ; aaaa: Address | |
178 ; 0-7: Data | |
179 ; P: Parity bit. Set/Clear that 0-7+P are odd number of ones | |
180 ; Current config: | |
181 banksel buffer | |
182 movlw b'10100100' ; Config0: LCZ disabled, Wakeup => High = 2ms, Low = 2ms | |
183 movwf buffer+0 | |
184 movlw b'00000000' ; Config1: +20pF LCX Normal mode | |
185 ; movlw b'01000000' ; Config1: +20pF LCX carrier out mode | |
186 movwf buffer+1 | |
187 movlw b'00000000' ; Config2: +25pF LCY | |
188 movwf buffer+2 | |
189 movlw b'00000000' ; Config3 | |
190 movwf buffer+3 | |
191 movlw b'00000000' ; Config4 | |
192 movwf buffer+4 | |
193 ; movlw b'00001111' ; Config5 33% | |
194 ; movlw b'00101111' ; Config5 14% | |
195 movlw b'10011111' ; Config5 60% | |
196 movwf buffer+5 | |
197 bra mcp_reset_common | |
198 | |
199 global mcp_reset_rssi | |
200 mcp_reset_rssi: ; reset RX chip# for RSSI mode | |
201 ; Make sure row parity bit is correct | |
202 ; yyyaaaa01234567P | |
203 ; yyy: Command | |
204 ; aaaa: Address | |
205 ; 0-7: Data | |
206 ; P: Parity bit. Set/Clear that 0-7+P are odd number of ones | |
207 ; Current config: | |
208 banksel buffer | |
209 movlw b'10101000' ; Config0: LCZ disabled, Wakeup => High = 2ms, Low = 2ms | |
210 movwf buffer+0 | |
211 movlw b'10000000' ; Config1: +20pF LCX and RSSI Mode | |
212 movwf buffer+1 | |
213 movlw b'00000000' ; Config2: +25pF LCY | |
214 movwf buffer+2 | |
215 movlw b'00000000' ; Config3 | |
216 movwf buffer+3 | |
217 movlw b'00000000' ; Config4 | |
218 movwf buffer+4 | |
219 movlw b'11010000' ; Config5 60% | |
220 movwf buffer+5 | |
221 mcp_reset_common: | |
222 banksel TRISB | |
223 bcf TRISB,2 | |
224 bcf mcp_ncs ; CS=1 | |
225 nop | |
226 bsf mcp_power ; Power-up | |
227 nop | |
228 btfss mcp_power | |
229 bra mcp_reset_common | |
230 WAITMS .10 | |
231 ; Compute column parity byte | |
232 banksel buffer | |
233 movf buffer+0,W | |
234 xorwf buffer+1,W | |
235 xorwf buffer+2,W | |
236 xorwf buffer+3,W | |
237 xorwf buffer+4,W | |
238 xorwf buffer+5,W | |
239 xorlw 0xFF | |
240 movwf buffer+6 ; <- Column parity byte | |
241 banksel mcp_temp+0 | |
242 | |
243 mcp_writebyte_1st b'10100000' ; Reset Command | |
244 mcp_writebyte_2nd b'00000000' ; Dummy byte | |
245 | |
246 mcp_writebyte_1st b'00100000' ; Clamp off | |
247 mcp_writebyte_2nd b'00000000' ; Dummy byte | |
248 | |
249 movff buffer+0,mcp_temp+0 ; Data byte | |
250 mcp_write_config .0 | |
251 movff buffer+1,mcp_temp+0 ; Data byte | |
252 mcp_write_config .1 | |
253 movff buffer+2,mcp_temp+0 ; Data byte | |
254 mcp_write_config .2 | |
255 movff buffer+3,mcp_temp+0 ; Data byte | |
256 mcp_write_config .3 | |
257 movff buffer+4,mcp_temp+0 ; Data byte | |
258 mcp_write_config .4 | |
259 movff buffer+5,mcp_temp+0 ; Data byte | |
260 mcp_write_config .5 | |
261 movff buffer+6,mcp_temp+0 ; Data byte (Column parity byte) | |
262 mcp_write_config .6 | |
263 | |
264 ; mcp_writebyte_1st b'11000000' ; Read from Config0 | |
265 ; mcp_writebyte_2nd b'00000000' ; Dummy clks + Odd Parity Bit (Bit0) | |
266 ; call mcp_readbyte ; read into mcp_temp+0 | |
267 bsf INTCON3,INT3IE ; Enable INT3 | |
268 bsf INTCON2,INTEDG3 ; INT3 on rising edge | |
269 | |
270 ; Setup Timer 0 | |
271 movlw TMR0H_VALUE | |
272 movwf TMR0H | |
273 bcf INTCON,TMR0IF ; Clear flag | |
274 clrf TMR0L | |
275 return | |
276 | 17 |
277 global mcp_sleep | 18 global mcp_sleep |
278 mcp_sleep: | 19 mcp_sleep: |
279 bcf INTCON3,INT3IE ; Disable INT3 | 20 bcf INTCON3,INT3IE ; Disable INT3 |
280 bcf mcp_power ; RX off | 21 bcf mcp_power ; RX off |