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comparison src/hwos.asm @ 629:237931377539

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3.07 stable release
author heinrichsweikamp
date Fri, 29 Nov 2019 18:48:11 +0100
parents cd58f7fc86db
children 4cd81bdbf15c
comparison
equal deleted inserted replaced
628:cd58f7fc86db 629:237931377539
1 ;============================================================================= 1 ;=============================================================================
2 ; 2 ;
3 ; File hwos.asm combined next generation V3.03.7 3 ; File hwos.asm combined next generation V3.06.1
4 ; 4 ;
5 ; Definition of the hwOS dive computer platform. 5 ; Definition of the hwOS dive computer platform.
6 ; 6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;============================================================================= 8 ;=============================================================================
291 291
292 292
293 ; Timer 3 for IR-RX Timeout 293 ; Timer 3 for IR-RX Timeout
294 IFDEF _external_sensor 294 IFDEF _external_sensor
295 clrf T3GCON ; reset Timer3 gate control register 295 clrf T3GCON ; reset Timer3 gate control register
296 movlw b'10001001' ; synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, 296 movlw b'10001101' ; not synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
297 ; incrementing by 1 bit each 30.51757813 µs 297 ; incrementing by 1 bit each 30.51757813 µs
298 movwf T3CON 298 movwf T3CON
299 ENDIF 299 ENDIF
300 300
301 301
334 movwf T2CON 334 movwf T2CON
335 335
336 336
337 ; Timer 5 for ISR-independent wait routines 337 ; Timer 5 for ISR-independent wait routines
338 clrf T5GCON ; reset Timer5 gate control register 338 clrf T5GCON ; reset Timer5 gate control register
339 movlw b'10001011' ; synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, 339 movlw b'10001111' ; not synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
340 movwf T5CON ; incrementing by 1 bit each 30.51757813 µs 340 movwf T5CON ; incrementing by 1 bit each 30.51757813 µs
341 341
342 342
343 banksel 0xF16 ; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM 343 banksel 0xF16 ; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM
344 344
345 ; Timer 7 for 62.5 ms Interrupt (sensor states) 345 ; Timer 7 for 62.5 ms Interrupt (sensor states)
346 clrf T7GCON ; reset Timer7 gate control register 346 clrf T7GCON ; reset Timer7 gate control register
347 movlw b'10001001' ; 1:1 prescaler -> 2 seconds @ 32768 Hz, synced 347 movlw b'10001101' ; 1:1 prescaler -> 2 seconds @ 32768 Hz, not synced
348 movwf T7CON 348 movwf T7CON
349 clrf TMR7L 349 clrf TMR7L
350 movlw .248 350 movlw .248
351 movwf TMR7H ; -> rollover after 2048 cycles -> 62.5 ms 351 movwf TMR7H ; -> rollover after 2048 cycles -> 62.5 ms
352 352
385 movwf PIE1 385 movwf PIE1
386 movlw b'00000010' ; Bit1: TMR3 386 movlw b'00000010' ; Bit1: TMR3
387 movwf PIE2 387 movwf PIE2
388 movlw b'00000000' ; Bit1: TMR5 388 movlw b'00000000' ; Bit1: TMR5
389 movwf PIE5 389 movwf PIE5
390 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 390 movlw b'00000001' ; Bit0: RTCC, Bit5: UART2 (Default OFF)
391 movwf PIE3 391 movwf PIE3
392 movlw b'00001000' ; Bit3: TMR7 392 movlw b'00001000' ; Bit3: TMR7
393 movwf PIE5 393 movwf PIE5
394 394
395 bcf active_reset_ostc_rx ; release RESET from RX circuitry 395 bcf active_reset_ostc_rx ; release RESET from RX circuitry