Mercurial > public > hwos_code

comparison src/ostc3.asm @ 0:11d4fc797f74

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
init
author heinrichsweikamp
date Wed, 24 Apr 2013 19:22:45 +0200
parents
children e4e662746c02
comparison
equal deleted inserted replaced
-1:000000000000 0:11d4fc797f74
1 ;=============================================================================
2 ;
3 ; File ostc3.asm
4 ;
5 ; Definition of the ostc3 dive computer platform.
6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;=============================================================================
9 ; HISTORY
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
11 ; 2011-06-24 : [MH] Added clock speeds.
12 #include "ostc3.inc"
13
14 ;=============================================================================
15 ;
16 ;----------------------------- CONFIG ---------------------------------
17 ; CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
18 ; CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
19 ; CONFIG XINST = OFF ;Code won't excute in extended mode...
20 ; CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out
21 ; CONFIG PLLCFG = OFF
22 ; CONFIG IESO = OFF ;Disabled
23 ; CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400)
24 ; CONFIG BOREN = ON ;Controlled with SBOREN bit
25 ; CONFIG BORV = 2 ;2.0V
26 ; CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
27 ; CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
28 ; CONFIG WDTPS = 128 ;1:128
29 ; CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
30 ; CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
31 ; CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
32 ;=============================================================================
33 boot CODE
34 global init_ostc3
35
36 init_ostc3:
37 banksel common ; Bank1
38 ;init oscillator
39 movlw b'01110010'
40 movwf OSCCON ; 16MHz INTOSC
41 movlw b'00001000'
42 movwf OSCCON2 ; Secondary Oscillator running
43 movlw b'00000000'
44 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
45 bcf RCON,SBOREN ; Bown-Out off
46 bcf RCON,IPEN ; Priority Interrupts off
47
48 ; I/O Ports
49 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
50
51 clrf REFOCON ; No reference oscillator active on REFO pin
52 clrf ODCON1 ; Disable Open Drain capability
53 clrf ODCON2 ; Disable Open Drain capability
54 clrf ODCON3 ; Disable Open Drain capability
55
56 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital.
57 movwf ANCON0
58 movlw b'00000000' ; ANSEL
59 movwf ANCON1
60 movlw b'00000010' ; ANSEL, AN17 -> Analog input
61 movwf ANCON2
62
63 banksel common
64
65 movlw b'00000000' ; 1= Input -> Data TFT_high
66 movwf TRISA
67 movlw b'00000000' ; Init port
68 movwf PORTA
69
70 movlw b'00001011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> lf_data, RB4 -> LED_green, RB5 -> /TFT_POWER
71 movwf TRISB
72 movlw b'00100000' ; Init port
73 movwf PORTB
74
75 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
76 movwf TRISC
77 movlw b'00000000' ; Init port
78 movwf PORTC
79
80 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
81 movwf TRISD
82 movlw b'00000000' ; Init port
83 movwf PORTD
84
85 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1,
86 movwf TRISE
87 movlw b'00010000' ; Init port
88 movwf PORTE
89
90 movlw b'00000110' ; 1= Input, (RF1, RF2) -> Analog
91 movwf TRISF
92 movlw b'00000000' ; Init port
93 movwf PORTF
94
95 movlw b'00001111' ; 1= Input, <7:6> not implemented, RG0 -> SCLK_MCP, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
96 movwf TRISG
97 movlw b'00000000' ; Init port
98 movwf PORTG
99
100 movlw b'00000000' ; 1= Input -> Data TFT_low
101 movwf TRISH
102 movlw b'00000000' ; Init port
103 movwf PORTH
104
105 movlw b'10010000' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
106 movwf TRISJ
107 movlw b'00100000' ; Init port
108 movwf PORTJ
109
110
111 ; Timer 0
112 ; movlw b'00000000' ; Timer0 with 1:2 prescaler
113 movlw b'00001000' ; Timer0 with 1:1 prescaler
114 movwf T0CON
115
116 ; Timer 1 - Button hold-down timer
117 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H
118 movwf T1CON
119
120 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
121
122 ; RTCC
123 movlw 0x55
124 movwf EECON2
125 movlw 0xAA
126 movwf EECON2
127 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
128 bsf RTCCFG,RTCPTR1
129 bsf RTCCFG,RTCPTR0
130 bsf RTCCFG,RTCEN ; Module enable
131 bsf RTCCFG,RTCOE ; Output enable
132 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J
133 movwf PADCFG1
134 movlw b'11000100'
135 movwf ALRMCFG ; 1 second alarm
136 movlw d'1'
137 movwf ALRMRPT ; Alarm repeat counter
138 movlw 0x55
139 movwf EECON2
140 movlw 0xAA
141 movwf EECON2
142 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
143
144 banksel common
145 ; A/D Converter
146 movlw b'00011000' ; power off ADC, select AN6
147 movwf ADCON0
148 movlw b'00100000' ; 2.048V Vref+
149 movwf ADCON1
150 movlw b'10001101' ; Right justified
151 movwf ADCON2
152
153
154 ;init serial port1 (TRISC6/7)
155 movlw b'00001000' ; BRG16=1
156 movwf BAUDCON1
157 movlw b'00100100' ; BRGH=1, SYNC=0
158 movwf TXSTA1
159 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD)
160 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD)
161 clrf SPBRGH1 ;
162 movlw b'10010000'
163 movwf RCSTA1
164
165 ;init serial port2 (TRISG2)
166 banksel BAUDCON2
167 movlw b'00100000' ; BRG16=0
168 movwf BAUDCON2
169 movlw b'00100000' ; BRGH=0, SYNC=0
170 movwf TXSTA2
171 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
172 movwf SPBRG2
173 clrf SPBRGH2
174 movlw b'10010000'
175 movwf RCSTA2
176 banksel common
177
178 ; Timer3 for IR-RX Timeout
179 clrf T3GCON ; Reset Timer3 Gate Control register
180 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
181 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
182 ; 30,51757813µs/bit in TMR3L:TMR3H
183 movwf T3CON
184
185 ; SPI Module(s)
186 ; SPI2: External Flash
187 movlw b'00110000'
188 movwf SSP2CON1
189 movlw b'00000000'
190 movwf SSP2STAT
191 ; ->0,25MHz Bit clock @1MHz mode (Eco)
192 ; -> 4MHz Bit clock @16MHz mode (Normal)
193 ; -> 16MHz Bit clock @64MHz mode (Fastest)
194
195 ; MSSP1 Module: I2C Master
196 movlw b'00101000' ; I2C Master Mode
197 movwf SSP1CON1
198 movlw b'00000000'
199 movwf SSP1CON2
200 movlw 0x27
201 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
202
203 ; PWM Module(s)
204 ; PWM1 for LED dimming
205 movlw b'00001100'
206 movwf CCP1CON
207 movlw b'00000001'
208 movwf PSTR1CON ; Pulse steering disabled
209 movlw d'255'
210 movwf PR2 ; Period
211 ; 255 is max brightness (300mW)
212 clrf CCPR1L ; Duty cycle
213 clrf CCPR1H ; Duty cycle
214 movlw T2CON_NORMAL
215 movwf T2CON
216
217 ; Timer5 for ISR-independent wait routines
218 clrf T5GCON ; Reset Timer5 Gate Control register
219 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
220 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
221 ; 30,51757813µs/bit in TMR5L:TMR5H
222 movwf T5CON
223
224 ; Timer7 for 62,5ms Interrupt (Sensor states)
225 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
226 clrf T7GCON ; Reset Timer7 Gate Control register
227 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
228 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
229 movwf T7CON
230 clrf TMR7L
231 movlw .248
232 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
233
234 banksel common
235 ; Interrupts
236 movlw b'11110000'
237 movwf INTCON
238 movlw b'10000000' ; BIT7=1: Pullup for PORTB disabled
239 movwf INTCON2
240 movlw b'00001000'
241 movwf INTCON3
242 movlw b'00000001' ; Bit0: TMR1
243 movwf PIE1
244 movlw b'00000010' ; Bit1: TMR3
245 movwf PIE2
246 movlw b'00000000' ; Bit1: TMR5
247 movwf PIE5
248 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
249 movwf PIE3
250 movlw b'00001000' ; Bit3: TMR7
251 movwf PIE5
252
253 bsf power_sw1
254 bsf power_sw2
255
256 return
257
258 ;=============================================================================
259 global speed_eco
260 speed_eco:
261 movlw d'1'
262 movff WREG,speed_setting ; Bank-independent
263 ; Done in ISR
264 return
265 ;=============================================================================
266 global speed_normal
267 speed_normal:
268 movlw d'2'
269 movff WREG,speed_setting ; Bank-independent
270 ; Done in ISR
271 return
272 ;=============================================================================
273 global speed_fastest
274 speed_fastest:
275 movlw d'3'
276 movff WREG,speed_setting ; Bank-independent
277 ; Done in ISR
278 return
279 ;=============================================================================
280
281 END