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annotate src/ostc3.asm @ 236:e2ea74646127

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configure hardware_flag byte
author heinrichsweikamp
date Wed, 25 Feb 2015 22:19:30 +0100
parents 56276a2418f9
children
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1 ;=============================================================================
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2 ;
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3 ; File ostc3.asm
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4 ;
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5 ; Definition of the ostc3 dive computer platform.
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
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11 ; 2011-06-24 : [MH] Added clock speeds.
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12 #include "ostc3.inc"
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13
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14 ;=============================================================================
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15 ;----------------------------- CONFIG ---------------------------------
1
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16 CONFIG RETEN = OFF ;Disabled - Controlled by SRETEN bit
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17 CONFIG SOSCSEL = HIGH ;High Power SOSC circuit selected
199
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18 CONFIG XINST = OFF ;Code won't excute in extended mode...
1
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19 CONFIG FOSC = INTIO2 ;Internal RC oscillator, no clock-out
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20 CONFIG PLLCFG = OFF
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21 CONFIG IESO = OFF ;Disabled
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22 CONFIG PWRTEN = OFF ;Disabled, because incompatible with ICD3 (Ri-400)
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23 CONFIG BOREN = ON ;Controlled with SBOREN bit
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24 CONFIG BORV = 2 ;2.0V
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25 CONFIG BORPWR = MEDIUM ;BORMV set to medium power level
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26 CONFIG WDTEN = ON ;WDT controlled by SWDTEN bit setting
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27 CONFIG WDTPS = 128 ;1:128
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28 CONFIG RTCOSC = SOSCREF ;RTCC uses SOSC
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29 CONFIG MCLRE = ON ;MCLR Enabled, RG5 Disabled
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30 CONFIG CCP2MX = PORTBE ;RE7-Microcontroller Mode/RB3-All other modes
0
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31 ;=============================================================================
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32 boot CODE
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33 global init_ostc3
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34
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35 init_ostc3:
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36 banksel common ; Bank1
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37 ;init oscillator
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38 movlw b'01110010'
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39 movwf OSCCON ; 16MHz INTOSC
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40 movlw b'00001000'
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41 movwf OSCCON2 ; Secondary Oscillator running
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42 movlw b'00000000'
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43 movwf OSCTUNE ; 4x PLL Disable (Bit6) - only works with 8 or 16MHz (=32 or 64MHz)
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44 bcf RCON,SBOREN ; Bown-Out off
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45 bcf RCON,IPEN ; Priority Interrupts off
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46 clrf CM1CON ; Disable
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47 banksel WDTCON
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48 movlw b'10000000'
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49 movwf WDTCON ; Setup Watchdog
0
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50
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51 ; I/O Ports
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52 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
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53
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54 clrf REFOCON ; No reference oscillator active on REFO pin
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55 clrf ODCON1 ; Disable Open Drain capability
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56 clrf ODCON2 ; Disable Open Drain capability
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57 clrf ODCON3 ; Disable Open Drain capability
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58 clrf CM2CON ; Disable
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59 clrf CM3CON ; Disable
0
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60
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61 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital.
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62 movwf ANCON0
113
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63 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog in
0
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64 movwf ANCON1
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65 movlw b'00000010' ; ANSEL, AN17 -> Analog input
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66 movwf ANCON2
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67
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68 banksel common
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69
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70 movlw b'00000000' ; 1= Input -> Data TFT_high
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71 movwf TRISA
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72 movlw b'00000000' ; Init port
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73 movwf PORTA
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74
113
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75 movlw b'00000011' ; 1= Input, (RB0, RB1) -> Switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green, RB5 -> /TFT_POWER
0
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76 movwf TRISB
113
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77 movlw b'00101000' ; Init port
0
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78 movwf PORTB
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79
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80 movlw b'10011010' ; 1= Input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
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81 movwf TRISC
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82 movlw b'00000000' ; Init port
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83 movwf PORTC
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84
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85 movlw b'00100000' ; 1= Input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
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86 movwf TRISD
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87 movlw b'00000000' ; Init port
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88 movwf PORTD
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89
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90 movlw b'00000000' ; 1= Input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware
0
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91 movwf TRISE
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92 movlw b'00110001' ; Init port
0
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93 movwf PORTE
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94
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95 movlw b'01111110' ; 1= Input, (RF1, RF2, RF3, RF4, RF5) -> Analog
0
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96 movwf TRISF
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97 movlw b'00000000' ; Init port
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98 movwf PORTF
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99
113
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100 movlw b'00001110' ; 1= Input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
0
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101 movwf TRISG
113
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102 movlw b'00000001' ; Init port
0
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103 movwf PORTG
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104
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105 movlw b'00000000' ; 1= Input -> Data TFT_low
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106 movwf TRISH
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107 movlw b'00000000' ; Init port
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108 movwf PORTH
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109
120
e2f04bb2539c battery check in sleep
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110 movlw b'10011011' ; 1= Input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
0
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111 movwf TRISJ
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112 movlw b'00100000' ; Init port
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113 movwf PORTJ
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114
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115
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116 ; Timer 0
28
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117 movlw b'00000001' ; Timer0 with 1:4 prescaler
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118 ; movlw b'00001000' ; Timer0 with 1:1 prescaler
0
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119 movwf T0CON
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120
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121 ; Timer 1 - Button hold-down timer
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122 movlw b'10001100' ; 32768Hz clock source, 1:1 Prescaler -> ; 30,51757813µs/bit in TMR1L:TMR1H
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123 movwf T1CON
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124
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125 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
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126
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127 ; RTCC
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128 movlw 0x55
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129 movwf EECON2
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130 movlw 0xAA
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131 movwf EECON2
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132 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
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133 bsf RTCCFG,RTCPTR1
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134 bsf RTCCFG,RTCPTR0
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135 bsf RTCCFG,RTCEN ; Module enable
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136 bsf RTCCFG,RTCOE ; Output enable
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137 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J
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138 movwf PADCFG1
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139 movlw b'11000100'
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140 movwf ALRMCFG ; 1 second alarm
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141 movlw d'1'
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142 movwf ALRMRPT ; Alarm repeat counter
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143 movlw 0x55
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144 movwf EECON2
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145 movlw 0xAA
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146 movwf EECON2
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147 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
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148
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149 banksel common
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150 ; A/D Converter
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151 movlw b'00011000' ; power off ADC, select AN6
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152 movwf ADCON0
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153 movlw b'00100000' ; 2.048V Vref+
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154 movwf ADCON1
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155 movlw b'10001101' ; Right justified
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156 movwf ADCON2
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157
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158
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159 ;init serial port1 (TRISC6/7)
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160 movlw b'00001000' ; BRG16=1
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161 movwf BAUDCON1
204
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162 ; movlw b'00100100' ; BRGH=1, SYNC=0
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163 ; movwf TXSTA1
0
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164 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD)
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165 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0,16% Error to 19200 BAUD)
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166 clrf SPBRGH1 ;
204
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167 ; movlw b'10010000'
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168 ; movwf RCSTA1
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169
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170 clrf RCSTA1
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171 clrf TXSTA1 ; UART disable
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172 bcf PORTC,6 ; TX hard to GND
0
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173
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174 ;init serial port2 (TRISG2)
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175 banksel BAUDCON2
113
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176 movlw b'00100000' ; BRG16=0 ; inverted for IR
0
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177 movwf BAUDCON2
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178 movlw b'00100000' ; BRGH=0, SYNC=0
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179 movwf TXSTA2
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180 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
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181 movwf SPBRG2
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182 clrf SPBRGH2
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183 movlw b'10010000'
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184 movwf RCSTA2
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185 banksel common
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186
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187 ; Timer3 for IR-RX Timeout
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188 clrf T3GCON ; Reset Timer3 Gate Control register
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189 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
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190 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
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191 ; 30,51757813µs/bit in TMR3L:TMR3H
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192 movwf T3CON
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193
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194 ; SPI Module(s)
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195 ; SPI2: External Flash
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196 movlw b'00110000'
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197 movwf SSP2CON1
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198 movlw b'00000000'
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199 movwf SSP2STAT
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200 ; ->0,25MHz Bit clock @1MHz mode (Eco)
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201 ; -> 4MHz Bit clock @16MHz mode (Normal)
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202 ; -> 16MHz Bit clock @64MHz mode (Fastest)
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203
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204 ; MSSP1 Module: I2C Master
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205 movlw b'00101000' ; I2C Master Mode
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206 movwf SSP1CON1
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207 movlw b'00000000'
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208 movwf SSP1CON2
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209 movlw 0x27
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210 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
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211
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212 ; PWM Module(s)
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213 ; PWM1 for LED dimming
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214 movlw b'00001100'
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215 movwf CCP1CON
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216 movlw b'00000001'
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217 movwf PSTR1CON ; Pulse steering disabled
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218 movlw d'255'
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219 movwf PR2 ; Period
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220 ; 255 is max brightness (300mW)
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221 clrf CCPR1L ; Duty cycle
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222 clrf CCPR1H ; Duty cycle
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223 movlw T2CON_NORMAL
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224 movwf T2CON
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225
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226 ; Timer5 for ISR-independent wait routines
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227 clrf T5GCON ; Reset Timer5 Gate Control register
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228 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
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229 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
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230 ; 30,51757813µs/bit in TMR5L:TMR5H
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231 movwf T5CON
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232
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233 ; Timer7 for 62,5ms Interrupt (Sensor states)
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234 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
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235 clrf T7GCON ; Reset Timer7 Gate Control register
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236 ; movlw b'10001101' ; 1:1 Prescaler -> 2seconds@32768Hz, not synced
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237 movlw b'10001001' ; 1:1 Prescaler -> 2seconds@32768Hz, synced
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238 movwf T7CON
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239 clrf TMR7L
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240 movlw .248
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241 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms
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242
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243 banksel common
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244 ; Interrupts
50
ec4d8503ec45 NEW: user-selectable color schemes
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245 movlw b'11010000'
0
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246 movwf INTCON
77
131e6dd9e201 BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
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247 movlw b'00001000' ; BIT7=1: Pullup for PORTB disabled
0
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248 movwf INTCON2
77
131e6dd9e201 BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
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249 movlw b'00000000'
0
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250 movwf INTCON3
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251 movlw b'00000001' ; Bit0: TMR1
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252 movwf PIE1
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253 movlw b'00000010' ; Bit1: TMR3
heinrichsweikamp
parents:
diff changeset
254 movwf PIE2
heinrichsweikamp
parents:
diff changeset
255 movlw b'00000000' ; Bit1: TMR5
heinrichsweikamp
parents:
diff changeset
256 movwf PIE5
heinrichsweikamp
parents:
diff changeset
257 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
heinrichsweikamp
parents:
diff changeset
258 movwf PIE3
heinrichsweikamp
parents:
diff changeset
259 movlw b'00001000' ; Bit3: TMR7
heinrichsweikamp
parents:
diff changeset
260 movwf PIE5
heinrichsweikamp
parents:
diff changeset
261
heinrichsweikamp
parents:
diff changeset
262 bsf power_sw1
58
c4876e4b3563 startup with 1.6 hardware
heinrichsweikamp
parents: 50
diff changeset
263 btfss power_sw1
c4876e4b3563 startup with 1.6 hardware
heinrichsweikamp
parents: 50
diff changeset
264 bra $-4
0
heinrichsweikamp
parents:
diff changeset
265 bsf power_sw2
58
c4876e4b3563 startup with 1.6 hardware
heinrichsweikamp
parents: 50
diff changeset
266 btfss power_sw2
c4876e4b3563 startup with 1.6 hardware
heinrichsweikamp
parents: 50
diff changeset
267 bra $-4
0
heinrichsweikamp
parents:
diff changeset
268
204
heinrichsweikamp
parents: 200
diff changeset
269 movlw d'2'
heinrichsweikamp
parents: 200
diff changeset
270 movwf speed_setting ; Normal
heinrichsweikamp
parents: 200
diff changeset
271
heinrichsweikamp
parents: 200
diff changeset
272
0
heinrichsweikamp
parents:
diff changeset
273 return
heinrichsweikamp
parents:
diff changeset
274
heinrichsweikamp
parents:
diff changeset
275 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
276 global speed_eco
heinrichsweikamp
parents:
diff changeset
277 speed_eco:
heinrichsweikamp
parents:
diff changeset
278 movlw d'1'
heinrichsweikamp
parents:
diff changeset
279 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
280 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
281 return
heinrichsweikamp
parents:
diff changeset
282 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
283 global speed_normal
heinrichsweikamp
parents:
diff changeset
284 speed_normal:
heinrichsweikamp
parents:
diff changeset
285 movlw d'2'
heinrichsweikamp
parents:
diff changeset
286 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
287 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
288 return
heinrichsweikamp
parents:
diff changeset
289 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
290 global speed_fastest
heinrichsweikamp
parents:
diff changeset
291 speed_fastest:
heinrichsweikamp
parents:
diff changeset
292 movlw d'3'
heinrichsweikamp
parents:
diff changeset
293 movff WREG,speed_setting ; Bank-independent
heinrichsweikamp
parents:
diff changeset
294 ; Done in ISR
heinrichsweikamp
parents:
diff changeset
295 return
heinrichsweikamp
parents:
diff changeset
296 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
297
heinrichsweikamp
parents:
diff changeset
298 END