Mercurial > public > hwos_code

annotate src/rtc.asm @ 493:dd84cdd6c2d2

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
2.15 rc
author heinrichsweikamp
date Thu, 30 Mar 2017 11:57:54 +0200
parents 8dfb93e80338
children b7eb98dbd800
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
heinrichsweikamp
parents:
diff changeset
3 ; File rtc.asm
heinrichsweikamp
parents:
diff changeset
4 ;
heinrichsweikamp
parents:
diff changeset
5 ;
heinrichsweikamp
parents:
diff changeset
6 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
7 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
8 ; HISTORY
heinrichsweikamp
parents:
diff changeset
9 ; 2011-08-08 : [mH] moving from OSTC code
heinrichsweikamp
parents:
diff changeset
10
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 265
diff changeset
11 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
12 #include "math.inc"
heinrichsweikamp
parents:
diff changeset
13
heinrichsweikamp
parents:
diff changeset
14 sensors CODE
heinrichsweikamp
parents:
diff changeset
15
heinrichsweikamp
parents:
diff changeset
16 global rtc_init
heinrichsweikamp
parents:
diff changeset
17 rtc_init:
heinrichsweikamp
parents:
diff changeset
18 movlw .1
heinrichsweikamp
parents:
diff changeset
19 movwf secs
heinrichsweikamp
parents:
diff changeset
20 movlw .59
heinrichsweikamp
parents:
diff changeset
21 movwf mins
heinrichsweikamp
parents:
diff changeset
22 movlw .12
heinrichsweikamp
parents:
diff changeset
23 movwf hours
490
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 463
diff changeset
24 movlw .29
0
heinrichsweikamp
parents:
diff changeset
25 movwf day
265
7eddbcb27109 1.76 release
heinrichsweikamp
parents: 147
diff changeset
26 movlw .3
0
heinrichsweikamp
parents:
diff changeset
27 movwf month
490
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 463
diff changeset
28 movlw .17
0
heinrichsweikamp
parents:
diff changeset
29 movwf year
463
2c58631d5229 minor cleanups
heinrichsweikamp
parents: 275
diff changeset
30 ; rcall rtc_set_rtc ; writes mins,sec,hours,day,month and year to rtc module
2c58631d5229 minor cleanups
heinrichsweikamp
parents: 275
diff changeset
31 ; return
0
heinrichsweikamp
parents:
diff changeset
32
heinrichsweikamp
parents:
diff changeset
33 global rtc_set_rtc
heinrichsweikamp
parents:
diff changeset
34 rtc_set_rtc:
heinrichsweikamp
parents:
diff changeset
35 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
heinrichsweikamp
parents:
diff changeset
36 movlw 0x55
heinrichsweikamp
parents:
diff changeset
37 movwf EECON2
heinrichsweikamp
parents:
diff changeset
38 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
39 movwf EECON2
heinrichsweikamp
parents:
diff changeset
40 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
heinrichsweikamp
parents:
diff changeset
41 bsf RTCCFG,RTCPTR1
heinrichsweikamp
parents:
diff changeset
42 bsf RTCCFG,RTCPTR0 ; year
heinrichsweikamp
parents:
diff changeset
43 movff year,WREG
heinrichsweikamp
parents:
diff changeset
44 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
45 movwf RTCVALL ; year
heinrichsweikamp
parents:
diff changeset
46 movwf RTCVALH ; dummy write
heinrichsweikamp
parents:
diff changeset
47 movff day,WREG
heinrichsweikamp
parents:
diff changeset
48 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
49 movwf RTCVALL ;day
heinrichsweikamp
parents:
diff changeset
50 movff month,WREG
heinrichsweikamp
parents:
diff changeset
51 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
52 movwf RTCVALH ;month
heinrichsweikamp
parents:
diff changeset
53 movff hours,WREG
heinrichsweikamp
parents:
diff changeset
54 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
55 movwf RTCVALL ;hours
heinrichsweikamp
parents:
diff changeset
56 movlw d'0'
heinrichsweikamp
parents:
diff changeset
57 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
58 movwf RTCVALH ;weekday
heinrichsweikamp
parents:
diff changeset
59 movff secs,WREG
heinrichsweikamp
parents:
diff changeset
60 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
61 movwf RTCVALL ;secs
heinrichsweikamp
parents:
diff changeset
62 movff mins,WREG
heinrichsweikamp
parents:
diff changeset
63 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
heinrichsweikamp
parents:
diff changeset
64 movwf RTCVALH ;minutes
heinrichsweikamp
parents:
diff changeset
65 movlw 0x55
heinrichsweikamp
parents:
diff changeset
66 movwf EECON2
heinrichsweikamp
parents:
diff changeset
67 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
68 movwf EECON2
heinrichsweikamp
parents:
diff changeset
69 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
heinrichsweikamp
parents:
diff changeset
70 banksel common
heinrichsweikamp
parents:
diff changeset
71 return
heinrichsweikamp
parents:
diff changeset
72
heinrichsweikamp
parents:
diff changeset
73 rtc_dec2bcd:
heinrichsweikamp
parents:
diff changeset
74 banksel temp1
heinrichsweikamp
parents:
diff changeset
75 movwf temp1 ; Input in dec
heinrichsweikamp
parents:
diff changeset
76 setf temp2 ; 10s
heinrichsweikamp
parents:
diff changeset
77
heinrichsweikamp
parents:
diff changeset
78 rtc_dec2bcd2:
heinrichsweikamp
parents:
diff changeset
79 incf temp2,F ; Count 10's
heinrichsweikamp
parents:
diff changeset
80 movlw d'10'
heinrichsweikamp
parents:
diff changeset
81 subwf temp1,F
heinrichsweikamp
parents:
diff changeset
82 btfss STATUS,N
heinrichsweikamp
parents:
diff changeset
83 bra rtc_dec2bcd2
heinrichsweikamp
parents:
diff changeset
84 movlw d'10'
heinrichsweikamp
parents:
diff changeset
85 addwf temp1,F ; 1s
heinrichsweikamp
parents:
diff changeset
86 swapf temp2,W ; swap to bit 7-4 -> WREG
heinrichsweikamp
parents:
diff changeset
87 addwf temp1,W ; Result in BCD
heinrichsweikamp
parents:
diff changeset
88 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
heinrichsweikamp
parents:
diff changeset
89 return
heinrichsweikamp
parents:
diff changeset
90
heinrichsweikamp
parents:
diff changeset
91 END