annotate src/rtc.asm @ 608:d866684249bd

work on 2.99 stable
author heinrichsweikamp
date Mon, 07 Jan 2019 21:13:43 +0100
parents ca4556fb60b9
children c40025d8e750
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 598
diff changeset
3 ; File rtc.asm ## V2.98c
0
heinrichsweikamp
parents:
diff changeset
4 ;
heinrichsweikamp
parents:
diff changeset
5 ;
heinrichsweikamp
parents:
diff changeset
6 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
7 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
8 ; HISTORY
heinrichsweikamp
parents:
diff changeset
9 ; 2011-08-08 : [mH] moving from OSTC code
heinrichsweikamp
parents:
diff changeset
10
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 265
diff changeset
11 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
12 #include "math.inc"
heinrichsweikamp
parents:
diff changeset
13
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 598
diff changeset
14 rtc CODE
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
15
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
16 ;=============================================================================
0
heinrichsweikamp
parents:
diff changeset
17
heinrichsweikamp
parents:
diff changeset
18 global rtc_init
heinrichsweikamp
parents:
diff changeset
19 rtc_init:
heinrichsweikamp
parents:
diff changeset
20 movlw .1
heinrichsweikamp
parents:
diff changeset
21 movwf secs
heinrichsweikamp
parents:
diff changeset
22 movlw .59
heinrichsweikamp
parents:
diff changeset
23 movwf mins
heinrichsweikamp
parents:
diff changeset
24 movlw .12
heinrichsweikamp
parents:
diff changeset
25 movwf hours
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 598
diff changeset
26 movlw .2
0
heinrichsweikamp
parents:
diff changeset
27 movwf day
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 598
diff changeset
28 movlw .12
0
heinrichsweikamp
parents:
diff changeset
29 movwf month
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 598
diff changeset
30 movlw .17
0
heinrichsweikamp
parents:
diff changeset
31 movwf year
463
2c58631d5229 minor cleanups
heinrichsweikamp
parents: 275
diff changeset
32 ; rcall rtc_set_rtc ; writes mins,sec,hours,day,month and year to rtc module
2c58631d5229 minor cleanups
heinrichsweikamp
parents: 275
diff changeset
33 ; return
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
34
0
heinrichsweikamp
parents:
diff changeset
35 global rtc_set_rtc
heinrichsweikamp
parents:
diff changeset
36 rtc_set_rtc:
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
37 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
38 movlw 0x55
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
39 movwf EECON2
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
40 movlw 0xAA
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
41 movwf EECON2
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
42 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
43 bsf RTCCFG,RTCPTR1
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
44 bsf RTCCFG,RTCPTR0 ; year
0
heinrichsweikamp
parents:
diff changeset
45 movff year,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
46 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
0
heinrichsweikamp
parents:
diff changeset
47 movwf RTCVALL ; year
heinrichsweikamp
parents:
diff changeset
48 movwf RTCVALH ; dummy write
heinrichsweikamp
parents:
diff changeset
49 movff day,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
50 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
51 movwf RTCVALL ;day
0
heinrichsweikamp
parents:
diff changeset
52 movff month,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
53 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
54 movwf RTCVALH ;month
0
heinrichsweikamp
parents:
diff changeset
55 movff hours,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
56 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
57 movwf RTCVALL ;hours
0
heinrichsweikamp
parents:
diff changeset
58 movlw d'0'
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
59 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
60 movwf RTCVALH ;weekday
0
heinrichsweikamp
parents:
diff changeset
61 movff secs,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
62 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
63 movwf RTCVALL ;secs
0
heinrichsweikamp
parents:
diff changeset
64 movff mins,WREG
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
65 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
66 movwf RTCVALH ;minutes
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
67 movlw 0x55
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
68 movwf EECON2
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
69 movlw 0xAA
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
70 movwf EECON2
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
71 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
0
heinrichsweikamp
parents:
diff changeset
72 banksel common
heinrichsweikamp
parents:
diff changeset
73 return
heinrichsweikamp
parents:
diff changeset
74
heinrichsweikamp
parents:
diff changeset
75 rtc_dec2bcd:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
76 banksel lo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
77 movwf lo ; Input in decimal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
78 setf hi ; 10s
0
heinrichsweikamp
parents:
diff changeset
79 rtc_dec2bcd2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
80 incf hi,F ; Count 10's
0
heinrichsweikamp
parents:
diff changeset
81 movlw d'10'
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
82 subwf lo,F
0
heinrichsweikamp
parents:
diff changeset
83 btfss STATUS,N
heinrichsweikamp
parents:
diff changeset
84 bra rtc_dec2bcd2
heinrichsweikamp
parents:
diff changeset
85 movlw d'10'
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
86 addwf lo,F ; 1s
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
87 swapf hi,W ; swap to bit 7-4 -> WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
88 addwf lo,W ; Result in BCD
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 560
diff changeset
89 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM
0
heinrichsweikamp
parents:
diff changeset
90 return
heinrichsweikamp
parents:
diff changeset
91
heinrichsweikamp
parents:
diff changeset
92 END