annotate src/isr.asm @ 611:cd7991986ace

undo BOR bit
author heinrichsweikamp
date Wed, 09 Jan 2019 21:28:53 +0100
parents d866684249bd
children 1ad0531e9078
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1 ;=============================================================================
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2 ;
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3 ; File isr.asm REFACTORED VERSION V2.99f
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4 ;
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5 ; INTERUPT subroutines
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code.
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11
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653a3ab08062 rename into hwOS
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12 #include "hwos.inc"
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13 #include "shared_definitions.h" ; Mailbox from/to p2_deco.c
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14 #include "ms5541.inc"
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15 #include "adc_lightsensor.inc"
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16 #include "eeprom_rs232.inc"
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17
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18 ;=============================================================================
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19
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20 extern start
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21
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22 isr_high CODE 0x0008 ; high priority interrupts
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23 bra HighInt
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24 nop
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25 nop
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26 nop
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27 nop
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28 nop
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29 nop
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30 bra HighInt
0
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31
604
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32 isr_low CODE 0x00018 ; low priority interrupts
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33 ; *** low priority interrupts not used
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34 retfie FAST ; restores BSR, STATUS and WREG
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35
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36 HighInt:
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37 movff PRODL,isr_prod+0
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38 movff PRODH,isr_prod+1
0
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39
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40 ; Buttons
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41 btfsc PIR1,TMR1IF ; timer 1 INT (button hold-down timer)
582
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42 rcall timer1int
604
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43 btfsc INTCON,INT0IF ; buttons
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44 rcall isr_switch_right
604
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45 btfsc INTCON3,INT1IF ; buttons
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46 rcall isr_switch_left
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47
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48 ; IR/S8 link timer int
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49 btfsc PIR3,RC2IF ; UART 2
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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50 rcall isr_uart2 ; IR/S8 link
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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51 btfsc PIR2,TMR3IF ; timer 3
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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52 rcall isr_timer3 ; IR-Link timeout
113
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53
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54 ; Pressure sensor and others
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55 btfsc PIR5,TMR7IF ; timer 7
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56 rcall isr_tmr7 ; every 62.5ms
113
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57
582
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58 ; RTCC
604
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59 btfsc PIR3,RTCCIF ; real-time-clock interrupt
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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60 rcall isr_rtcc ; may return in bank common!
0
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61
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62 movff isr_prod+1,PRODH
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63 movff isr_prod+0,PRODL
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64 retfie FAST ; restores BSR, STATUS and WREG
0
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65
410
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66 isr_set_speed_to_normal:
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67 ; Set speed to normal
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68 movlw b'01110010'
604
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69 movwf OSCCON ; 16 MHz INTOSC
582
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70 movlw b'00000000'
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71 movwf OSCTUNE ; 4x PLL disable (bit 6) - only works with 8 or 16 MHz (=32 or 64 MHz)
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72 movlw T2CON_NORMAL
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73 movwf T2CON
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74 btfss OSCCON,HFIOFS
604
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75 bra $-2 ; wait until clock is stable
582
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76 return
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
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77
604
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78 isr_dimm_tft: ; adjust until max_CCPR1L=CCPR1L
582
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79 banksel common
604
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80 btfsc tft_is_dimming ; ignore while dimming
582
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81 return
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82 banksel isr_backup
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83 movf max_CCPR1L,W
604
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84 cpfsgt CCPR1L ; CCPR1L > max_CCPR1L ?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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85 bra isr_dimm_tft2 ; NO - dimm up
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
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86 ; dimm down
582
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87 decf CCPR1L,F ; -1
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88 return
410
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89 isr_dimm_tft2:
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90 movf max_CCPR1L,W
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91 sublw ambient_light_min_eco
604
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92 cpfsgt CCPR1L ; CCPR1L > max_CCPR1L-ambient_light_min_eco ?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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93 bra isr_dimm_tft3 ; NO - dimm up slow
582
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94 ; dimm up faster
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95 movlw .10
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96 addwf CCPR1L,F
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
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97 isr_dimm_tft3:
582
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98 incf CCPR1L,F ; +1
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99 return
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100 nop
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101 nop ; block flash here
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
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102
604
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103 isr_restore CODE 0x00080 ; restore first flash page from EEPROM
410
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104 restore_flash_0x00080:
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105 goto restore_flash
410
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106
604
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107 isr_routines ; CODE
0
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108 ;=============================================================================
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109
604
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110 isr_uart2: ; IR/S8 link
582
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111 banksel RCREG2
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112 movf RCREG2,W
604
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113 bcf RCSTA2,CREN ; clear receiver status
582
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114 bsf RCSTA2,CREN
b455b31ce022 work on 2.97 stable
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115 banksel isr_backup
604
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116 incf ir_s8_counter,F ; increase counter
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117 movff ir_s8_counter,isr1_temp ; copy
582
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118 dcfsnz isr1_temp,F
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119 movwf ir_s8_buffer+.0
b455b31ce022 work on 2.97 stable
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120 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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121 movwf ir_s8_buffer+.1
b455b31ce022 work on 2.97 stable
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parents: 570
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122 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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parents: 570
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123 movwf ir_s8_buffer+.2
b455b31ce022 work on 2.97 stable
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124 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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125 movwf ir_s8_buffer+.3
b455b31ce022 work on 2.97 stable
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126 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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127 movwf ir_s8_buffer+.4
b455b31ce022 work on 2.97 stable
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128 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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129 movwf ir_s8_buffer+.5
b455b31ce022 work on 2.97 stable
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130 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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131 movwf ir_s8_buffer+.6
b455b31ce022 work on 2.97 stable
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132 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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133 movwf ir_s8_buffer+.7
b455b31ce022 work on 2.97 stable
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134 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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135 movwf ir_s8_buffer+.8
b455b31ce022 work on 2.97 stable
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136 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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137 movwf ir_s8_buffer+.9
b455b31ce022 work on 2.97 stable
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138 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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139 movwf ir_s8_buffer+.10
b455b31ce022 work on 2.97 stable
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140 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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141 movwf ir_s8_buffer+.11
b455b31ce022 work on 2.97 stable
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142 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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143 movwf ir_s8_buffer+.12
b455b31ce022 work on 2.97 stable
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144 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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parents: 570
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145 movwf ir_s8_buffer+.13
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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146 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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147 movwf ir_s8_buffer+.14
b455b31ce022 work on 2.97 stable
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148 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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149 movwf ir_s8_buffer+.15
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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150 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
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parents: 570
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151 movwf ir_s8_buffer+.16
b455b31ce022 work on 2.97 stable
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parents: 570
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152 dcfsnz isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
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153 movwf ir_s8_buffer+.17
113
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154
604
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155 clrf TMR3L ; preload timer
582
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parents: 570
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156 movlw .253
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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157 movwf TMR3H
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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158 bsf T3CON,TMR3ON ; (re)start timeout counter
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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159 return
0
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160
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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161 isr_timer3: ; IR/S8 link timeout
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
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162 bcf T3CON,TMR3ON ; stop timer 3
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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163 banksel isr_backup ; select bank 0 for ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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164 movlw .15
604
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165 cpfseq ir_s8_counter ; got exactly 15 bytes?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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166 bra isr_timer3_1 ; NO - test for 16bytes
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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167 bra isr_timer3_ir ; YES - got 15 bytes, compute local checksum
0
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168 isr_timer3_1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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169 movlw .16
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
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170 cpfseq ir_s8_counter ; got exactly 16 bytes?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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171 bra isr_timer3_2 ; NO - test for 17 bytes
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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172 tstfsz ir_s8_buffer+.15 ; YES - last byte = 0x00 ?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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173 bra isr_timer3_exit ; No - exit
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
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174 bra isr_timer3_ir ; YES - got 16 bytes, compute local checksum
113
heinrichsweikamp
parents: 50
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175 isr_timer3_2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
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176 movlw .17
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
177 cpfseq ir_s8_counter ; got exactly 17 bytes?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
178 bra isr_timer3_exit ; NO - exit
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
179 bra isr_timer3_s8 ; YES - S8 data
0
heinrichsweikamp
parents:
diff changeset
180
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
181 isr_timer3_ir: ; IR input
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
182 movff ir_s8_buffer+.0,PRODL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
183 clrf PRODH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
184 movf ir_s8_buffer+.1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
185 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
186 movf ir_s8_buffer+.2,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
187 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
188 movf ir_s8_buffer+.3,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
189 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
190 movf ir_s8_buffer+.4,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
191 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
192 movf ir_s8_buffer+.5,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
193 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
194 movf ir_s8_buffer+.6,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
195 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
196 movf ir_s8_buffer+.7,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
197 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
198 movf ir_s8_buffer+.8,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
199 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
200 movf ir_s8_buffer+.9,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
201 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
202 movf ir_s8_buffer+.10,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
203 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
204 movf ir_s8_buffer+.11,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
205 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
206 movf ir_s8_buffer+.12,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
207 rcall isr_timer3_checksum
0
heinrichsweikamp
parents:
diff changeset
208
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
209 ; Compare checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
210 movf ir_s8_buffer+.13,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
211 cpfseq PRODL ; checksum ok?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
212 bra isr_timer3_exit ; NO - exit
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
213 movf ir_s8_buffer+.14,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
214 cpfseq PRODH ; checksum ok?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
215 bra isr_timer3_exit ; NO - exit
0
heinrichsweikamp
parents:
diff changeset
216
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
217 ; Checksum OK, copy results
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
218 movff ir_s8_buffer+.1,hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
219 movff ir_s8_buffer+.2,o2_mv_sensor1+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
220 movff ir_s8_buffer+.3,o2_mv_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
221 movff ir_s8_buffer+.4,o2_mv_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
222 movff ir_s8_buffer+.5,o2_mv_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
223 movff ir_s8_buffer+.6,o2_mv_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
224 movff ir_s8_buffer+.7,o2_mv_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
225 movff ir_s8_buffer+.8,o2_ppo2_sensor1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
226 movff ir_s8_buffer+.9,o2_ppo2_sensor2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
227 movff ir_s8_buffer+.10,o2_ppo2_sensor3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
228 movff ir_s8_buffer+.11,hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
229 movff ir_s8_buffer+.12,hud_battery_mv+1
0
heinrichsweikamp
parents:
diff changeset
230
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
231 movlw ir_timeout_value ; multiples of 62.5 ms
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
232 movwf ir_s8_timeout ; reload timeout
227
03946aa48fa5 NEW: Support for hwHUD without the LED module
heinrichsweikamp
parents: 204
diff changeset
233
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
234 banksel hud_status_byte
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
235 bsf hud_connection_ok ; set manually for hwHUD w/o the HUD module...
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
236 banksel isr_backup ; select bank 0 for ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
237
0
heinrichsweikamp
parents:
diff changeset
238 isr_timer3_exit:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
239 clrf ir_s8_counter ; clear pointer
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
240 bcf PIR2,TMR3IF ; clear flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
241 return
0
heinrichsweikamp
parents:
diff changeset
242
heinrichsweikamp
parents:
diff changeset
243 isr_timer3_checksum:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
244 addwf PRODL,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
245 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
246 addwfc PRODH,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
247 return
0
heinrichsweikamp
parents:
diff changeset
248
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
249 isr_timer3_s8: ; S8 input
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
250 movff ir_s8_buffer+.0,PRODL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
251 clrf PRODH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
252 movf ir_s8_buffer+.1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
253 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
254 movf ir_s8_buffer+.2,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
255 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
256 movf ir_s8_buffer+.3,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
257 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
258 movf ir_s8_buffer+.4,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
259 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
260 movf ir_s8_buffer+.5,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
261 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
262 movf ir_s8_buffer+.6,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
263 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
264 movf ir_s8_buffer+.7,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
265 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
266 movf ir_s8_buffer+.8,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
267 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
268 movf ir_s8_buffer+.9,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
269 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
270 movf ir_s8_buffer+.10,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
271 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
272 movf ir_s8_buffer+.11,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
273 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
274 movf ir_s8_buffer+.12,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
275 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
276 movf ir_s8_buffer+.13,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
277 rcall isr_timer3_checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
278 movf ir_s8_buffer+.14,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
279 rcall isr_timer3_checksum
113
heinrichsweikamp
parents: 50
diff changeset
280
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
281 ; Compare checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
282 movf ir_s8_buffer+.15,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
283 cpfseq PRODL ; checksum ok?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
284 bra isr_timer3_exit ; NO - exit
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
285 movf ir_s8_buffer+.16,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
286 cpfseq PRODH ; checksum ok?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
287 bra isr_timer3_exit ; NO - exit
113
heinrichsweikamp
parents: 50
diff changeset
288
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
289 ; Checksum OK, copy results
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
290 movff ir_s8_buffer+.3,hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
291 movff ir_s8_buffer+.13,hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
292 movff ir_s8_buffer+.14,hud_battery_mv+1
113
heinrichsweikamp
parents: 50
diff changeset
293
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
294 banksel common
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
295 btfsc new_s8_data_available ; =1: old data already processed?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
296 bra isr_timer3_skip ; NO - skip copying new results
113
heinrichsweikamp
parents: 50
diff changeset
297
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
298 movff ir_s8_buffer+.6,s8_rawdata_sensor1+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
299 movff ir_s8_buffer+.5,s8_rawdata_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
300 movff ir_s8_buffer+.4,s8_rawdata_sensor1+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
301 movff ir_s8_buffer+.9,s8_rawdata_sensor2+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
302 movff ir_s8_buffer+.8,s8_rawdata_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
303 movff ir_s8_buffer+.7,s8_rawdata_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
304 movff ir_s8_buffer+.12,s8_rawdata_sensor3+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
305 movff ir_s8_buffer+.11,s8_rawdata_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
306 movff ir_s8_buffer+.10,s8_rawdata_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
307 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
308 bsf new_s8_data_available ; set flag
268
29acdb601548 BUGFIX: Increase timing tolerance for S8 HUD (cR only)
heinrichsweikamp
parents: 236
diff changeset
309
29acdb601548 BUGFIX: Increase timing tolerance for S8 HUD (cR only)
heinrichsweikamp
parents: 236
diff changeset
310 isr_timer3_skip:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
311 banksel ir_s8_timeout
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
312 movlw ir_timeout_value ; multiples of 62.5ms
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
313 movwf ir_s8_timeout ; reload timeout
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
314 bra isr_timer3_exit ; exit
113
heinrichsweikamp
parents: 50
diff changeset
315
heinrichsweikamp
parents: 50
diff changeset
316
0
heinrichsweikamp
parents:
diff changeset
317 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
318
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
319 isr_tmr7: ; each 62.5ms
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
320 bcf PIR5,TMR7IF ; clear flag
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
321 banksel 0xF16 ; addresses F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM
469
heinrichsweikamp
parents: 453
diff changeset
322 movlw .248
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
323 movwf TMR7H ; rollover after 2048 cycles -> 62.5ms
0
heinrichsweikamp
parents:
diff changeset
324
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
325 banksel common
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
326 call get_analog_switches ; get analog readings
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
327 btfss INTCON3,INT1IE
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
328 bra isr_tmr7_a
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
329 btfsc analog_sw2_pressed
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
330 rcall isr_switch_left
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
331 isr_tmr7_a:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
332 banksel common
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
333 btfss INTCON,INT0IE
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
334 bra isr_tmr7_b
448
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
335 btfsc analog_sw1_pressed
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
336 rcall isr_switch_right
aadfe9f2edaf work on new battery options
heinrichsweikamp
parents: 410
diff changeset
337 isr_tmr7_b:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
338 banksel common
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
339 btfss no_sensor_int ; sensor interrupt (because it's addressed during sleep)?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
340 bra isr_tmr7_c ; NO - continue
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
341 banksel isr_backup ; YES - back to bank 0 ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
342 return
490
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
343 isr_tmr7_c:
8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
heinrichsweikamp
parents: 469
diff changeset
344 banksel isr_backup
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
345 movf max_CCPR1L,W ; dimm value
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
346 cpfseq CCPR1L ; = current PWM value?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
347 rcall isr_dimm_tft ; NO - adjust until max_CCPR1L=CCPR1L
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
348
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
349 banksel isr_backup
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
350 decfsz ir_s8_timeout,F ; IR data still valid?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
351 bra isr_tmr7_2 ; YES - continue
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
352 ; timeout, clear IR-Data
0
heinrichsweikamp
parents:
diff changeset
353
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
354 movlw ir_timeout_value ; multiples of 62.5ms
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
355 movwf ir_s8_timeout ; reload timeout
0
heinrichsweikamp
parents:
diff changeset
356
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
357 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
358 btfss analog_o2_input
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
359 bra isr_tmr7_1a ; always with normal ostc3 hardware
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
360 btfss s8_digital
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
361 bra isr_tmr7_2 ; only when digital
113
heinrichsweikamp
parents: 50
diff changeset
362 isr_tmr7_1a:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
363 clrf o2_mv_sensor1+0 ; S8/IR timeout clears all analog input readings to zero -> fallback will be triggered when sensor mode was used
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
364 clrf o2_mv_sensor1+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
365 clrf o2_mv_sensor2+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
366 clrf o2_mv_sensor2+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
367 clrf o2_mv_sensor3+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
368 clrf o2_mv_sensor3+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
369 banksel hud_battery_mv
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
370 clrf hud_battery_mv+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
371 clrf hud_battery_mv+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
372 banksel hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
373 clrf hud_status_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
374 clrf o2_ppo2_sensor1 ; for IR/S8 UD
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
375 clrf o2_ppo2_sensor2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
376 clrf o2_ppo2_sensor3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
377
570
c8ea60294175 react to external S8 HUD disconnect or failure in surface mode
heinrichsweikamp
parents: 565
diff changeset
378 banksel common
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
379 bsf new_s8_data_available ; set flag to update in surface mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
380
0
heinrichsweikamp
parents:
diff changeset
381 isr_tmr7_2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
382 banksel common
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
383 btfss no_sensor_int ; sensor interrupt (because it's addressed during sleep)?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
384 bra isr_sensor_state2 ; NO - continue
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
385 banksel isr_backup ; YES - back to Bank0 ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
386 return
0
heinrichsweikamp
parents:
diff changeset
387
heinrichsweikamp
parents:
diff changeset
388 isr_sensor_state2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
389 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
390 movff sensor_state_counter,WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
391 btfss WREG,0 ; every 1/4 second
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
392 bsf quarter_second_update ; set flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
393 banksel isr_backup ; back to Bank0 ISR data
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
394 movlw d'2' ; coding for normal speed
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
395 cpfseq cpu_speed_state ; CPU running on normal speed?
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
396 rcall isr_set_speed_to_normal ; NO - set CPU speed to normal
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
397
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
398 incf sensor_state_counter,F ; counts to eight for state machine
0
heinrichsweikamp
parents:
diff changeset
399
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
400 ; State 1: Clear flags and average registers, get temperature (51 us) and start pressure integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
401 ; State 2: Get pressure (51 us), start temperature integration (73.5 us) and calculate temperature compensated pressure (233 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
402 ; State 3: Get temperature (51 us) and start pressure integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
403 ; State 4: Get pressure (51 us), start temperature integration (73.5 us) and calculate temperature compensated pressure (233 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
404 ; State 5: Get temperature (51 us) and start pressure integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
405 ; State 6: Get pressure (51 us), start temperature integration (73.5 us) and calculate temperature compensated pressure (233 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
406 ; State 7: Get temperature (51 us) and start pressure integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
407 ; State 8: Get pressure (51 us), start temperature integration (73.5 us), calculate temperature compensated pressure (233 us) and build average for half-second update of temperature and pressure
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
408
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
409 movff sensor_state_counter,WREG ; WREG used as temp here...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
410 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
411 bra sensor_int_state1_plus_restart ; do State 1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
412 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
413 bra sensor_int_state2 ; do State 2
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
414 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
415 bra sensor_int_state1 ; do State 3
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
416 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
417 bra sensor_int_state2 ; do State 4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
418 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
419 bra sensor_int_state1 ; do State 5
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
420 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
421 bra sensor_int_state2 ; do State 6
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
422 dcfsnz WREG,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
423 bra sensor_int_state1 ; do State 7
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
424 ; bra sensor_int2_plus_average ; do State 8
0
heinrichsweikamp
parents:
diff changeset
425 ;sensor_int2_plus_average:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
426 ; First, do state2:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
427 call get_pressure_value ; state 2: get pressure (51 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
428 call get_temperature_start ; and start temperature integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
429 call calculate_compensation ; calculate temperature compensated pressure (27 us)
0
heinrichsweikamp
parents:
diff changeset
430 ; Build average
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
431 bcf STATUS,C ; clear carry bit
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
432 rrcf amb_pressure_avg+1 ; amb_pressure sum / 2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
433 rrcf amb_pressure_avg+0
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
434 bcf STATUS,C ; clear carry bit, twice
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
435 rrcf amb_pressure_avg+1 ; amb_pressure sum / 4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
436 rrcf amb_pressure_avg+0
0
heinrichsweikamp
parents:
diff changeset
437
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
438 movff amb_pressure_avg+1,amb_pressure+1 ; copy into actual register
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
439 movff amb_pressure_avg+0,amb_pressure+0
0
heinrichsweikamp
parents:
diff changeset
440
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
441 bcf STATUS,C
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
442 btfsc temperature_avg+1,7 ; copy sign bit to carry
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
443 bsf STATUS,C
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
444 rrcf temperature_avg+1 ; signed temperature /2
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
445 rrcf temperature_avg+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
446 bcf STATUS,C
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
447 btfsc temperature_avg+1,7 ; copy sign bit to carry
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
448 bsf STATUS,C
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
449 rrcf temperature_avg+1 ; signed temperature /4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
450 rrcf temperature_avg+0
0
heinrichsweikamp
parents:
diff changeset
451
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
452 movff temperature_avg+1,temperature+1 ; copy into actual register
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
453 movff temperature_avg+0,temperature+0
0
heinrichsweikamp
parents:
diff changeset
454
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
455 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
456 bcf temp_changed ; clear flag for temperature update
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
457 bcf pressure_refresh ; clear flag for pressure update
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
458 banksel isr_backup ; back to bank 0 ISR data
0
heinrichsweikamp
parents:
diff changeset
459
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
460 ; Temp changed?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
461 movf temperature+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
462 cpfseq last_temperature+0
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
463 bra isr_sensor_state2_2 ; YES
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
464 movf temperature+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
465 cpfseq last_temperature+1
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
466 bra isr_sensor_state2_2 ; YES
0
heinrichsweikamp
parents:
diff changeset
467
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
468 bra isr_sensor_state2_3 ; no change
0
heinrichsweikamp
parents:
diff changeset
469
heinrichsweikamp
parents:
diff changeset
470 isr_sensor_state2_2:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
471 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
472 bsf temp_changed ; YES
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
473 banksel isr_backup ; back to bank 0 ISR data
0
heinrichsweikamp
parents:
diff changeset
474 isr_sensor_state2_3:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
475 movff temperature+0,last_temperature+0 ; copy for compare
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
476 movff temperature+1,last_temperature+1
0
heinrichsweikamp
parents:
diff changeset
477
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
478 movf amb_pressure+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
479 cpfseq last_pressure+0
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
480 bra isr_sensor_state2_4 ; YES
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
481 movf amb_pressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
482 cpfseq last_pressure+1
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
483 bra isr_sensor_state2_4 ; YES
0
heinrichsweikamp
parents:
diff changeset
484
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
485 bra isr_sensor_state2_5 ; no change
0
heinrichsweikamp
parents:
diff changeset
486 isr_sensor_state2_4:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
487 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
488 bsf pressure_refresh ; YES
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
489 banksel isr_backup ; back to bank 0 ISR data
0
heinrichsweikamp
parents:
diff changeset
490 isr_sensor_state2_5:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
491 movff amb_pressure+0,last_pressure+0 ; copy for compare
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
492 movff amb_pressure+1,last_pressure+1
0
heinrichsweikamp
parents:
diff changeset
493
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
494 clrf sensor_state_counter ; reset state counter
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
495 banksel common ; flag2 is in bank 1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
496 btfss simulatormode_active ; are we in simulator mode?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
497 bra comp_air_pressure ; NO
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
498 bsf pressure_refresh ; always set pressure_refresh flag in simulator mode
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
499 banksel isr_backup ; back to bank 0 ISR data
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
500 movlw LOW d'1000' ; simulate 1000 mbar surface pressure
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
501 movwf last_surfpressure+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
502 movlw HIGH d'1000'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
503 movwf last_surfpressure+1
0
heinrichsweikamp
parents:
diff changeset
504
heinrichsweikamp
parents:
diff changeset
505 comp_air_pressure:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
506 banksel isr_backup ; back to bank 0 ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
507 movf last_surfpressure+0,W ; compensate air pressure
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
508 subwf amb_pressure+0,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
509 movwf rel_pressure+0 ; rel_pressure stores depth
0
heinrichsweikamp
parents:
diff changeset
510
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
511 movf last_surfpressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
512 subwfb amb_pressure+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
513 movwf rel_pressure+1
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
514 btfss STATUS,N ; is result below zero?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
515 bra sensor_int_state_exit ; NO
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
516 clrf rel_pressure+0 ; YES - do not display negative depths
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
517 clrf rel_pressure+1 ; e.g. when surface air pressure dropped during the dive
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
518 bra sensor_int_state_exit
0
heinrichsweikamp
parents:
diff changeset
519
heinrichsweikamp
parents:
diff changeset
520 sensor_int_state1_plus_restart:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
521 clrf amb_pressure_avg+0 ; pressure average registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
522 clrf amb_pressure_avg+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
523 clrf temperature_avg+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
524 clrf temperature_avg+1
0
heinrichsweikamp
parents:
diff changeset
525
heinrichsweikamp
parents:
diff changeset
526 sensor_int_state1:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
527 call get_temperature_value ; state 1: get temperature...
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
528 call get_pressure_start ; ...and start pressure integration
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
529 bra sensor_int_state_exit
0
heinrichsweikamp
parents:
diff changeset
530
heinrichsweikamp
parents:
diff changeset
531 sensor_int_state2:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
532 call get_pressure_value ; state 2: get pressure (51 us)...
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
533 call get_temperature_start ; ...and start temperature integration (73.5 us)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
534 call calculate_compensation ; .. and calculate temperature compensated pressure (233 us)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
535 ;bra sensor_int_state_exit
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
536
0
heinrichsweikamp
parents:
diff changeset
537 sensor_int_state_exit:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
538 rcall isr_restore_clock ; restore clock
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
539 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
540
0
heinrichsweikamp
parents:
diff changeset
541 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
542
heinrichsweikamp
parents:
diff changeset
543 isr_rtcc: ; each second
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
544 bcf PIR3,RTCCIF ; clear flag
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
545 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
546 bsf RTCCFG,RTCPTR1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
547 bsf RTCCFG,RTCPTR0 ; year
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
548 movff RTCVALL,year ; format is BCD
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
549 movff RTCVALH,day ; dummy read
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
550 movff RTCVALL,day ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
551 movff RTCVALH,month ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
552 movff RTCVALL,hours ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
553 movff RTCVALH,secs ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
554 movff RTCVALL,secs ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
555 movff RTCVALH,mins ; format is BCD
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
556 banksel isr_backup ; back to bank 0 ISR data
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
557
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
558 ; Convert BCD to DEC and set registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
559 movff mins, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
560 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
561 movff WREG,mins
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
562 movff secs, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
563 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
564 movff WREG,secs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
565 movff hours, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
566 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
567 movff WREG,hours
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
568 movff month, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
569 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
570 movff WREG,month
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
571 movff day, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
572 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
573 movff WREG,day
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
574 movff year, isr1_temp
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
575 rcall isr_rtcc_convert ; converts to dec with result in WREG
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
576 movff WREG,year
0
heinrichsweikamp
parents:
diff changeset
577
heinrichsweikamp
parents:
diff changeset
578 ; Place once/second tasks for ISR here (Be sure of the right bank!)
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
579 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
580 btfss sleepmode ; in sleepmode?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
581 call get_ambient_level ; NO - get ambient light level and set max_CCPR1L
0
heinrichsweikamp
parents:
diff changeset
582
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
583 rcall isr_battery_gauge ; add amount of battery consumption to battery_gauge:6
0
heinrichsweikamp
parents:
diff changeset
584
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
585 ; update uptime
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
586 banksel uptime+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
587 incf uptime+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
588 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
589 addwfc uptime+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
590 addwfc uptime+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
591 addwfc uptime+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
592
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
593 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
594 bsf onesecupdate ; a new second has begun
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
595 btfsc divemode ; in divemode?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
596 rcall isr_divemode_1sec ; YES - do some divemode stuff in bank common
0
heinrichsweikamp
parents:
diff changeset
597
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
598 btfss divemode ; in divemode?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
599 rcall isr_update_lastdive_time ; NO - update the last dive timer
453
b4f28ab23b87 NEW: Show Uptime (Time since last firmware boot) in information menu
heinrichsweikamp
parents: 451
diff changeset
600
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
601 tstfsz secs ; secs == 0 ?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
602 return ; NO - done
0
heinrichsweikamp
parents:
diff changeset
603
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
604 bsf oneminupdate ; a new minute has begun
0
heinrichsweikamp
parents:
diff changeset
605
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
606 btfss divemode ; in Divemode?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
607 rcall check_nofly_desat_time ; NO - so increase interval
0
heinrichsweikamp
parents:
diff changeset
608
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
609 ; Check if a new hour has just begun
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
610 tstfsz mins ; mins == 0 ?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
611 bra isr_rtcc2 ; NP
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
612 bsf onehourupdate ; YES - set flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
613
0
heinrichsweikamp
parents:
diff changeset
614 isr_rtcc2:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
615 banksel isr_backup ; back to bank 0 ISR data
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
616 return ; done
0
heinrichsweikamp
parents:
diff changeset
617
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
618 isr_update_lastdive_time: ; called every second when not in divemode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
619 ; update uptime
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
620 banksel lastdive_time+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
621 incf lastdive_time+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
622 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
623 addwfc lastdive_time+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
624 addwfc lastdive_time+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
625 addwfc lastdive_time+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
626 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
627 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
628
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
629 isr_battery_gauge:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
630 banksel isr_backup ; bank 0 ISR data
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
631 movlw current_sleepmode ; 100µA/3600 -> nAs (sleepmode current)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
632 movwf isr1_temp ; store value (low byte)
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
633 clrf isr2_temp ; high byte
0
heinrichsweikamp
parents:
diff changeset
634
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
635 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
636 btfss sleepmode ; in sleepmode?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
637 rcall isr_battery_gauge2 ; NO - compute current consumption value into isr1_temp and isr2_temp
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
638
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
639 banksel isr_backup ; bank 0 ISR data
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
640 movf isr1_temp,W ; 48 Bit add of isr1_temp and isr2_temp into battery_gauge:6
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
641 addwf battery_gauge+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
642 movf isr2_temp,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
643 addwfc battery_gauge+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
644 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
645 addwfc battery_gauge+2,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
646 addwfc battery_gauge+3,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
647 addwfc battery_gauge+4,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
648 addwfc battery_gauge+5,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
649 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
650
0
heinrichsweikamp
parents:
diff changeset
651 isr_battery_gauge2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
652 ; set consumption rate in nAs for an one second interval
0
heinrichsweikamp
parents:
diff changeset
653 ; Example:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
654 ; movlw LOW .55556 ; 0,2A/3600*1e9s = nAs
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
655 ; movwf isr1_temp ; low byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
656 ; movlw HIGH .55556 ; 0,2A/3600*1e9s = nAs
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
657 ; movwf isr2_temp ; high byte
0
heinrichsweikamp
parents:
diff changeset
658
heinrichsweikamp
parents:
diff changeset
659 ; Current consumption for LED backlight is 47*CCPR1L+272
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
660 movf CCPR1L,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
661 mullw current_backlight_multi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
662 movlw LOW current_backlight_offset
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
663 addwf PRODL,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
664 movlw HIGH current_backlight_offset
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
665 addwfc PRODH,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
666 movff PRODL,isr1_temp
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
667 movff PRODH,isr2_temp ; isr1_temp and isr2_temp hold value for backlight
0
heinrichsweikamp
parents:
diff changeset
668
heinrichsweikamp
parents:
diff changeset
669 ; Add current for CPU and GPU
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
670 ; cpu_speed_state=1: ECO (3.1mA -> 861nAs), =2: NORMAL (5.50mA -> 1528nAs) or =3: FASTEST (8.04mA -> 2233nAs)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
671 banksel isr_backup ; Bank0 ISR data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
672 movlw .1
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
673 cpfseq cpu_speed_state
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
674 bra isr_battery_gauge3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
675 movlw LOW current_speed_eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
676 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
677 movlw HIGH current_speed_eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
678 addwfc isr2_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
679 bra isr_battery_gauge5
0
heinrichsweikamp
parents:
diff changeset
680 isr_battery_gauge3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
681 movlw .2
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
682 cpfseq cpu_speed_state
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
683 bra isr_battery_gauge4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
684 movlw LOW current_speed_normal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
685 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
686 movlw HIGH current_speed_normal
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
687 addwfc isr2_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
688 bra isr_battery_gauge5
0
heinrichsweikamp
parents:
diff changeset
689 isr_battery_gauge4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
690 movlw LOW current_speed_fastest
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
691 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
692 movlw HIGH current_speed_fastest
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
693 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
694 isr_battery_gauge5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
695 ; Add current if IR receiver is on
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
696 btfss ir_power ; IR enabled?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
697 bra isr_battery_gauge6 ; NO
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
698 movlw LOW current_ir_receiver
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
699 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
700 movlw HIGH current_ir_receiver
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
701 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
702 isr_battery_gauge6:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
703 ; Add current for compass/accelerometer
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
704 btfss compass_enabled ; compass active?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
705 bra isr_battery_gauge7 ; NO
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
706 movlw LOW current_compass
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
707 addwf isr1_temp,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
708 movlw HIGH current_compass
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
709 addwfc isr2_temp,F
0
heinrichsweikamp
parents:
diff changeset
710 isr_battery_gauge7:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
711 return
0
heinrichsweikamp
parents:
diff changeset
712
heinrichsweikamp
parents:
diff changeset
713 isr_divemode_1sec:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
714 incf samplesecs,F ; "samplingrate" diving seconds done
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
715 decf samplesecs_value,W ; holds "samplingrate" value (minus 1 into WREG)
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
716 cpfsgt samplesecs ; done?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
717 bra isr_divemode_1sec2 ; NO
0
heinrichsweikamp
parents:
diff changeset
718
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
719 clrf samplesecs ; clear counter...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
720 bsf store_sample ; ...and set bit for profile storage
0
heinrichsweikamp
parents:
diff changeset
721 isr_divemode_1sec2:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
722 ; increase total divetime (regardless of start_dive_threshold)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
723 infsnz total_divetime_seconds+0,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
724 incf total_divetime_seconds+1,F ; total dive time (regardless of start_dive_threshold)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
725
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
726 btfss divemode2 ; displayed divetime is running?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
727 return ; NO (e.g. too shallow)
0
heinrichsweikamp
parents:
diff changeset
728
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
729 ; increase divetime registers (displayed dive time)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
730 incf divesecs,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
731 movlw d'59'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
732 cpfsgt divesecs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
733 bra isr_divemode_1sec2a
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
734
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
735 clrf divesecs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
736 bsf realdive ; this bit is always set (again) if the dive is longer then one minute
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
737 infsnz divemins+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
738 incf divemins+1,F ; increase divemins
0
heinrichsweikamp
parents:
diff changeset
739
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
740 isr_divemode_1sec2a:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
741 btfss FLAG_apnoe_mode ; are we in apnoe mode?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
742 return ; NO
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
743
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
744 incf apnoe_secs,F ; increase descent registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
745 movlw d'59'
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
746 cpfsgt apnoe_secs ; full minute?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
747 return ; NO
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
748 clrf apnoe_secs
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
749 incf apnoe_mins,F ; increase descent mins
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
750 return
0
heinrichsweikamp
parents:
diff changeset
751
heinrichsweikamp
parents:
diff changeset
752 ;=============================================================================
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
753 ; BCD to Binary conversion.
0
heinrichsweikamp
parents:
diff changeset
754 ; Input: isr1_temp = Value in BCD
heinrichsweikamp
parents:
diff changeset
755 ; Output WREG = value in binary.
heinrichsweikamp
parents:
diff changeset
756 isr_rtcc_convert:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
757 swapf isr1_temp, W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
758 andlw 0x0F ; W = tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
759 rlncf WREG, W ; W = 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
760 subwf isr1_temp, F ; 16*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
761 subwf isr1_temp, F ; 14*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
762 subwf isr1_temp, W ; 12*tens + ones - 2*tens
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
763 return
0
heinrichsweikamp
parents:
diff changeset
764
heinrichsweikamp
parents:
diff changeset
765 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
766
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
767 isr_switch_right:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
768 bcf INTCON,INT0IE ; disable INT0
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
769 banksel common ; flag1 is in bank 1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
770 btfss flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
771 bsf switch_right ; set flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
772 btfsc flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
773 bsf switch_left ; set flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
774 bra isr_switch_common ; continue...
0
heinrichsweikamp
parents:
diff changeset
775
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
776 isr_switch_left:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
777 bcf INTCON3,INT1IE ; disable INT1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
778 banksel common ; flag1 is in bank 1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
779 btfss flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
780 bsf switch_left ; set flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
781 btfsc flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
782 bsf switch_right ; set flag
0
heinrichsweikamp
parents:
diff changeset
783 isr_switch_common:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
784 ; load timer1 for first press
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
785 clrf TMR1L
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
786 movlw TMR1H_VALUE_FIRST ; in steps of 7.8125 ms
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
787 movwf TMR1H
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
788 bsf T1CON,TMR1ON ; start timer 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
789 banksel isr_backup ; select bank 0 for ISR data
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
790 bcf INTCON3,INT1IF ; clear flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
791 bcf INTCON,INT0IF ; clear flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
792 return
0
heinrichsweikamp
parents:
diff changeset
793
heinrichsweikamp
parents:
diff changeset
794 timer1int:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
795 bcf PIR1,TMR1IF ; clear flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
796 banksel common ; flag1 is in bank 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
797 bcf INTCON,INT0IF ; clear flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
798 bcf INTCON3,INT1IF ; clear flag
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
799 ; digital
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
800 btfss switch_left1 ; left button hold-down?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
801 bra timer1int_left ; YES
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
802 btfss switch_right2 ; right button hold-down?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
803 bra timer1int_right ; YES
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
804
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
805 ; Analog
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
806 btfsc analog_sw2_pressed ; left button hold-down?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
807 bra timer1int_left ; YES
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
808 btfsc analog_sw1_pressed ; right button hold-down?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
809 bra timer1int_right ; YES
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
810
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
811 ; No button hold-down, stop Timer 1
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
812 bcf T1CON,TMR1ON ; stop timer 1
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
813 bsf INTCON,INT0IE ; enable INT0
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
814 bsf INTCON3,INT1IE ; enable INT1
451
66049b6f2c0b speedup analog presses
heinrichsweikamp
parents: 448
diff changeset
815 return
0
heinrichsweikamp
parents:
diff changeset
816
heinrichsweikamp
parents:
diff changeset
817 timer1int_left:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
818 btfss flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
819 bsf switch_left ; (re-)set flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
820 btfsc flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
821 bsf switch_right ; (re-)set flag
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
822 bra timer1int_common ; continue
0
heinrichsweikamp
parents:
diff changeset
823 timer1int_right:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
824 btfss flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
825 bsf switch_right ; set flag
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
826 btfsc flip_screen ; 180° flipped?
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
827 bsf switch_left ; set flag
0
heinrichsweikamp
parents:
diff changeset
828 timer1int_common:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
829 ; load timer1 for next press
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
830 clrf TMR1L
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
831 movlw TMR1H_VALUE_CONT ; surface mode
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
832 btfsc divemode
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
833 movlw TMR1H_VALUE_CONT_DIVE ; sive mode
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
834 movwf TMR1H
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
835 return ; return from timer1int with timer1 kept running
0
heinrichsweikamp
parents:
diff changeset
836
heinrichsweikamp
parents:
diff changeset
837 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
838
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
839 check_nofly_desat_time: ; called every minute when not in divemode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
840 banksel int_O_desaturation_time
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
841 movf int_O_desaturation_time+0,W ; is Desat null ?
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
842 iorwf int_O_desaturation_time+1,W
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
843 bz check_nofly_desat_time_1 ; YES
0
heinrichsweikamp
parents:
diff changeset
844
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
845 ; int_O_desaturation_time is only computed while in start, surface mode, menue_tree or ghostwriter.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
846 ; So the ISR may clock surface_interval past the actual surface interval time. But TFT_surface_lastdive
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
847 ; will check int_O_desaturation_time and in case int_O_desaturation_time is zero it will not show
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
848 ; surface_interval but lastdive_time instead. So this glitch remains invisible.
0
heinrichsweikamp
parents:
diff changeset
849
147
fdd4e30846ae some cleanup
heinrichsweikamp
parents: 145
diff changeset
850 ; Increase surface interval timer
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
851 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
852 infsnz surface_interval+0,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
853 incf surface_interval+1,F
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
854 return ; done
0
heinrichsweikamp
parents:
diff changeset
855
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
856 check_nofly_desat_time_1:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
857 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
858 clrf surface_interval+0
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
859 clrf surface_interval+1 ; clear surface interval timer
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
860 return ; done
0
heinrichsweikamp
parents:
diff changeset
861
heinrichsweikamp
parents:
diff changeset
862 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
863
heinrichsweikamp
parents:
diff changeset
864 isr_restore_clock:
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
865 movff cpu_speed_request,cpu_speed_state ; acknowledge CPU speed request
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
866 banksel isr_backup
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
867 movlw d'1'
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
868 cpfseq cpu_speed_request
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
869 bra isr_restore_speed2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
870 ; Reset to eco
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
871 movlw b'00000000'
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
872 movwf OSCTUNE ; 4x PLL Ddsable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
873 movlw b'00110010'
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
874 movwf OSCCON ; 1 MHz INTOSC
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
875 movlw T2CON_ECO
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
876 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
877 bra isr_restore_exit
0
heinrichsweikamp
parents:
diff changeset
878 isr_restore_speed2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
879 movlw d'2'
608
d866684249bd work on 2.99 stable
heinrichsweikamp
parents: 604
diff changeset
880 cpfseq cpu_speed_request
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
881 bra isr_restore_speed3
0
heinrichsweikamp
parents:
diff changeset
882 ; Reset to normal
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
883 movlw b'01110010'
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
884 movwf OSCCON ; 16 MHz INTOSC
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
885 movlw b'00000000'
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
886 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
887 movlw T2CON_NORMAL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
888 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
889 bra isr_restore_exit
0
heinrichsweikamp
parents:
diff changeset
890 isr_restore_speed3:
heinrichsweikamp
parents:
diff changeset
891 ; Reset to fastest
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
892 movlw b'01110010' ; 16 MHz INTOSC
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
893 movwf OSCCON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
894 movlw b'01000000'
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
895 movwf OSCTUNE ; 4x PLL enable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
896 movlw T2CON_FASTEST
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
897 movwf T2CON
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
898 ;bra isr_restore_exit
0
heinrichsweikamp
parents:
diff changeset
899 isr_restore_exit:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
900 btfss OSCCON,HFIOFS
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
901 bra isr_restore_exit ; loop until PLL is stable
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
902 return
0
heinrichsweikamp
parents:
diff changeset
903
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
904
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
905 restore_flash: ; restore first flash page from EEPROM
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
906 banksel common
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
907 ; Start address in internal flash
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
908 movlw 0x00
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
909 movwf TBLPTRL
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
910 movwf TBLPTRH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
911 movwf TBLPTRU
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
912
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
913 movlw b'10010100' ; setup erase
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
914 rcall Write ; write
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
915
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
916 movlw .128
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
917 movwf lo ; byte counter
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
918 clrf EEADR
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
919 movlw .3
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
920 movwf EEADRH ; setup backup address
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
921
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
922 TBLRD*- ; dummy read to be in 128 byte block
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
923 restore_flash_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
924 call read_eeprom
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
925 incf EEADR,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
926 movff EEDATA,TABLAT ; put 1 byte
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
927 tblwt+* ; table write with pre-increment
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
928 decfsz lo,F ; 128 bytes done?
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
929 bra restore_flash_loop ; NO - loop
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
930
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
931 movlw b'10000100' ; setup writes
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
932 rcall Write ; write
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
933
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
934 reset ; done, reset CPU
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
935
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
936 Write:
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
937 movwf EECON1 ; type of memory to write in
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
938 movlw 0x55
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
939 movwf EECON2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
940 movlw 0xAA
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
941 movwf EECON2
604
ca4556fb60b9 bump to 2.99beta, work on 3.00 stable
heinrichsweikamp
parents: 582
diff changeset
942 bsf EECON1,WR ; write
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
943 nop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
944 nop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
945 return
410
d3087a8ed7e1 BUGFIX: Fix rare issue after battery change (OSTC3 did not start properly)
heinrichsweikamp
parents: 378
diff changeset
946
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 570
diff changeset
947 END