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1 ;=============================================================================
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2 ;
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3 ; File mcp.asm
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4 ;
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5 ; Basic routines for RX circuity
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6 ;
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7 ; Copyright (c) 2012, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2012-08-12 : [mH] Creation
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11
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12
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13 #include "ostc3.inc"
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14 #include "wait.inc"
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15
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16 mcp_writebyte_1st macro char
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17 movlw char
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18 rcall mcp_write_one_byte
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19 endm
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20
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21 mcp_writebyte_2nd macro char
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22 movlw char
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23 rcall mcp_write_one_byte2
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24 endm
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25
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26 ; Writes mcp_temp+0 to config reg
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27 mcp_write_config macro char
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28 movlw char
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29 rcall mcp_write_config_reg
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30 endm
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31
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32 mcp code
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33
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34 mcp_write_one_byte:
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35 movwf mcp_temp+0 ; save one byte
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36 bcf TRISG,0 ; CLK output
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37 nop
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38 bcf mcp_clk ; clk=0
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39 bsf mcp_ncs ; cs=1
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40 nop
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41 bcf mcp_ncs ; cs=0
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42 bcf TRISB,3 ; mcp_lf_data output
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43 movlw .8
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44 movwf mcp_temp+1 ; Bit counter
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45 mcp_write_one_byte_loop:
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46 btfss mcp_temp+0,7
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47 bcf mcp_lf_data
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48 btfsc mcp_temp+0,7
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49 bsf mcp_lf_data
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50 bsf mcp_clk ; clk=1
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51 rlncf mcp_temp+0,F ; shift byte left no carry
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52 bcf mcp_clk ; clk=0
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53 decfsz mcp_temp+1,F ; 8Bit done?
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54 bra mcp_write_one_byte_loop ; Not yet...
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55 return
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56
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57 mcp_write_one_byte2:
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58 movwf mcp_temp+0 ; save one byte
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59 movlw .8
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60 movwf mcp_temp+1 ; Bit counter
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61 mcp_write_one_byte_loop2:
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62 btfss mcp_temp+0,7
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63 bcf mcp_lf_data
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64 btfsc mcp_temp+0,7
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65 bsf mcp_lf_data
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66 bsf mcp_clk ; clk=1
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67 rlncf mcp_temp+0,F ; shift byte left no carry
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68 bcf mcp_clk ; clk=0
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69 decfsz mcp_temp+1,F ; 8Bit done?
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70 bra mcp_write_one_byte_loop2; Not yet...
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71 bsf TRISB,3 ; mcp_lf_data input again
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72 bsf mcp_ncs ; cs=1
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73 bsf TRISG,0 ; CLK input
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74 return
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75
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76 mcp_readbyte:
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77 bcf TRISG,0 ; CLK output
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78 nop
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79 bcf mcp_clk ; clk=0
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80 bcf mcp_ncs ; cs=0
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81 movlw .7
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82 movwf mcp_temp+1 ; Bit counter
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83 nop
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84 nop
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85 mcp_readloop:
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86 bsf mcp_clk ; clk=1
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87 bcf mcp_clk ; clk=0
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88 decfsz mcp_temp+1,F ; 7 Bit done?
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89 bra mcp_readloop ; Not yet...
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90
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91 movlw .8
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92 movwf mcp_temp+1 ; Bit counter
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93 mcp_readloop2:
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94 bsf mcp_clk ; clk=1
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95 bcf mcp_clk ; clk=0
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96 btfss mcp_lf_data
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97 bcf mcp_temp+0,7
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98 btfsc mcp_lf_data
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99 bsf mcp_temp+0,7
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100 rlncf mcp_temp+0 ; MSB first
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101 decfsz mcp_temp+1,F ; 8 Bit done?
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102 bra mcp_readloop2 ; Not yet...
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103
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104 ; Dummy clk for parity bit
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105 bsf mcp_clk ; clk=1
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106 nop
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107 bcf mcp_clk ; clk=0
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108 bsf mcp_ncs ; cs=1
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109 bsf TRISG,0 ; CLK input
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110 return
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111
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112 mcp_write_config_reg: ; Writes mcp_temp+0 to config #WREG
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113 movwf mcp_temp+2 ; Save config#
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114 bcf TRISG,0 ; CLK output
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115 clrf mcp_temp+3 ; for parity
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116 bcf mcp_clk ; clk=0
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117 bsf mcp_ncs ; cs=1
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118 nop
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119 bcf mcp_ncs ; cs=0
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120 bcf TRISB,3 ; mcp_lf_data output
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121 bsf mcp_lf_data
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122 bsf mcp_clk ; clk=1
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123 bcf mcp_clk ; clk=0
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124 bsf mcp_clk ; clk=1
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125 bcf mcp_clk ; clk=0
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126 bsf mcp_clk ; clk=1
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127 bcf mcp_clk ; clk=0 ; Write command done.
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128
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129 ; Now, 4Bit register address
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130 movlw .4
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131 movwf mcp_temp+1 ; Bit counter
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132 mcp_write_config_reg1:
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133 btfss mcp_temp+2,3
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134 bcf mcp_lf_data
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135 btfsc mcp_temp+2,3
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136 bsf mcp_lf_data
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137 bsf mcp_clk ; clk=1
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138 rlncf mcp_temp+2,F ; shift byte left no carry
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139 bcf mcp_clk ; clk=0
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140 decfsz mcp_temp+1,F ; 4Bit done?
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141 bra mcp_write_config_reg1 ; Not yet...
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142
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143 ; 8Bit data
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144 movlw .8
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145 movwf mcp_temp+1 ; Bit counter
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146 mcp_write_config_reg2:
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147 btfss mcp_temp+0,7
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148 bcf mcp_lf_data
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149 btfsc mcp_temp+0,7
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150 bsf mcp_lf_data
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151 btfsc mcp_temp+0,7
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152 incf mcp_temp+3,F ; count 1's...
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153 bsf mcp_clk ; clk=1
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154 rlncf mcp_temp+0,F ; shift byte left no carry
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155 bcf mcp_clk ; clk=0
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156 decfsz mcp_temp+1,F ; 8Bit done?
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157 bra mcp_write_config_reg2 ; Not yet...
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158
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159 ; 1bit parity
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160 btfss mcp_temp+3,0
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161 bsf mcp_lf_data ; Set row parity bit
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162 btfsc mcp_temp+3,0
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163 bcf mcp_lf_data ; clear row parity bit
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164 bsf mcp_clk ; clk=1
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165 bcf mcp_clk ; clk=0 ; Parity bit done.
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166
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167 bsf TRISB,3 ; mcp_lf_data input again
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168 bsf mcp_ncs ; cs=1
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169 bsf TRISG,0 ; CLK input
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170 return
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171
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172 global mcp_reset
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173 mcp_reset: ; reset RX chip# (Normal mode)
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174 ; Make sure row parity bit is correct
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175 ; yyyaaaa01234567P
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176 ; yyy: Command
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177 ; aaaa: Address
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178 ; 0-7: Data
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179 ; P: Parity bit. Set/Clear that 0-7+P are odd number of ones
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180 ; Current config:
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181 banksel buffer
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182 movlw b'10100100' ; Config0: LCZ disabled, Wakeup => High = 2ms, Low = 2ms
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183 movwf buffer+0
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184 movlw b'00000000' ; Config1: +20pF LCX Normal mode
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185 ; movlw b'01000000' ; Config1: +20pF LCX carrier out mode
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186 movwf buffer+1
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187 movlw b'00000000' ; Config2: +25pF LCY
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188 movwf buffer+2
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189 movlw b'00000000' ; Config3
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190 movwf buffer+3
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191 movlw b'00000000' ; Config4
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192 movwf buffer+4
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193 ; movlw b'00001111' ; Config5 33%
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194 ; movlw b'00101111' ; Config5 14%
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195 movlw b'10011111' ; Config5 60%
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196 movwf buffer+5
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197 bra mcp_reset_common
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198
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199 global mcp_reset_rssi
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200 mcp_reset_rssi: ; reset RX chip# for RSSI mode
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201 ; Make sure row parity bit is correct
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202 ; yyyaaaa01234567P
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203 ; yyy: Command
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204 ; aaaa: Address
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205 ; 0-7: Data
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206 ; P: Parity bit. Set/Clear that 0-7+P are odd number of ones
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207 ; Current config:
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208 banksel buffer
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209 movlw b'10101000' ; Config0: LCZ disabled, Wakeup => High = 2ms, Low = 2ms
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210 movwf buffer+0
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211 movlw b'10000000' ; Config1: +20pF LCX and RSSI Mode
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212 movwf buffer+1
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213 movlw b'00000000' ; Config2: +25pF LCY
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214 movwf buffer+2
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215 movlw b'00000000' ; Config3
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216 movwf buffer+3
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217 movlw b'00000000' ; Config4
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218 movwf buffer+4
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219 movlw b'11010000' ; Config5 60%
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220 movwf buffer+5
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221 mcp_reset_common:
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222 banksel TRISB
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223 bcf TRISB,2
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224 bcf mcp_ncs ; CS=1
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225 nop
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226 bsf mcp_power ; Power-up
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227 nop
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228 btfss mcp_power
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229 bra mcp_reset_common
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230 WAITMS .10
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231 ; Compute column parity byte
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232 banksel buffer
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233 movf buffer+0,W
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234 xorwf buffer+1,W
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235 xorwf buffer+2,W
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236 xorwf buffer+3,W
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237 xorwf buffer+4,W
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238 xorwf buffer+5,W
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239 xorlw 0xFF
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240 movwf buffer+6 ; <- Column parity byte
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241 banksel mcp_temp+0
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242
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243 mcp_writebyte_1st b'10100000' ; Reset Command
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244 mcp_writebyte_2nd b'00000000' ; Dummy byte
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245
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246 mcp_writebyte_1st b'00100000' ; Clamp off
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247 mcp_writebyte_2nd b'00000000' ; Dummy byte
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248
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249 movff buffer+0,mcp_temp+0 ; Data byte
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250 mcp_write_config .0
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251 movff buffer+1,mcp_temp+0 ; Data byte
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252 mcp_write_config .1
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253 movff buffer+2,mcp_temp+0 ; Data byte
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254 mcp_write_config .2
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255 movff buffer+3,mcp_temp+0 ; Data byte
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256 mcp_write_config .3
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257 movff buffer+4,mcp_temp+0 ; Data byte
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258 mcp_write_config .4
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259 movff buffer+5,mcp_temp+0 ; Data byte
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260 mcp_write_config .5
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261 movff buffer+6,mcp_temp+0 ; Data byte (Column parity byte)
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262 mcp_write_config .6
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263
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264 ; mcp_writebyte_1st b'11000000' ; Read from Config0
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265 ; mcp_writebyte_2nd b'00000000' ; Dummy clks + Odd Parity Bit (Bit0)
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266 ; call mcp_readbyte ; read into mcp_temp+0
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267 bsf INTCON3,INT3IE ; Enable INT3
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268 bsf INTCON2,INTEDG3 ; INT3 on rising edge
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269
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270 ; Setup Timer 0
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271 movlw TMR0H_VALUE
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272 movwf TMR0H
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273 bcf INTCON,TMR0IF ; Clear flag
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274 clrf TMR0L
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275 return
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276
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277 global mcp_sleep
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278 mcp_sleep:
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279 bcf INTCON3,INT3IE ; Disable INT3
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280 bcf mcp_power ; RX off
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281 btfsc mcp_power
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282 bra $-4
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283 return
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284
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285
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0
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286
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287 END
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