annotate src/eeprom_rs232.asm @ 2:ab8a7c3f1db0

battery warning levels, max. brightnes setting
author heinrichsweikamp
date Sun, 05 May 2013 15:37:24 +0200
parents 11d4fc797f74
children f3062a611eef
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
heinrichsweikamp
parents:
diff changeset
3 ; File eeprom_rs232.asm
heinrichsweikamp
parents:
diff changeset
4 ;
heinrichsweikamp
parents:
diff changeset
5 ; Internal EEPROM, RS232
heinrichsweikamp
parents:
diff changeset
6 ;
heinrichsweikamp
parents:
diff changeset
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
8 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
9 ; HISTORY
heinrichsweikamp
parents:
diff changeset
10 ; 2011-08-06 : [mH] moving from OSTC code
heinrichsweikamp
parents:
diff changeset
11
heinrichsweikamp
parents:
diff changeset
12 #include "ostc3.inc"
heinrichsweikamp
parents:
diff changeset
13 #include "start.inc"
heinrichsweikamp
parents:
diff changeset
14 #include "tft.inc"
heinrichsweikamp
parents:
diff changeset
15 #include "wait.inc"
heinrichsweikamp
parents:
diff changeset
16 #include "strings.inc"
heinrichsweikamp
parents:
diff changeset
17 #include "convert.inc"
heinrichsweikamp
parents:
diff changeset
18
heinrichsweikamp
parents:
diff changeset
19 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
20 eeprom code 0xF00000+0x10
heinrichsweikamp
parents:
diff changeset
21 ; Skip SERIAL number. Should not be overwritten.
heinrichsweikamp
parents:
diff changeset
22 global eeprom_serial_save, eeprom_opt_backup
heinrichsweikamp
parents:
diff changeset
23 eeprom_serial_save res 2
heinrichsweikamp
parents:
diff changeset
24 eeprom_opt_backup res 0x3E
heinrichsweikamp
parents:
diff changeset
25
heinrichsweikamp
parents:
diff changeset
26 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
27 basic CODE
heinrichsweikamp
parents:
diff changeset
28
heinrichsweikamp
parents:
diff changeset
29 global write_int_eeprom_1
heinrichsweikamp
parents:
diff changeset
30 write_int_eeprom_1:
heinrichsweikamp
parents:
diff changeset
31 movwf EEADR
heinrichsweikamp
parents:
diff changeset
32 bra write_eeprom ; writes and "returns" after write
heinrichsweikamp
parents:
diff changeset
33
heinrichsweikamp
parents:
diff changeset
34 global read_int_eeprom_1
heinrichsweikamp
parents:
diff changeset
35 read_int_eeprom_1:
heinrichsweikamp
parents:
diff changeset
36 movwf EEADR
heinrichsweikamp
parents:
diff changeset
37 bra read_eeprom ; reads and "returns" after write
heinrichsweikamp
parents:
diff changeset
38
heinrichsweikamp
parents:
diff changeset
39 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
40 ; reads from internal eeprom
heinrichsweikamp
parents:
diff changeset
41 ; Input: EEADRH:EEADR = EEPROM address.
heinrichsweikamp
parents:
diff changeset
42 ; Output: EEDATA.
heinrichsweikamp
parents:
diff changeset
43 ; Trashed: NONE.
heinrichsweikamp
parents:
diff changeset
44 global read_eeprom
heinrichsweikamp
parents:
diff changeset
45 read_eeprom:
heinrichsweikamp
parents:
diff changeset
46 bcf EECON1,EEPGD
heinrichsweikamp
parents:
diff changeset
47 bcf EECON1,CFGS
heinrichsweikamp
parents:
diff changeset
48 bsf EECON1,RD
heinrichsweikamp
parents:
diff changeset
49 return
heinrichsweikamp
parents:
diff changeset
50
heinrichsweikamp
parents:
diff changeset
51 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
52 ; writes into internal eeprom
heinrichsweikamp
parents:
diff changeset
53 ; Input: EEADRH:EEADR = EEPROM address.
heinrichsweikamp
parents:
diff changeset
54 ; EEDATA = byte to write.
heinrichsweikamp
parents:
diff changeset
55 ; Trashed: WREG.
heinrichsweikamp
parents:
diff changeset
56 global write_eeprom
heinrichsweikamp
parents:
diff changeset
57 write_eeprom:
heinrichsweikamp
parents:
diff changeset
58 bcf EECON1,EEPGD
heinrichsweikamp
parents:
diff changeset
59 bcf EECON1,CFGS
heinrichsweikamp
parents:
diff changeset
60 bsf EECON1,WREN
heinrichsweikamp
parents:
diff changeset
61
heinrichsweikamp
parents:
diff changeset
62 bcf INTCON,GIE ; even the RTC will be delayed for the next 5 instructions...
heinrichsweikamp
parents:
diff changeset
63 movlw 0x55
heinrichsweikamp
parents:
diff changeset
64 movwf EECON2
heinrichsweikamp
parents:
diff changeset
65 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
66 movwf EECON2
heinrichsweikamp
parents:
diff changeset
67 bsf EECON1,WR
heinrichsweikamp
parents:
diff changeset
68 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
heinrichsweikamp
parents:
diff changeset
69
heinrichsweikamp
parents:
diff changeset
70 write_eep2:
heinrichsweikamp
parents:
diff changeset
71 btfsc EECON1,WR
heinrichsweikamp
parents:
diff changeset
72 bra write_eep2 ; wait about 4ms...
heinrichsweikamp
parents:
diff changeset
73 bcf EECON1,WREN
heinrichsweikamp
parents:
diff changeset
74 return
heinrichsweikamp
parents:
diff changeset
75
heinrichsweikamp
parents:
diff changeset
76 global disable_ir
heinrichsweikamp
parents:
diff changeset
77 disable_ir:
heinrichsweikamp
parents:
diff changeset
78 banksel TXSTA2
heinrichsweikamp
parents:
diff changeset
79 clrf TXSTA2
heinrichsweikamp
parents:
diff changeset
80 clrf RCSTA2
heinrichsweikamp
parents:
diff changeset
81 banksel common
heinrichsweikamp
parents:
diff changeset
82 bcf ir_power ; IR off
heinrichsweikamp
parents:
diff changeset
83 return
heinrichsweikamp
parents:
diff changeset
84
heinrichsweikamp
parents:
diff changeset
85 global enable_ir
heinrichsweikamp
parents:
diff changeset
86 enable_ir:
heinrichsweikamp
parents:
diff changeset
87 ;init serial port2 (TRISG2)
heinrichsweikamp
parents:
diff changeset
88 banksel TXSTA2
heinrichsweikamp
parents:
diff changeset
89 movlw b'00100000' ; BRGH=0, SYNC=0
heinrichsweikamp
parents:
diff changeset
90 movwf TXSTA2
heinrichsweikamp
parents:
diff changeset
91 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
heinrichsweikamp
parents:
diff changeset
92 movwf SPBRG2
heinrichsweikamp
parents:
diff changeset
93 clrf SPBRGH2
heinrichsweikamp
parents:
diff changeset
94 movlw b'10010000'
heinrichsweikamp
parents:
diff changeset
95 movwf RCSTA2
heinrichsweikamp
parents:
diff changeset
96 banksel common
heinrichsweikamp
parents:
diff changeset
97 bsf ir_power ; Power-up IR
heinrichsweikamp
parents:
diff changeset
98 btfss ir_power
heinrichsweikamp
parents:
diff changeset
99 bra $-6
heinrichsweikamp
parents:
diff changeset
100 return
heinrichsweikamp
parents:
diff changeset
101
heinrichsweikamp
parents:
diff changeset
102 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
103 global enable_rs232
heinrichsweikamp
parents:
diff changeset
104 enable_rs232:
heinrichsweikamp
parents:
diff changeset
105 bcf TRISC,6 ; Output
heinrichsweikamp
parents:
diff changeset
106 bsf TRISC,7 ; Input
heinrichsweikamp
parents:
diff changeset
107 call speed_normal ; 16MHz
heinrichsweikamp
parents:
diff changeset
108 enable_rs232_2:
heinrichsweikamp
parents:
diff changeset
109 movlw T2CON_NORMAL
heinrichsweikamp
parents:
diff changeset
110 cpfseq T2CON
heinrichsweikamp
parents:
diff changeset
111 bra enable_rs232_2 ; Wait until speed is normal
heinrichsweikamp
parents:
diff changeset
112 ;init serial port1 (TRISC6/7)
heinrichsweikamp
parents:
diff changeset
113 clrf RCSTA1
heinrichsweikamp
parents:
diff changeset
114 clrf TXSTA1
heinrichsweikamp
parents:
diff changeset
115 movlw b'00001000' ; BRG16=1
heinrichsweikamp
parents:
diff changeset
116 movwf BAUDCON1
heinrichsweikamp
parents:
diff changeset
117 movlw b'00100100' ; BRGH=1, SYNC=0
heinrichsweikamp
parents:
diff changeset
118 movwf TXSTA1
heinrichsweikamp
parents:
diff changeset
119 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0,79% Error to 115200 BAUD)
heinrichsweikamp
parents:
diff changeset
120 movwf SPBRG1
heinrichsweikamp
parents:
diff changeset
121 clrf SPBRGH1
heinrichsweikamp
parents:
diff changeset
122 movlw b'10010000'
heinrichsweikamp
parents:
diff changeset
123 movwf RCSTA1
heinrichsweikamp
parents:
diff changeset
124 return
heinrichsweikamp
parents:
diff changeset
125
heinrichsweikamp
parents:
diff changeset
126 global disable_rs232
heinrichsweikamp
parents:
diff changeset
127 disable_rs232:
heinrichsweikamp
parents:
diff changeset
128 clrf RCSTA1
heinrichsweikamp
parents:
diff changeset
129 clrf TXSTA1 ; UART disable
heinrichsweikamp
parents:
diff changeset
130 bsf TRISC,6 ; Input
heinrichsweikamp
parents:
diff changeset
131 bsf TRISC,7 ; Input
heinrichsweikamp
parents:
diff changeset
132 return
heinrichsweikamp
parents:
diff changeset
133
heinrichsweikamp
parents:
diff changeset
134 global rs232_wait_tx
heinrichsweikamp
parents:
diff changeset
135 rs232_wait_tx:
heinrichsweikamp
parents:
diff changeset
136 ; btfss RCSTA1,SPEN ; Transmitter active?
heinrichsweikamp
parents:
diff changeset
137 ; return ; No, return!
heinrichsweikamp
parents:
diff changeset
138
heinrichsweikamp
parents:
diff changeset
139 btfsc TXSTA1,TRMT ; Transmit Shift Register empty?
heinrichsweikamp
parents:
diff changeset
140 return ; Yes, return!
heinrichsweikamp
parents:
diff changeset
141
heinrichsweikamp
parents:
diff changeset
142 btfss TXSTA,TRMT ; RS232 Busy?
heinrichsweikamp
parents:
diff changeset
143 bra rs232_wait_tx ; yes, wait...
heinrichsweikamp
parents:
diff changeset
144 return ; Done.
heinrichsweikamp
parents:
diff changeset
145
heinrichsweikamp
parents:
diff changeset
146 global rs232_get_byte
heinrichsweikamp
parents:
diff changeset
147 rs232_get_byte:
heinrichsweikamp
parents:
diff changeset
148 bcf PIR1,RCIF ; clear flag
heinrichsweikamp
parents:
diff changeset
149 bcf rs232_recieve_overflow ; clear flag
heinrichsweikamp
parents:
diff changeset
150 clrf uart1_temp
heinrichsweikamp
parents:
diff changeset
151 clrf uart2_temp
heinrichsweikamp
parents:
diff changeset
152 rs232_get_byte2:
heinrichsweikamp
parents:
diff changeset
153 btfsc PIR1,RCIF ; data arrived?
heinrichsweikamp
parents:
diff changeset
154 return
heinrichsweikamp
parents:
diff changeset
155 ; bra rs232_get_byte3
heinrichsweikamp
parents:
diff changeset
156
heinrichsweikamp
parents:
diff changeset
157 decfsz uart2_temp,F
heinrichsweikamp
parents:
diff changeset
158 bra rs232_get_byte2
heinrichsweikamp
parents:
diff changeset
159 decfsz uart1_temp,F
heinrichsweikamp
parents:
diff changeset
160 bra rs232_get_byte2
heinrichsweikamp
parents:
diff changeset
161 ; timeout occoured (about 20ms)
heinrichsweikamp
parents:
diff changeset
162 bsf rs232_recieve_overflow ; set flag
heinrichsweikamp
parents:
diff changeset
163 ;rs232_get_byte3:
heinrichsweikamp
parents:
diff changeset
164 bcf RCSTA1,CREN ; Clear receiver status
heinrichsweikamp
parents:
diff changeset
165 bsf RCSTA1,CREN
heinrichsweikamp
parents:
diff changeset
166 return ; and return anyway
heinrichsweikamp
parents:
diff changeset
167
heinrichsweikamp
parents:
diff changeset
168 END